154a17cb1STang Yun ping1. modify "ddrbin_param.txt", choose ddr frequency, uart info. 254a17cb1STang Yun ping2. run "ddrbin_tool" with argument 1: ddrbin_param.txt, argument 2: ddr bin file. 354a17cb1STang Yun ping like: ./ddrbin_tool ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 454a17cb1STang Yun ping 554a17cb1STang Yun pingsupport following chip: 6*2820321cSZhihuan HePX30: ddr bin version should be released later than V1.11. Support modify uart info only. The ddr bin version V1.12 and later support DDR 2t info modification, only DDR3 support. 7*2820321cSZhihuan HeRK1808: ddr bin version should be released later than V1.03. Support modify uart info and ddr frequency. ddr freq should be one of 333,400,533,666,786,933. The ddr bin version V1.03 and later support DDR 2t info modification, only DDR2/DDR3/DDR4 support. 8*2820321cSZhihuan HeRK322x: ddr bin version should be released later than V1.08. Support modify uart info and ddr frequency. These is no limit to ddr frequency. The ddr bin version V1.09 and later support DDR 2t info modification, only DDR2/DDR3 support. 9*2820321cSZhihuan HeRK322xh: ddr bin version should be released later than V1.14. Support modify uart info only. The ddr bin version V1.16 and later support DDR 2t info modification, only DDR3 support. 10*2820321cSZhihuan HeRK3288: ddr bin version should be released later than V1.07. Support modify uart info only. The ddr bin version V1.08 and later support DDR 2t info modification, only DDR3 support. 11*2820321cSZhihuan HeRK3308: ddr bin version should be released later than V1.28. Support modify uart info and ddr frequency. ddr freq should be one of 225,294,393,451,589. The ddr bin version V1.29 and later support DDR 2t info modification, only DDR2/DDR3 support. 12*2820321cSZhihuan HeRK3326: ddr bin version should be released later than V1.11. Support modify uart info only. The ddr bin version V1.12 and later support DDR 2t info modification, only DDR3 support. 13*2820321cSZhihuan HeRK3368: ddr bin version should be released later than V2.04. Support modify uart info and ddr frequency. These is no limit to ddr frequency. The ddr bin version V2.05 and later support DDR 2t info modification, only DDR3 support. 14*2820321cSZhihuan HeRK3328: ddr bin version should be released later than V1.14. Support modify uart info only. The ddr bin version V1.16 and later support DDR 2t info modification, only DDR3 support. 1554a17cb1STang Yun pingRK3399: ddr bin version should be released later than V1.20. Support modify uart info only. 16*2820321cSZhihuan HeRK3399PRO NPU: ddr bin version should be released later than V1.03. Support modify uart info and ddr frequency. ddr freq should be one of 333,400,533,666,786,933. The ddr bin version V1.03 and later support DDR 2t info modification, only DDR2/DDR3/DDR4 support. 1754a17cb1STang Yun ping 1854a17cb1STang Yun pingddrbin_param.txt: 1954a17cb1STang Yun pingstart tag: keep default value. Do not modify it. 20*2820321cSZhihuan Heddr2_freq: ddr2 frequency, unit:MHz. 21*2820321cSZhihuan Help2_freq: lpddr2 frequency, unit:MHz. 22*2820321cSZhihuan Heddr3_freq: ddr3 frequency, unit:MHz. 23*2820321cSZhihuan Help3_freq: lpddr3 frequency, unit:MHz. 24*2820321cSZhihuan Heddr4_freq: ddr4 frequency, unit:MHz. 25*2820321cSZhihuan Help4_freq: lpddr4 frequency, unit:MHz. 2654a17cb1STang Yun ping 27*2820321cSZhihuan HeIf ddr*_freq/lp*_freq is no value, it's frequency will keep the same with the ddr bin frequency. 28558a25b2STang Yun ping 2954a17cb1STang Yun pinguart id：uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 30558a25b2STang Yun pinguart iomux：uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 31558a25b2STang Yun pingOr 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 3254a17cb1STang Yun pinguart baudrate：uart baudrate should be 115200 or 1500000. 33558a25b2STang Yun ping 34*2820321cSZhihuan HeIf uart id/iomux/baudrate is no value, uart info will keep the same with ddr bin config. 35*2820321cSZhihuan He 36*2820321cSZhihuan Heddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 37*2820321cSZhihuan HeIf 'ddr_2t' is no value, ddr_2t info will keep the same with ddr bin config.