186251429SZhihuan Hefunction 1: modify ddr.bin file from ddrbin_param.txt. 2612e733eSZhihuan He 1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want. 386251429SZhihuan He If want to keep items default, please keep these items blank. 41f5c20ccSYouMin Chen 2) run 'ddrbin_tool.py' with argument 1: chip_name, argument 2: ddrbin_param.txt, argument 3: ddr bin file. 51f5c20ccSYouMin Chen like: ./ddrbin_tool.py px30 ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 6612e733eSZhihuan He 786251429SZhihuan Hefunction 2: get ddr.bin file config to gen_param.txt file 886251429SZhihuan He If want to get ddrbin file config, please run like that: 91f5c20ccSYouMin Chen ./ddrbin_tool.py px30 -g gen_param.txt px30_ddr_333MHz_v1.15.bin 1086251429SZhihuan He The config will show in gen_param.txt. 1154a17cb1STang Yun ping 1286251429SZhihuan HeThe detail information as following: 1354a17cb1STang Yun ping 1486251429SZhihuan He* support ddrbin version 156f34a9d1SZhihuan He The 'X' means not support change those parameters by tool. 166dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 176dab7052SYouMin Chen | platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT | ddr2/3/4, lp2/3 Vref | 186dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 196dab7052SYouMin Chen | RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X | X | 206dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 219dcea43dSZhihuan He | PX30/RK3326 | V1.11 | X | X | V1.12 | X | X | X | X | X | 226dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 236dab7052SYouMin Chen | RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | X | 246dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 256dab7052SYouMin Chen | RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | X | 266dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 276dab7052SYouMin Chen | RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | X | 286dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 296dab7052SYouMin Chen | RK3288 | V1.11 | X | X | V1.11 | X | X | X | X | X | 306dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 316dab7052SYouMin Chen | RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X | X | 326dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 336dab7052SYouMin Chen | RK3308S | V2.05 | V2.05 | V2.05 | V2.05 | V2.05 | X | X | X | X | 346dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 356dab7052SYouMin Chen | RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | X | 366dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 376dab7052SYouMin Chen | RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | X | 386dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 396dab7052SYouMin Chen | RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | X | 406dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 416dab7052SYouMin Chen | RK3399PRO NPU | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | X | 426dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 436dab7052SYouMin Chen | RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | X | 446dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 456dab7052SYouMin Chen | RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | V1.19 | 466dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 476dab7052SYouMin Chen | RK3588 | V1.00 | V1.00 | X | V1.00 | V1.00 | V1.00 | X | X | X | 486dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 496dab7052SYouMin Chen | RK3528 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.08 | 506dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 516dab7052SYouMin Chen | RK3562 | X | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.05 | 526dab7052SYouMin Chen +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 539dcea43dSZhihuan He | RV1106/RV1103 | V1.10 | V1.10 | V1.10 | V1.10 | V1.10 | X | X | X | X | 549dcea43dSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 55*6348802dSWesley Yao | RV1126B/BP | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.00 | 56*6348802dSWesley Yao +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 576f34a9d1SZhihuan He 586f34a9d1SZhihuan He| function | platform and ddrbin version | 59bac3cde4SZhihuan He| ------------------------------------- | ------------------------------------------ | 606f34a9d1SZhihuan He| first scan channel/channel mask | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 616f34a9d1SZhihuan He| stride type | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 62*6348802dSWesley Yao| ext_temp_ref | RK356x V1.16/RK3528 V1.07/RK1808 V1.06/RV1126B V1.00 | 636f34a9d1SZhihuan He| link_ecc_en | Null | 64*6348802dSWesley Yao| per_bank_ref_en | RK3588 V1.09/RV1126B V1.00 | 65*6348802dSWesley Yao| derate_en | RK3588 V1.09/RK356x V1.19/RK3528 V1.07/RV1126B V1.00 | 666f34a9d1SZhihuan He| auto_precharge_en | Null | 676f34a9d1SZhihuan He| res_space_remap_portion | RK3588 V1.09 | 686f34a9d1SZhihuan He| res_space_remap_all | RK3588 V1.09 | 69*6348802dSWesley Yao| rd_vref_scan_en | RK3588 V1.08/RV1126B V1.00 | 70*6348802dSWesley Yao| wr_vref_scan_en | RK3588 V1.08/RV1126B V1.00 | 716f34a9d1SZhihuan He| eye_2d_scan_en | RK3588 V1.08 | 726f34a9d1SZhihuan He| ch/bank/rank_mask | RK3588 V1.00 | 736f34a9d1SZhihuan He| pstore base_addr/buf_size | RK3588 V1.09 | 746f34a9d1SZhihuan He| uboot/atf/optee/spl/tpl log en | RK3588 V1.09 | 756f34a9d1SZhihuan He| boot_fsp | RK3588 V1.09 | 76*6348802dSWesley Yao| pageclose | RK3588 V1.10/RV1126B V1.00 | 77*6348802dSWesley Yao| first_init_dram_type/dfs_disable | RK3588 V1.11/RV1126B V1.00 | 7886251429SZhihuan He 7986251429SZhihuan He* UART info 8086251429SZhihuan He 8186251429SZhihuan Heuart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 8286251429SZhihuan Heuart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 8386251429SZhihuan Heor 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 8486251429SZhihuan Heuart baudrate: uart baudrate should be 115200 or 1500000. 8586251429SZhihuan He 8686251429SZhihuan He* disable print training information 8786251429SZhihuan He 886f34a9d1SZhihuan Hedis_train_print: 1: will disabled print training information; 0: will enable print training information. 8986251429SZhihuan He 906f34a9d1SZhihuan He* recycle registers space(remap register space to DDR) 9186251429SZhihuan He 926f34a9d1SZhihuan Heres_space_remap_portion 936f34a9d1SZhihuan He1: will remap the part of registers to DDR memory space(will not larger than 4GB). 946f34a9d1SZhihuan HeIt is PCIE and some reserved space in RK3588, and the PCIE can not be used when set to 1. 956f34a9d1SZhihuan He 966f34a9d1SZhihuan Heres_space_remap_all 976f34a9d1SZhihuan He1: will wrap all registers space(include res_space_remap_portion enable space) to DDR memory space. This space would be place in larger than 4GB. 986f34a9d1SZhihuan HeThe PCIE can be used when set to 1 in RK3588. 99612e733eSZhihuan He 100612e733eSZhihuan He* DDR eye scanning 101612e733eSZhihuan He1) eye_2d_scan_en: 1: will enable 2D eye scanning for debug purpose, vref and skew eye scanning. 102612e733eSZhihuan He2) wr_vref_scan_en: 1: enable vref scan and use scanning result for write. 103612e733eSZhihuan He3) rd_vref_scan_en: 1: enable vref scan and use scanning result for read. 10486251429SZhihuan He 1056f34a9d1SZhihuan He* DDR auto precharge 1066f34a9d1SZhihuan He 1076f34a9d1SZhihuan Heauto_precharge_en: 1: will enable the DDR auto precharge. 1086f34a9d1SZhihuan He 1096f34a9d1SZhihuan He* DDR refresh derate 1106f34a9d1SZhihuan He 1116f34a9d1SZhihuan Hederate_en: 1: will enable derate function of the LP2/LP3/LP4/LP4X/LP5. 1126f34a9d1SZhihuan HeThe high temperature will issue more refresh command and the low temperature will less. 1136f34a9d1SZhihuan He 1146f34a9d1SZhihuan He* DDR per bank refresh 1156f34a9d1SZhihuan He 1166f34a9d1SZhihuan Heper_bank_ref_en: 1: will enable per bank refresh 1176f34a9d1SZhihuan He 1186f34a9d1SZhihuan He* link ECC enable 1196f34a9d1SZhihuan He 1206f34a9d1SZhihuan Helink_ecc_en: 1: read/write link ecc enable. 1216f34a9d1SZhihuan He 1226f34a9d1SZhihuan He* Extended temperature refresh 1236f34a9d1SZhihuan He 1241c9962b9SYouMin Chenext_temp_ref: 1251c9962b9SYouMin Chen 0: ref1x for normal chip, 2x for 3568M/3568J 1261c9962b9SYouMin Chen 1: fix 2x ref for all chip 1271c9962b9SYouMin Chen 2: fix 4x ref for all chip 1281c9962b9SYouMin Chen 3: fix 1x ref for all chip 1291c9962b9SYouMin ChenNote: If derate-enabled DDR are configured with derate_en=1, the ext_temp_ref configuration does not take effect. 1306f34a9d1SZhihuan He 1316f34a9d1SZhihuan He* pstore_base_addr pstore_buf_size 1326f34a9d1SZhihuan HeThe pstore buffer base address: pstore_base_addr << 16, 64kB align. 1336f34a9d1SZhihuan HeThe pstore buffer size: pstore_buf_size * 4KB. 1346f34a9d1SZhihuan HeIt is define the addr and size to save ddrbin log for last log. 1356f34a9d1SZhihuan He 1366f34a9d1SZhihuan He* uboot_log_en 1376f34a9d1SZhihuan He1: enable uboot log. 1386f34a9d1SZhihuan He0: disable uboot log. 1396f34a9d1SZhihuan He 1406f34a9d1SZhihuan He* atf_log_en 1416f34a9d1SZhihuan He1: enable atf log. 1426f34a9d1SZhihuan He0: disable atf log. 1436f34a9d1SZhihuan He 1446f34a9d1SZhihuan He* optee_log_en 1456f34a9d1SZhihuan He1: enable optee log. 1466f34a9d1SZhihuan He0: disable optee log. 1476f34a9d1SZhihuan He 1486f34a9d1SZhihuan He* spl_log_en 1496f34a9d1SZhihuan He1: enable spl log. 1506f34a9d1SZhihuan He0: disable spl log. 1516f34a9d1SZhihuan He 1526f34a9d1SZhihuan He* tpl_log_en 1536f34a9d1SZhihuan He1: enable tpl log. 1546f34a9d1SZhihuan He0: disable tpl log. 1556f34a9d1SZhihuan He 1569c25957fSYouMin Chen* pageclose 1579c25957fSYouMin Chen1: enable pageclose. 1589c25957fSYouMin Chen0: disable pageclose. 1599c25957fSYouMin Chen 1606f34a9d1SZhihuan He* boot_fsp 1616f34a9d1SZhihuan HeTo choose the which DDR freq to boot system. 0 means fsp0_freq, 1 means fsp1_freq, 2 means fsp2_freq, 3 means fsp3_freq, the default is 0. 1626f34a9d1SZhihuan He 1634026ce53SZhihuan He* periodic interval 1644026ce53SZhihuan HeThe 0 means disable periodic training, others means enable. Unit: 100ms. 1654026ce53SZhihuan He 1664026ce53SZhihuan He* trfc_mode 1674026ce53SZhihuan He0: use default trfc 1684026ce53SZhihuan He1: use next density trfc 1694026ce53SZhihuan He2: use max trfc 1704026ce53SZhihuan He3: use min trfc 1714026ce53SZhihuan He 172bac3cde4SZhihuan He* first_init_dram_type 173bac3cde4SZhihuan HeThe define first init dram type to saving initial time. 174bac3cde4SZhihuan He|----------------------------|-----------------| 175bac3cde4SZhihuan He| first_init_dram_type value | DDR type | 176bac3cde4SZhihuan He| 0 | DDR4 | 177bac3cde4SZhihuan He| 2 | DDR2 | 178bac3cde4SZhihuan He| 3 | DDR3 | 179bac3cde4SZhihuan He| 5 | LPDDR2 | 180bac3cde4SZhihuan He| 6 | LPDDR3 | 181bac3cde4SZhihuan He| 7 | LPDDR4 | 182bac3cde4SZhihuan He| 8 | LPDDR4X | 183bac3cde4SZhihuan He| 9 | LPDDR5 | 184bac3cde4SZhihuan He| 10 | DDR5 | 185bac3cde4SZhihuan He|----------------------------|-----------------| 186bac3cde4SZhihuan He 187bac3cde4SZhihuan He* dfs_disable 188bac3cde4SZhihuan He1: disbale ddr freq switch function 189bac3cde4SZhihuan He0: enable ddr freq switch function 190bac3cde4SZhihuan He 191bac3cde4SZhihuan HeNote: 192bac3cde4SZhihuan HeThe starting frequency is fixed to f0 frequency after turning off the frequency scaling. 193bac3cde4SZhihuan HeIf the DDR frequency needs to be modified, ddrx_f0_freq/fsp0_freq should be modified. 194bac3cde4SZhihuan He 1956f34a9d1SZhihuan He* DDR (final) freq(also called ddrx_f0_freq_mhz/fsp0_freq) 1966f34a9d1SZhihuan He 1976f34a9d1SZhihuan HeFor RK3588, the boot_fsp used to choose which ddrx_fx_freq_mhz/fspx_freq to boot system, default is ddrx_f0_freq_mhz/fsp0_freq. 1986f34a9d1SZhihuan HeFor the others platform, it is the final freq to boot system. 19986251429SZhihuan He 200d42b646fSZhihuan Heddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz. 201d42b646fSZhihuan Help2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz. 202d42b646fSZhihuan Heddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz. 203d42b646fSZhihuan Help3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz. 204d42b646fSZhihuan Heddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz. 205d42b646fSZhihuan Help4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz. 206d42b646fSZhihuan Help4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz. 207d42b646fSZhihuan Help5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz. 20854a17cb1STang Yun ping 2096f34a9d1SZhihuan He* support ddr frequency: 2106f34a9d1SZhihuan HeThe 'X' as follows means not support change frequencies by tool. 2116f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 2126f34a9d1SZhihuan He| platform | support frequencies(MHZ) | 2136f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 2146f34a9d1SZhihuan He| RK1108 | DDR2: 400; LP2: <= 533; DDR3: <= 800 | 2156f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 21686251429SZhihuan He| PX30/RK3326 | X | 2176f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 21886251429SZhihuan He| RK1808 | 333,400,533,666,786,933 | 2196f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 2206f34a9d1SZhihuan He| RK322x | DDR2/LP2: <= 533; others: <= 800 | 2216f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 22286251429SZhihuan He| RK322xh | X | 2236f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 22486251429SZhihuan He| RK3288 | X | 2256f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 2266f34a9d1SZhihuan He| RK3308/RK3308S| DDR2/LP2: 393,451; DDR3: 393,451,589 | 2276f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 2286f34a9d1SZhihuan He| RK3368 | DDR3: <= 800; LP3: <= 666 | 2296f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 23086251429SZhihuan He| RK3328 | X | 2316f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 23286251429SZhihuan He| RK3399 | X | 2336f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 23486251429SZhihuan He| RK3399PRO NPU | 333,400,533,666,786,933 | 2356f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 23686251429SZhihuan He| RV1126/RV1109 | 328,396,528,664,784,924,1056 | 2376f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 2386f34a9d1SZhihuan He| RK3566 | 324,396,528,630,780,920,1056 | 2396f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 2406f34a9d1SZhihuan He| RK3568 | DDR3/LP3: 324,396,528,630,780,920,1056 | 2416f34a9d1SZhihuan He| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184,1332,1560 | 2426f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 2438edfcbeaSZhihuan He| RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] | 2446f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 245bac3cde4SZhihuan He| RK3528 | DDR3/LP3/LP4/LP4X: 324,396,528,630,780,920,1056 | 246bac3cde4SZhihuan He| | DDR4: 324,396,528,630,780,920,1056,1184 | 247bac3cde4SZhihuan He+---------------+-----------------------------------------------------------------+ 248bac3cde4SZhihuan He| RK3562 | DDR3/LP3: [324MHz - 1056MHz]; LP4/LP4X/DDR4: [324MHz - 1392MHz] | 249f90d99fcSZhihuan He+---------------+-----------------------------------------------------------------+ 2509dcea43dSZhihuan He| RV1106/RV1103 | DDR2: 528MHz; DDR3: 324,660,792,924; | 2519dcea43dSZhihuan He+---------------+-----------------------------------------------------------------+ 252*6348802dSWesley Yao| RV1126B | DDR3/LP3: [324MHz - 1056MHz]; LP4/LP4X/DDR4: [324MHz - 1392MHz] | 253*6348802dSWesley Yao| | LP4/LP4X f1: [324MHz - 400MHz] | 254*6348802dSWesley Yao+---------------+-----------------------------------------------------------------+ 255*6348802dSWesley Yao| RV1126BP | [324MHz - 1056MHz] | 256*6348802dSWesley Yao| | LP4/LP4X f1: [324MHz - 400MHz] | 257*6348802dSWesley Yao+---------------+-----------------------------------------------------------------+ 258558a25b2STang Yun ping 25986251429SZhihuan He* DDR frequencies(add more) 260eea48410SZhihuan He 2616f34a9d1SZhihuan Heddr2_f1_freq_mhz: ddr2 frequency fsp 1, unit:MHz. 2626f34a9d1SZhihuan Heddr2_f2_freq_mhz: ddr2 frequency fsp 2, unit:MHz. 2636f34a9d1SZhihuan Heddr2_f3_freq_mhz: ddr2 frequency fsp 3, unit:MHz. 2646f34a9d1SZhihuan Heddr2_f4_freq_mhz: ddr2 frequency fsp 4, unit:MHz. 2656f34a9d1SZhihuan Heddr2_f5_freq_mhz: ddr2 frequency fsp 5, unit:MHz. 26672640b4bSZhihuan He... 2676f34a9d1SZhihuan HeThe ddrx_f0_freq_mhz(the fsp0 frequency) is named ddrx_freq. 26886251429SZhihuan He 269612e733eSZhihuan Heddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used. 2708edfcbeaSZhihuan HeThe program will initialize dram by following order. 27186251429SZhihuan Hefor example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq. 272612e733eSZhihuan HeAnd the final frequency is ddr4_freq to boot system. 273612e733eSZhihuan HeThe ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 27486251429SZhihuan HeSo it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'. 275612e733eSZhihuan HeSuch as: ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq) 27686251429SZhihuan HeFor example: 27786251429SZhihuan He ... 27886251429SZhihuan He ddr4_freq=1560 27986251429SZhihuan He ... 28086251429SZhihuan He ddr4_f1_freq_mhz=324 28186251429SZhihuan He ddr4_f2_freq_mhz=528 28286251429SZhihuan He ddr4_f3_freq_mhz=780 28386251429SZhihuan He ... 28486251429SZhihuan He 2856f34a9d1SZhihuan HeNote: The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 2866f34a9d1SZhihuan He 28786251429SZhihuan He* SR PD idle 28886251429SZhihuan He 28986251429SZhihuan Hesr_idle: auto self-refresh mode delay time. 29086251429SZhihuan Hepd_idle: auto power-down mode delay time. 29186251429SZhihuan He 29286251429SZhihuan He* DDR 2T 29386251429SZhihuan He 29486251429SZhihuan Heddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 29586251429SZhihuan He 29686251429SZhihuan He* PLL ssmod 29786251429SZhihuan He 2983e8d76b8SZhihuan HeThese parameters are about Spread Spectrum Modulator(ssmod) for PLL. 299bac3cde4SZhihuan Hessmod_downspread: ssmod work mode. 300bac3cde4SZhihuan He2'b00: center spread. (Suggest to use center spread for better clock jitter) 301bac3cde4SZhihuan He2'b01: down spread. 302bac3cde4SZhihuan He2'b10: up spread.(Please refer to the datasheet for support information) 303bac3cde4SZhihuan He2'b11: reserved 304bac3cde4SZhihuan He 305bac3cde4SZhihuan Hessmod_div: Divider required to set the modulation frequency. 306bac3cde4SZhihuan He RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5. 3073e8d76b8SZhihuan Hessmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f. 308bac3cde4SZhihuan He The larger the ssmod_spread value, the smaller of EMI, the worse of clk jitter. 309bac3cde4SZhihuan He Suggest to use ssmod_spread = 5, which means the center spread is +/-0.5%. 310bac3cde4SZhihuan HePlease refer to "Rockchip_Developer_Guide_Pll_Ssmod_Clock_CN" for more information. 31186251429SZhihuan He 31286251429SZhihuan He* driver strength 31386251429SZhihuan He 31486251429SZhihuan Hephy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm. 31586251429SZhihuan Hephy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm. 31686251429SZhihuan Hephy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm. 31786251429SZhihuan Heddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm. 31886251429SZhihuan Hephy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm. 31986251429SZhihuan Hephy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm. 32086251429SZhihuan Hephy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm. 32186251429SZhihuan Heddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm. 32286251429SZhihuan He 32386251429SZhihuan HeThe phy side driver strength support value as follows: 324612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 325612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 326612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 327612e733eSZhihuan He| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | | 328612e733eSZhihuan He| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | | 329612e733eSZhihuan He| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | X | 330612e733eSZhihuan He| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | | 331612e733eSZhihuan He| | 20 | 21 | | 25,24,23,22 | | | | 332612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 333612e733eSZhihuan He| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | | 334612e733eSZhihuan He| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | | 335612e733eSZhihuan He| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 336612e733eSZhihuan He| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 337612e733eSZhihuan He| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 338612e733eSZhihuan He| | | | | | 28 | 23 | | 339612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 340612e733eSZhihuan He| RK3588 | X | X | X | 240,120,80,60, | follow LP4 | follow LP4 | follow LP4 | 341612e733eSZhihuan He| | | | | 48,40,34,30 | | | | 342612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 343f90d99fcSZhihuan He| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 585,297,202, | 585,297,202, | | 344f90d99fcSZhihuan He| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 150,122,103,90,| | 345f90d99fcSZhihuan He| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43,| follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 346f90d99fcSZhihuan He| | 38,36,34,33,31,30,| 39,37,35,34,32,31,| | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 347f90d99fcSZhihuan He| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 348f90d99fcSZhihuan He| | | | | | 30 | 30 | | 349f90d99fcSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 350*6348802dSWesley Yao| | 573,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 586,297,202, | 558,282,190, | | 351*6348802dSWesley Yao| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 142,115,96,84, | | 352*6348802dSWesley Yao| RV1126B/BP | 60,55,50,47,44,41,| 62,57,52,49,46,43,| follow DDR4 | 67,62,57,53,49, | 76,69,63,58,53,| 72,64,58,54,49,| X | 353*6348802dSWesley Yao| | 38,36,35,33,32,30,| 40,38,36,34,33,31,| | 46,43,41,39,37, | 49,47,44,41,39,| 46,43,40,38,36,| | 354*6348802dSWesley Yao| | 29,28 | 30,29 | | 35,34,33,31 | 37,35,34,33,31,| 34,32,31,30,29,| | 355*6348802dSWesley Yao| | | | | | 30 | 28 | | 356*6348802dSWesley Yao+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 35786251429SZhihuan He 35886251429SZhihuan HeThe DRAM side driver strength support value as follows: 359612e733eSZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 360612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | LP5 | 361612e733eSZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 362612e733eSZhihuan He| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | follow LP4 | 363612e733eSZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 36486251429SZhihuan He 36586251429SZhihuan He* ODT 36686251429SZhihuan Hephy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm. 36786251429SZhihuan Heddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm. 36886251429SZhihuan Hephy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable 36986251429SZhihuan Hephy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable 37086251429SZhihuan Hephy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz. 37186251429SZhihuan Heddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz. 37286251429SZhihuan He 3739dcea43dSZhihuan HeNote: 3749dcea43dSZhihuan Heddr4_odten_freq_mhz: The DDR4 DRAM ODT is not supported below 625MHz according to JEDEC standard. It means ddr4_odten_freq_mhz should not less than 625. 3759dcea43dSZhihuan Help4_dq_odten_freq_mhz/lp4x_dq_odten_freq_mhz: The lp4/lp4x DRAM DQ ODT is not supported below 800MHz according to JEDEC standard. 3769dcea43dSZhihuan He It means lp4_dq_odten_freq_mhz/lp4x_dq_odten_freq_mhz should not less than 800. 3779dcea43dSZhihuan He 37886251429SZhihuan HeThe phy side ODT support value as follows: 37986251429SZhihuan HeThe ODT "0" means disabled ODT. 380612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 381612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 382612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 383612e733eSZhihuan He| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | | 384612e733eSZhihuan He| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | | 385612e733eSZhihuan He| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | X | 386612e733eSZhihuan He| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | | 387612e733eSZhihuan He| | 28,27,25 | 27 | | 29,27 | | | | 388612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 389612e733eSZhihuan He| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | | 390612e733eSZhihuan He| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | | 391612e733eSZhihuan He| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 392612e733eSZhihuan He| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 393612e733eSZhihuan He| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 394612e733eSZhihuan He| | | | | | 28 | 23 | | 395612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 396612e733eSZhihuan He| RK3588 | X | X | X | 0,240,120,80, | follow LP4 | follow LP4 | follow LP4 | 397612e733eSZhihuan He| | | | | 60,48,40,34,30 | | | | 398612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 399f90d99fcSZhihuan He| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 585,297,202, | 585,297,202, | | 400f90d99fcSZhihuan He| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 150,122,103,90,| | 401f90d99fcSZhihuan He| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43, | follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 402f90d99fcSZhihuan He| | 38,36,34,33,31,30,| 39,37,35,34,32,31, | | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 403f90d99fcSZhihuan He| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 404f90d99fcSZhihuan He| | | | | | 30 | 30 | | 405f90d99fcSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 406*6348802dSWesley Yao| | 573,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 586,297,202, | 558,282,190, | | 407*6348802dSWesley Yao| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 142,115,96,84, | | 408*6348802dSWesley Yao| RV1126B/BP | 60,55,50,47,44,41,| 62,57,52,49,46,43, | follow DDR4 | 67,62,57,53,49, | 76,69,63,58,53,| 72,64,58,54,49,| X | 409*6348802dSWesley Yao| | 38,36,35,33,32,30,| 40,38,36,34,33,31, | | 46,43,41,39,37, | 49,47,44,41,39,| 46,43,40,38,36,| | 410*6348802dSWesley Yao| | 29,28 | 30,29 | | 35,34,33,31 | 37,35,34,33,31,| 34,32,31,30,29,| | 411*6348802dSWesley Yao| | | | | | 30 | 28 | | 412*6348802dSWesley Yao+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 413*6348802dSWesley Yao 41486251429SZhihuan HeThe DRAM side ODT support value as follows: 415612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 416612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | LP5 | 417612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 418612e733eSZhihuan He| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | follow LP4 | 419612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 42086251429SZhihuan He 42186251429SZhihuan He* slew rate 42286251429SZhihuan He 42386251429SZhihuan Hephy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on. 42486251429SZhihuan Hephy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on. 42586251429SZhihuan Hephy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on. 42686251429SZhihuan Hephy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off. 42786251429SZhihuan Hephy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off. 42886251429SZhihuan Hephy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off. 42986251429SZhihuan He 430612e733eSZhihuan HeThe max value is 0x1f, the min is 0x0. 431612e733eSZhihuan He 43286251429SZhihuan He* byte map 43386251429SZhihuan He 434612e733eSZhihuan Heddr*_bytes_map: The bytes remap in PHY. 43586251429SZhihuan He 43686251429SZhihuan He* dq remap 43786251429SZhihuan He 438612e733eSZhihuan Help*_dq*_*_map: The dq remap in PHY. 439612e733eSZhihuan Heddr*_cs*_dq*_dq*_map: The dq remap in PHY. 44086251429SZhihuan He 44186251429SZhihuan He* lp4/lp4x more information 44286251429SZhihuan He 44386251429SZhihuan Help4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz. 4446dab7052SYouMin Chen 4456dab7052SYouMin Chen* vref 4466dab7052SYouMin Chen 4476dab7052SYouMin Chenphy_ddr*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand. 4486dab7052SYouMin Chenddr*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand. 4496dab7052SYouMin Chenddr*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand. 4506dab7052SYouMin Chenphy_ddr*_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand. 4516dab7052SYouMin Chenddr*_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand. 4526dab7052SYouMin Chenddr*_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand. 4536dab7052SYouMin Chen 4546dab7052SYouMin ChenFor DDR2/3/4 and LPDDR2/3, if the configuration value is "0", Vref is automatically calculated by the code. 4558edfcbeaSZhihuan He 4568edfcbeaSZhihuan He* hash info 4578edfcbeaSZhihuan Hech/bank/rank_mask*: is used to DDR address hash mask. 458bac3cde4SZhihuan He 459bac3cde4SZhihuan He* modify skew info 460bac3cde4SZhihuan He 461bac3cde4SZhihuan Heddr*_skew_freq_mhz: Used to specify the frequency of skew. 462bac3cde4SZhihuan He 463bac3cde4SZhihuan Heddr*_skew: The skew value of dram type are need to modify. If need to modify skew, you must check with the hardware engineer. 464bac3cde4SZhihuan He 465bac3cde4SZhihuan HeThe support platform: 466bac3cde4SZhihuan He|---------------------------|--------------------|--------------------------------------------| 467bac3cde4SZhihuan He| platform | ddrbin version | calculate one step delay(ps) | 468bac3cde4SZhihuan He| RK3528 | V1.06 | 1000000 / ddr*_skew_freq_mhz / 128 | 469bac3cde4SZhihuan He|---------------------------|--------------------|--------------------------------------------| 470bac3cde4SZhihuan He 471bac3cde4SZhihuan HeFor RK3528, the skew one step is 7.398ps when ddr*_skew_freq_mhz is 1056. 472bac3cde4SZhihuan He 473bac3cde4SZhihuan HeBefore modify skew, it is recommended to read every CA skew from the bin file and then adjust the CA skew which want to change. 474