16b245014SSiva Durga Prasad Paladugu /* 26b245014SSiva Durga Prasad Paladugu * (C) Copyright 2015 Xilinx, Inc, 36b245014SSiva Durga Prasad Paladugu * Michal Simek <michal.simek@xilinx.com> 46b245014SSiva Durga Prasad Paladugu * 56b245014SSiva Durga Prasad Paladugu * SPDX-License-Identifier: GPL-2.0 66b245014SSiva Durga Prasad Paladugu */ 76b245014SSiva Durga Prasad Paladugu 86b245014SSiva Durga Prasad Paladugu #ifndef _ZYNQMPPL_H_ 96b245014SSiva Durga Prasad Paladugu #define _ZYNQMPPL_H_ 106b245014SSiva Durga Prasad Paladugu 116b245014SSiva Durga Prasad Paladugu #include <xilinx.h> 126b245014SSiva Durga Prasad Paladugu 13*47e60cbdSMichal Simek #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 146b245014SSiva Durga Prasad Paladugu #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 156b245014SSiva Durga Prasad Paladugu #define ZYNQMP_FPGA_OP_INIT (1 << 0) 166b245014SSiva Durga Prasad Paladugu #define ZYNQMP_FPGA_OP_LOAD (1 << 1) 176b245014SSiva Durga Prasad Paladugu #define ZYNQMP_FPGA_OP_DONE (1 << 2) 186b245014SSiva Durga Prasad Paladugu 196b245014SSiva Durga Prasad Paladugu extern struct xilinx_fpga_op zynqmp_op; 206b245014SSiva Durga Prasad Paladugu 216b245014SSiva Durga Prasad Paladugu #define XILINX_ZYNQMP_DESC \ 226b245014SSiva Durga Prasad Paladugu { xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op } 236b245014SSiva Durga Prasad Paladugu 246b245014SSiva Durga Prasad Paladugu #endif /* _ZYNQMPPL_H_ */ 25