16b245014SSiva Durga Prasad Paladugu /* 26b245014SSiva Durga Prasad Paladugu * (C) Copyright 2015 Xilinx, Inc, 36b245014SSiva Durga Prasad Paladugu * Michal Simek <michal.simek@xilinx.com> 46b245014SSiva Durga Prasad Paladugu * 56b245014SSiva Durga Prasad Paladugu * SPDX-License-Identifier: GPL-2.0 66b245014SSiva Durga Prasad Paladugu */ 76b245014SSiva Durga Prasad Paladugu 86b245014SSiva Durga Prasad Paladugu #ifndef _ZYNQMPPL_H_ 96b245014SSiva Durga Prasad Paladugu #define _ZYNQMPPL_H_ 106b245014SSiva Durga Prasad Paladugu 116b245014SSiva Durga Prasad Paladugu #include <xilinx.h> 126b245014SSiva Durga Prasad Paladugu 1347e60cbdSMichal Simek #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 146b245014SSiva Durga Prasad Paladugu #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 156b245014SSiva Durga Prasad Paladugu #define ZYNQMP_FPGA_OP_INIT (1 << 0) 166b245014SSiva Durga Prasad Paladugu #define ZYNQMP_FPGA_OP_LOAD (1 << 1) 176b245014SSiva Durga Prasad Paladugu #define ZYNQMP_FPGA_OP_DONE (1 << 2) 186b245014SSiva Durga Prasad Paladugu 190cba6abbSSoren Brinkmann #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 200cba6abbSSoren Brinkmann #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ 210cba6abbSSoren Brinkmann ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) 220cba6abbSSoren Brinkmann #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 23*92687047SMichal Simek #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT) 240cba6abbSSoren Brinkmann 256b245014SSiva Durga Prasad Paladugu extern struct xilinx_fpga_op zynqmp_op; 266b245014SSiva Durga Prasad Paladugu 276b245014SSiva Durga Prasad Paladugu #define XILINX_ZYNQMP_DESC \ 286b245014SSiva Durga Prasad Paladugu { xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op } 296b245014SSiva Durga Prasad Paladugu 306b245014SSiva Durga Prasad Paladugu #endif /* _ZYNQMPPL_H_ */ 31