1 /* 2 * Copyright 2013, 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Driver for the Vitesse VSC9953 L2 Switch 7 */ 8 9 #ifndef _VSC9953_H_ 10 #define _VSC9953_H_ 11 12 #include <config.h> 13 #include <miiphy.h> 14 #include <asm/types.h> 15 16 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) 17 18 #define VSC9953_SYS_OFFSET 0x010000 19 #define VSC9953_REW_OFFSET 0x030000 20 #define VSC9953_DEV_GMII_OFFSET 0x100000 21 #define VSC9953_QSYS_OFFSET 0x200000 22 #define VSC9953_ANA_OFFSET 0x280000 23 #define VSC9953_DEVCPU_GCB 0x070000 24 #define VSC9953_ES0 0x040000 25 #define VSC9953_IS1 0x050000 26 #define VSC9953_IS2 0x060000 27 28 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 29 #define VSC9953_PHY_REGS_OFFST 0x0000AC 30 31 /* Macros for vsc9953_chip_regs.soft_rst register */ 32 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 33 34 /* Macros for vsc9953_sys_sys.reset_cfg register */ 35 #define VSC9953_CORE_ENABLE 0x80 36 #define VSC9953_MEM_ENABLE 0x40 37 #define VSC9953_MEM_INIT 0x20 38 39 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ 40 #define VSC9953_MAC_ENA_CFG 0x00000011 41 42 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ 43 #define VSC9953_MAC_MODE_CFG 0x00000011 44 45 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ 46 #define VSC9953_MAC_IFG_CFG 0x00000515 47 48 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ 49 #define VSC9953_MAC_HDX_CFG 0x00001043 50 51 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ 52 #define VSC9953_MAC_MAX_LEN 0x000005ee 53 54 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ 55 #define VSC9953_CLOCK_CFG 0x00000001 56 #define VSC9953_CLOCK_CFG_1000M 0x00000001 57 58 /* Macros for vsc9953_sys_sys.front_port_mode register */ 59 #define VSC9953_FRONT_PORT_MODE 0x00000000 60 61 /* Macros for vsc9953_ana_pfc.pfc_cfg register */ 62 #define VSC9953_PFC_FC 0x00000001 63 #define VSC9953_PFC_FC_QSGMII 0x00000000 64 65 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ 66 #define VSC9953_MAC_FC_CFG 0x04700000 67 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 68 69 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ 70 #define VSC9953_PAUSE_CFG 0x001ffffe 71 72 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ 73 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff 74 75 /* Macros for vsc9953_sys_sys.stat_cfg register */ 76 #define VSC9953_STAT_CLEAR_RX 0x00000400 77 #define VSC9953_STAT_CLEAR_TX 0x00000800 78 #define VSC9953_STAT_CLEAR_DR 0x00001000 79 80 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ 81 #define VSC9953_VCAP_MV_CFG 0x0000ffff 82 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 83 84 /* Macros for register vsc9953_ana_ana_tables.mac_access register */ 85 #define VSC9953_MAC_CMD_IDLE 0x00000000 86 #define VSC9953_MAC_CMD_LEARN 0x00000001 87 #define VSC9953_MAC_CMD_FORGET 0x00000002 88 #define VSC9953_MAC_CMD_AGE 0x00000003 89 #define VSC9953_MAC_CMD_NEXT 0x00000004 90 #define VSC9953_MAC_CMD_READ 0x00000006 91 #define VSC9953_MAC_CMD_WRITE 0x00000007 92 #define VSC9953_MAC_CMD_MASK 0x00000007 93 #define VSC9953_MAC_CMD_VALID 0x00000800 94 #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000 95 #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200 96 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400 97 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600 98 #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600 99 #define VSC9953_MAC_DESTIDX_MASK 0x000001f8 100 #define VSC9953_MAC_VID_MASK 0x1fff0000 101 #define VSC9953_MAC_MACH_MASK 0x0000ffff 102 103 /* Macros for vsc9953_ana_port.vlan_cfg register */ 104 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 105 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 106 #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000 107 #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000 108 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff 109 110 /* Macros for vsc9953_rew_port.port_vlan_cfg register */ 111 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff 112 113 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ 114 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff 115 116 /* Macros for vsc9953_ana_ana_tables.vlan_access register */ 117 #define VSC9953_VLAN_PORT_MASK 0x00001ffc 118 #define VSC9953_VLAN_CMD_MASK 0x00000003 119 #define VSC9953_VLAN_CMD_IDLE 0x00000000 120 #define VSC9953_VLAN_CMD_READ 0x00000001 121 #define VSC9953_VLAN_CMD_WRITE 0x00000002 122 #define VSC9953_VLAN_CMD_INIT 0x00000003 123 124 /* Macros for vsc9953_ana_port.port_cfg register */ 125 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080 126 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 127 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 128 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 129 130 /* Macros for vsc9953_qsys_sys.switch_port_mode register */ 131 #define VSC9953_PORT_ENA 0x00002000 132 133 /* Macros for vsc9953_ana_ana.agen_ctrl register */ 134 #define VSC9953_FID_MASK_ALL 0x00fff000 135 136 /* Macros for vsc9953_ana_ana.adv_learn register */ 137 #define VSC9953_VLAN_CHK 0x00000400 138 139 /* Macros for vsc9953_ana_ana.auto_age register */ 140 #define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe 141 142 /* Macros for vsc9953_rew_port.port_tag_cfg register */ 143 #define VSC9953_TAG_CFG_MASK 0x00000180 144 #define VSC9953_TAG_CFG_NONE 0x00000000 145 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 146 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 147 #define VSC9953_TAG_CFG_ALL 0x00000180 148 #define VSC9953_TAG_VID_PVID 0x00000010 149 150 /* Macros for vsc9953_ana_ana.anag_efil register */ 151 #define VSC9953_AGE_PORT_EN 0x00080000 152 #define VSC9953_AGE_PORT_MASK 0x0007c000 153 #define VSC9953_AGE_VID_EN 0x00002000 154 #define VSC9953_AGE_VID_MASK 0x00001fff 155 156 /* Macros for vsc9953_ana_ana_tables.mach_data register */ 157 #define VSC9953_MACHDATA_VID_MASK 0x1fff0000 158 159 #define VSC9953_MAX_PORTS 10 160 #define VSC9953_PORT_CHECK(port) \ 161 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) 162 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \ 163 ( \ 164 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ 165 ) ? 0 : 1 \ 166 ) 167 #define VSC9953_MAX_VLAN 4096 168 #define VSC9953_VLAN_CHECK(vid) \ 169 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) 170 #define VSC9953_DEFAULT_AGE_TIME 300 171 172 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" 173 174 #define MIIMIND_OPR_PEND 0x00000004 175 176 struct vsc9953_mdio_info { 177 struct vsc9953_mii_mng *regs; 178 char *name; 179 }; 180 181 /* VSC9953 ANA structure */ 182 183 struct vsc9953_ana_port { 184 u32 vlan_cfg; 185 u32 drop_cfg; 186 u32 qos_cfg; 187 u32 vcap_cfg; 188 u32 vcap_s1_key_cfg[3]; 189 u32 vcap_s2_cfg; 190 u32 qos_pcp_dei_map_cfg[16]; 191 u32 cpu_fwd_cfg; 192 u32 cpu_fwd_bpdu_cfg; 193 u32 cpu_fwd_garp_cfg; 194 u32 cpu_fwd_ccm_cfg; 195 u32 port_cfg; 196 u32 pol_cfg; 197 u32 reserved[34]; 198 }; 199 200 struct vsc9953_ana_pol { 201 u32 pol_pir_cfg; 202 u32 pol_cir_cfg; 203 u32 pol_mode_cfg; 204 u32 pol_pir_state; 205 u32 pol_cir_state; 206 u32 reserved1[3]; 207 }; 208 209 struct vsc9953_ana_ana_tables { 210 u32 entry_lim[11]; 211 u32 an_moved; 212 u32 mach_data; 213 u32 macl_data; 214 u32 mac_access; 215 u32 mact_indx; 216 u32 vlan_access; 217 u32 vlan_tidx; 218 }; 219 220 struct vsc9953_ana_ana { 221 u32 adv_learn; 222 u32 vlan_mask; 223 u32 reserved; 224 u32 anag_efil; 225 u32 an_events; 226 u32 storm_limit_burst; 227 u32 storm_limit_cfg[4]; 228 u32 isolated_prts; 229 u32 community_ports; 230 u32 auto_age; 231 u32 mac_options; 232 u32 learn_disc; 233 u32 agen_ctrl; 234 u32 mirror_ports; 235 u32 emirror_ports; 236 u32 flooding; 237 u32 flooding_ipmc; 238 u32 sflow_cfg[11]; 239 u32 port_mode[12]; 240 }; 241 242 struct vsc9953_ana_pgid { 243 u32 port_grp_id[91]; 244 }; 245 246 struct vsc9953_ana_pfc { 247 u32 pfc_cfg; 248 u32 reserved1[15]; 249 }; 250 251 struct vsc9953_ana_pol_misc { 252 u32 pol_flowc[10]; 253 u32 reserved1[17]; 254 u32 pol_hyst; 255 }; 256 257 struct vsc9953_ana_common { 258 u32 aggr_cfg; 259 u32 cpuq_cfg; 260 u32 cpuq_8021_cfg; 261 u32 dscp_cfg; 262 u32 dscp_rewr_cfg; 263 u32 vcap_rng_type_cfg; 264 u32 vcap_rng_val_cfg; 265 u32 discard_cfg; 266 u32 fid_cfg; 267 }; 268 269 struct vsc9953_analyzer { 270 struct vsc9953_ana_port port[11]; 271 u32 reserved1[9536]; 272 struct vsc9953_ana_pol pol[164]; 273 struct vsc9953_ana_ana_tables ana_tables; 274 u32 reserved2[14]; 275 struct vsc9953_ana_ana ana; 276 u32 reserved3[21]; 277 struct vsc9953_ana_pgid port_id_tbl; 278 u32 reserved4[549]; 279 struct vsc9953_ana_pfc pfc[10]; 280 struct vsc9953_ana_pol_misc pol_misc; 281 u32 reserved5[196]; 282 struct vsc9953_ana_common common; 283 }; 284 /* END VSC9953 ANA structure t*/ 285 286 /* VSC9953 DEV_GMII structure */ 287 288 struct vsc9953_dev_gmii_port_mode { 289 u32 clock_cfg; 290 u32 port_misc; 291 u32 reserved1; 292 u32 eee_cfg; 293 }; 294 295 struct vsc9953_dev_gmii_mac_cfg_status { 296 u32 mac_ena_cfg; 297 u32 mac_mode_cfg; 298 u32 mac_maxlen_cfg; 299 u32 mac_tags_cfg; 300 u32 mac_adv_chk_cfg; 301 u32 mac_ifg_cfg; 302 u32 mac_hdx_cfg; 303 u32 mac_fc_mac_low_cfg; 304 u32 mac_fc_mac_high_cfg; 305 u32 mac_sticky; 306 }; 307 308 struct vsc9953_dev_gmii { 309 struct vsc9953_dev_gmii_port_mode port_mode; 310 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; 311 }; 312 313 /* END VSC9953 DEV_GMII structure */ 314 315 /* VSC9953 QSYS structure */ 316 317 struct vsc9953_qsys_hsch { 318 u32 cir_cfg; 319 u32 reserved1; 320 u32 se_cfg; 321 u32 se_dwrr_cfg[8]; 322 u32 cir_state; 323 u32 reserved2[20]; 324 }; 325 326 struct vsc9953_qsys_sys { 327 u32 port_mode[12]; 328 u32 switch_port_mode[11]; 329 u32 stat_cnt_cfg; 330 u32 eee_cfg[10]; 331 u32 eee_thrs; 332 u32 igr_no_sharing; 333 u32 egr_no_sharing; 334 u32 sw_status[11]; 335 u32 ext_cpu_cfg; 336 u32 cpu_group_map; 337 u32 reserved1[23]; 338 }; 339 340 struct vsc9953_qsys_qos_cfg { 341 u32 red_profile[16]; 342 u32 res_qos_mode; 343 }; 344 345 struct vsc9953_qsys_drop_cfg { 346 u32 egr_drop_mode; 347 }; 348 349 struct vsc9953_qsys_mmgt { 350 u32 eq_cntrl; 351 u32 reserved1; 352 }; 353 354 struct vsc9953_qsys_hsch_misc { 355 u32 hsch_misc_cfg; 356 u32 reserved1[546]; 357 }; 358 359 struct vsc9953_qsys_res_ctrl { 360 u32 res_cfg; 361 u32 res_stat; 362 363 }; 364 365 struct vsc9953_qsys_reg { 366 struct vsc9953_qsys_hsch hsch[108]; 367 struct vsc9953_qsys_sys sys; 368 struct vsc9953_qsys_qos_cfg qos_cfg; 369 struct vsc9953_qsys_drop_cfg drop_cfg; 370 struct vsc9953_qsys_mmgt mmgt; 371 struct vsc9953_qsys_hsch_misc hsch_misc; 372 struct vsc9953_qsys_res_ctrl res_ctrl[1024]; 373 }; 374 375 /* END VSC9953 QSYS structure */ 376 377 /* VSC9953 SYS structure */ 378 379 struct vsc9953_rx_cntrs { 380 u32 c_rx_oct; 381 u32 c_rx_uc; 382 u32 c_rx_mc; 383 u32 c_rx_bc; 384 u32 c_rx_short; 385 u32 c_rx_frag; 386 u32 c_rx_jabber; 387 u32 c_rx_crc; 388 u32 c_rx_symbol_err; 389 u32 c_rx_sz_64; 390 u32 c_rx_sz_65_127; 391 u32 c_rx_sz_128_255; 392 u32 c_rx_sz_256_511; 393 u32 c_rx_sz_512_1023; 394 u32 c_rx_sz_1024_1526; 395 u32 c_rx_sz_jumbo; 396 u32 c_rx_pause; 397 u32 c_rx_control; 398 u32 c_rx_long; 399 u32 c_rx_cat_drop; 400 u32 c_rx_red_prio_0; 401 u32 c_rx_red_prio_1; 402 u32 c_rx_red_prio_2; 403 u32 c_rx_red_prio_3; 404 u32 c_rx_red_prio_4; 405 u32 c_rx_red_prio_5; 406 u32 c_rx_red_prio_6; 407 u32 c_rx_red_prio_7; 408 u32 c_rx_yellow_prio_0; 409 u32 c_rx_yellow_prio_1; 410 u32 c_rx_yellow_prio_2; 411 u32 c_rx_yellow_prio_3; 412 u32 c_rx_yellow_prio_4; 413 u32 c_rx_yellow_prio_5; 414 u32 c_rx_yellow_prio_6; 415 u32 c_rx_yellow_prio_7; 416 u32 c_rx_green_prio_0; 417 u32 c_rx_green_prio_1; 418 u32 c_rx_green_prio_2; 419 u32 c_rx_green_prio_3; 420 u32 c_rx_green_prio_4; 421 u32 c_rx_green_prio_5; 422 u32 c_rx_green_prio_6; 423 u32 c_rx_green_prio_7; 424 u32 reserved[20]; 425 }; 426 427 struct vsc9953_tx_cntrs { 428 u32 c_tx_oct; 429 u32 c_tx_uc; 430 u32 c_tx_mc; 431 u32 c_tx_bc; 432 u32 c_tx_col; 433 u32 c_tx_drop; 434 u32 c_tx_pause; 435 u32 c_tx_sz_64; 436 u32 c_tx_sz_65_127; 437 u32 c_tx_sz_128_255; 438 u32 c_tx_sz_256_511; 439 u32 c_tx_sz_512_1023; 440 u32 c_tx_sz_1024_1526; 441 u32 c_tx_sz_jumbo; 442 u32 c_tx_yellow_prio_0; 443 u32 c_tx_yellow_prio_1; 444 u32 c_tx_yellow_prio_2; 445 u32 c_tx_yellow_prio_3; 446 u32 c_tx_yellow_prio_4; 447 u32 c_tx_yellow_prio_5; 448 u32 c_tx_yellow_prio_6; 449 u32 c_tx_yellow_prio_7; 450 u32 c_tx_green_prio_0; 451 u32 c_tx_green_prio_1; 452 u32 c_tx_green_prio_2; 453 u32 c_tx_green_prio_3; 454 u32 c_tx_green_prio_4; 455 u32 c_tx_green_prio_5; 456 u32 c_tx_green_prio_6; 457 u32 c_tx_green_prio_7; 458 u32 c_tx_aged; 459 u32 reserved[33]; 460 }; 461 462 struct vsc9953_drop_cntrs { 463 u32 c_dr_local; 464 u32 c_dr_tail; 465 u32 c_dr_yellow_prio_0; 466 u32 c_dr_yellow_prio_1; 467 u32 c_dr_yellow_prio_2; 468 u32 c_dr_yellow_prio_3; 469 u32 c_dr_yellow_prio_4; 470 u32 c_dr_yellow_prio_5; 471 u32 c_dr_yellow_prio_6; 472 u32 c_dr_yellow_prio_7; 473 u32 c_dr_green_prio_0; 474 u32 c_dr_green_prio_1; 475 u32 c_dr_green_prio_2; 476 u32 c_dr_green_prio_3; 477 u32 c_dr_green_prio_4; 478 u32 c_dr_green_prio_5; 479 u32 c_dr_green_prio_6; 480 u32 c_dr_green_prio_7; 481 u32 reserved[46]; 482 }; 483 484 struct vsc9953_sys_stat { 485 struct vsc9953_rx_cntrs rx_cntrs; 486 struct vsc9953_tx_cntrs tx_cntrs; 487 struct vsc9953_drop_cntrs drop_cntrs; 488 u32 reserved1[6]; 489 }; 490 491 struct vsc9953_sys_sys { 492 u32 reset_cfg; 493 u32 reserved1; 494 u32 vlan_etype_cfg; 495 u32 port_mode[12]; 496 u32 front_port_mode[10]; 497 u32 frame_aging; 498 u32 stat_cfg; 499 u32 reserved2[50]; 500 }; 501 502 struct vsc9953_sys_pause_cfg { 503 u32 pause_cfg[11]; 504 u32 pause_tot_cfg; 505 u32 tail_drop_level[11]; 506 u32 tot_tail_drop_lvl; 507 u32 mac_fc_cfg[10]; 508 }; 509 510 struct vsc9953_sys_mmgt { 511 u16 free_cnt; 512 }; 513 514 struct vsc9953_system_reg { 515 struct vsc9953_sys_stat stat; 516 struct vsc9953_sys_sys sys; 517 struct vsc9953_sys_pause_cfg pause_cfg; 518 struct vsc9953_sys_mmgt mmgt; 519 }; 520 521 /* END VSC9953 SYS structure */ 522 523 /* VSC9953 REW structure */ 524 525 struct vsc9953_rew_port { 526 u32 port_vlan_cfg; 527 u32 port_tag_cfg; 528 u32 port_port_cfg; 529 u32 port_dscp_cfg; 530 u32 port_pcp_dei_qos_map_cfg[16]; 531 u32 reserved[12]; 532 }; 533 534 struct vsc9953_rew_common { 535 u32 reserve[4]; 536 u32 dscp_remap_dp1_cfg[64]; 537 u32 dscp_remap_cfg[64]; 538 }; 539 540 struct vsc9953_rew_reg { 541 struct vsc9953_rew_port port[12]; 542 struct vsc9953_rew_common common; 543 }; 544 545 /* END VSC9953 REW structure */ 546 547 /* VSC9953 DEVCPU_GCB structure */ 548 549 struct vsc9953_chip_regs { 550 u32 chipd_id; 551 u32 gpr; 552 u32 soft_rst; 553 }; 554 555 struct vsc9953_gpio { 556 u32 gpio_out_set[10]; 557 u32 gpio_out_clr[10]; 558 u32 gpio_out[10]; 559 u32 gpio_in[10]; 560 }; 561 562 struct vsc9953_mii_mng { 563 u32 miimstatus; 564 u32 reserved1; 565 u32 miimcmd; 566 u32 miimdata; 567 u32 miimcfg; 568 u32 miimscan_0; 569 u32 miimscan_1; 570 u32 miiscan_lst_rslts; 571 u32 miiscan_lst_rslts_valid; 572 }; 573 574 struct vsc9953_mii_read_scan { 575 u32 mii_scan_results_sticky[2]; 576 }; 577 578 struct vsc9953_devcpu_gcb { 579 struct vsc9953_chip_regs chip_regs; 580 struct vsc9953_gpio gpio; 581 struct vsc9953_mii_mng mii_mng[2]; 582 struct vsc9953_mii_read_scan mii_read_scan; 583 }; 584 585 /* END VSC9953 DEVCPU_GCB structure */ 586 587 /* VSC9953 IS* structure */ 588 589 struct vsc9953_vcap_core_cfg { 590 u32 vcap_update_ctrl; 591 u32 vcap_mv_cfg; 592 }; 593 594 struct vsc9953_vcap { 595 struct vsc9953_vcap_core_cfg vcap_core_cfg; 596 }; 597 598 /* END VSC9953 IS* structure */ 599 600 #define VSC9953_PORT_INFO_INITIALIZER(idx) \ 601 { \ 602 .enabled = 0, \ 603 .phyaddr = 0, \ 604 .index = idx, \ 605 .phy_regs = NULL, \ 606 .enet_if = PHY_INTERFACE_MODE_NONE, \ 607 .bus = NULL, \ 608 .phydev = NULL, \ 609 } 610 611 /* Structure to describe a VSC9953 port */ 612 struct vsc9953_port_info { 613 u8 enabled; 614 u8 phyaddr; 615 int index; 616 void *phy_regs; 617 phy_interface_t enet_if; 618 struct mii_dev *bus; 619 struct phy_device *phydev; 620 }; 621 622 /* Structure to describe a VSC9953 switch */ 623 struct vsc9953_info { 624 struct vsc9953_port_info port[VSC9953_MAX_PORTS]; 625 }; 626 627 void vsc9953_init(bd_t *bis); 628 629 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); 630 void vsc9953_port_info_set_phy_address(int port_no, int address); 631 void vsc9953_port_enable(int port_no); 632 void vsc9953_port_disable(int port_no); 633 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); 634 635 #endif /* _VSC9953_H_ */ 636