1 /* 2 * vsc9953.h 3 * 4 * Driver for the Vitesse VSC9953 L2 Switch 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2013 Freescale Semiconductor, Inc. 11 * 12 */ 13 14 #ifndef _VSC9953_H_ 15 #define _VSC9953_H_ 16 17 #include <config.h> 18 #include <miiphy.h> 19 #include <asm/types.h> 20 21 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) 22 23 #define VSC9953_SYS_OFFSET 0x010000 24 #define VSC9953_REW_OFFSET 0x030000 25 #define VSC9953_DEV_GMII_OFFSET 0x100000 26 #define VSC9953_QSYS_OFFSET 0x200000 27 #define VSC9953_ANA_OFFSET 0x280000 28 #define VSC9953_DEVCPU_GCB 0x070000 29 #define VSC9953_ES0 0x040000 30 #define VSC9953_IS1 0x050000 31 #define VSC9953_IS2 0x060000 32 33 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 34 #define VSC9953_PHY_REGS_OFFST 0x0000AC 35 36 /* Macros for vsc9953_chip_regs.soft_rst register */ 37 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 38 39 /* Macros for vsc9953_sys_sys.reset_cfg register */ 40 #define VSC9953_CORE_ENABLE 0x80 41 #define VSC9953_MEM_ENABLE 0x40 42 #define VSC9953_MEM_INIT 0x20 43 44 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ 45 #define VSC9953_MAC_ENA_CFG 0x00000011 46 47 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ 48 #define VSC9953_MAC_MODE_CFG 0x00000011 49 50 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ 51 #define VSC9953_MAC_IFG_CFG 0x00000515 52 53 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ 54 #define VSC9953_MAC_HDX_CFG 0x00001043 55 56 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ 57 #define VSC9953_MAC_MAX_LEN 0x000005ee 58 59 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ 60 #define VSC9953_CLOCK_CFG 0x00000001 61 #define VSC9953_CLOCK_CFG_1000M 0x00000001 62 63 /* Macros for vsc9953_sys_sys.front_port_mode register */ 64 #define VSC9953_FRONT_PORT_MODE 0x00000000 65 66 /* Macros for vsc9953_ana_pfc.pfc_cfg register */ 67 #define VSC9953_PFC_FC 0x00000001 68 #define VSC9953_PFC_FC_QSGMII 0x00000000 69 70 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ 71 #define VSC9953_MAC_FC_CFG 0x04700000 72 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 73 74 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ 75 #define VSC9953_PAUSE_CFG 0x001ffffe 76 77 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ 78 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff 79 80 /* Macros for vsc9953_sys_sys.stat_cfg register */ 81 #define VSC9953_STAT_CLEAR_RX 0x00000400 82 #define VSC9953_STAT_CLEAR_TX 0x00000800 83 #define VSC9953_STAT_CLEAR_DR 0x00001000 84 85 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ 86 #define VSC9953_VCAP_MV_CFG 0x0000ffff 87 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 88 89 /* Macros for register vsc9953_ana_ana_tables.mac_access register */ 90 #define VSC9953_MAC_CMD_IDLE 0x00000000 91 #define VSC9953_MAC_CMD_LEARN 0x00000001 92 #define VSC9953_MAC_CMD_FORGET 0x00000002 93 #define VSC9953_MAC_CMD_AGE 0x00000003 94 #define VSC9953_MAC_CMD_NEXT 0x00000004 95 #define VSC9953_MAC_CMD_READ 0x00000006 96 #define VSC9953_MAC_CMD_WRITE 0x00000007 97 #define VSC9953_MAC_CMD_MASK 0x00000007 98 #define VSC9953_MAC_CMD_VALID 0x00000800 99 #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000 100 #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200 101 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400 102 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600 103 #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600 104 #define VSC9953_MAC_DESTIDX_MASK 0x000001f8 105 #define VSC9953_MAC_VID_MASK 0x1fff0000 106 #define VSC9953_MAC_MACH_MASK 0x0000ffff 107 108 /* Macros for vsc9953_ana_port.vlan_cfg register */ 109 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 110 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 111 #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000 112 #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000 113 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff 114 115 /* Macros for vsc9953_rew_port.port_vlan_cfg register */ 116 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff 117 118 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ 119 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff 120 121 /* Macros for vsc9953_ana_ana_tables.vlan_access register */ 122 #define VSC9953_VLAN_PORT_MASK 0x00001ffc 123 #define VSC9953_VLAN_CMD_MASK 0x00000003 124 #define VSC9953_VLAN_CMD_IDLE 0x00000000 125 #define VSC9953_VLAN_CMD_READ 0x00000001 126 #define VSC9953_VLAN_CMD_WRITE 0x00000002 127 #define VSC9953_VLAN_CMD_INIT 0x00000003 128 129 /* Macros for vsc9953_ana_port.port_cfg register */ 130 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080 131 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 132 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 133 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 134 135 /* Macros for vsc9953_qsys_sys.switch_port_mode register */ 136 #define VSC9953_PORT_ENA 0x00002000 137 138 /* Macros for vsc9953_ana_ana.adv_learn register */ 139 #define VSC9953_VLAN_CHK 0x00000400 140 141 /* Macros for vsc9953_rew_port.port_tag_cfg register */ 142 #define VSC9953_TAG_CFG_MASK 0x00000180 143 #define VSC9953_TAG_CFG_NONE 0x00000000 144 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 145 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 146 #define VSC9953_TAG_CFG_ALL 0x00000180 147 #define VSC9953_TAG_VID_PVID 0x00000010 148 149 /* Macros for vsc9953_ana_ana.anag_efil register */ 150 #define VSC9953_AGE_PORT_EN 0x00080000 151 #define VSC9953_AGE_PORT_MASK 0x0007c000 152 #define VSC9953_AGE_VID_EN 0x00002000 153 #define VSC9953_AGE_VID_MASK 0x00001fff 154 155 /* Macros for vsc9953_ana_ana_tables.mach_data register */ 156 #define VSC9953_MACHDATA_VID_MASK 0x1fff0000 157 158 #define VSC9953_MAX_PORTS 10 159 #define VSC9953_PORT_CHECK(port) \ 160 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) 161 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \ 162 ( \ 163 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ 164 ) ? 0 : 1 \ 165 ) 166 #define VSC9953_MAX_VLAN 4096 167 #define VSC9953_VLAN_CHECK(vid) \ 168 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) 169 170 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" 171 172 #define MIIMIND_OPR_PEND 0x00000004 173 174 struct vsc9953_mdio_info { 175 struct vsc9953_mii_mng *regs; 176 char *name; 177 }; 178 179 /* VSC9953 ANA structure */ 180 181 struct vsc9953_ana_port { 182 u32 vlan_cfg; 183 u32 drop_cfg; 184 u32 qos_cfg; 185 u32 vcap_cfg; 186 u32 vcap_s1_key_cfg[3]; 187 u32 vcap_s2_cfg; 188 u32 qos_pcp_dei_map_cfg[16]; 189 u32 cpu_fwd_cfg; 190 u32 cpu_fwd_bpdu_cfg; 191 u32 cpu_fwd_garp_cfg; 192 u32 cpu_fwd_ccm_cfg; 193 u32 port_cfg; 194 u32 pol_cfg; 195 u32 reserved[34]; 196 }; 197 198 struct vsc9953_ana_pol { 199 u32 pol_pir_cfg; 200 u32 pol_cir_cfg; 201 u32 pol_mode_cfg; 202 u32 pol_pir_state; 203 u32 pol_cir_state; 204 u32 reserved1[3]; 205 }; 206 207 struct vsc9953_ana_ana_tables { 208 u32 entry_lim[11]; 209 u32 an_moved; 210 u32 mach_data; 211 u32 macl_data; 212 u32 mac_access; 213 u32 mact_indx; 214 u32 vlan_access; 215 u32 vlan_tidx; 216 }; 217 218 struct vsc9953_ana_ana { 219 u32 adv_learn; 220 u32 vlan_mask; 221 u32 reserved; 222 u32 anag_efil; 223 u32 an_events; 224 u32 storm_limit_burst; 225 u32 storm_limit_cfg[4]; 226 u32 isolated_prts; 227 u32 community_ports; 228 u32 auto_age; 229 u32 mac_options; 230 u32 learn_disc; 231 u32 agen_ctrl; 232 u32 mirror_ports; 233 u32 emirror_ports; 234 u32 flooding; 235 u32 flooding_ipmc; 236 u32 sflow_cfg[11]; 237 u32 port_mode[12]; 238 }; 239 240 struct vsc9953_ana_pgid { 241 u32 port_grp_id[91]; 242 }; 243 244 struct vsc9953_ana_pfc { 245 u32 pfc_cfg; 246 u32 reserved1[15]; 247 }; 248 249 struct vsc9953_ana_pol_misc { 250 u32 pol_flowc[10]; 251 u32 reserved1[17]; 252 u32 pol_hyst; 253 }; 254 255 struct vsc9953_ana_common { 256 u32 aggr_cfg; 257 u32 cpuq_cfg; 258 u32 cpuq_8021_cfg; 259 u32 dscp_cfg; 260 u32 dscp_rewr_cfg; 261 u32 vcap_rng_type_cfg; 262 u32 vcap_rng_val_cfg; 263 u32 discard_cfg; 264 u32 fid_cfg; 265 }; 266 267 struct vsc9953_analyzer { 268 struct vsc9953_ana_port port[11]; 269 u32 reserved1[9536]; 270 struct vsc9953_ana_pol pol[164]; 271 struct vsc9953_ana_ana_tables ana_tables; 272 u32 reserved2[14]; 273 struct vsc9953_ana_ana ana; 274 u32 reserved3[22]; 275 struct vsc9953_ana_pgid port_id_tbl; 276 u32 reserved4[549]; 277 struct vsc9953_ana_pfc pfc[10]; 278 struct vsc9953_ana_pol_misc pol_misc; 279 u32 reserved5[196]; 280 struct vsc9953_ana_common common; 281 }; 282 /* END VSC9953 ANA structure t*/ 283 284 /* VSC9953 DEV_GMII structure */ 285 286 struct vsc9953_dev_gmii_port_mode { 287 u32 clock_cfg; 288 u32 port_misc; 289 u32 reserved1; 290 u32 eee_cfg; 291 }; 292 293 struct vsc9953_dev_gmii_mac_cfg_status { 294 u32 mac_ena_cfg; 295 u32 mac_mode_cfg; 296 u32 mac_maxlen_cfg; 297 u32 mac_tags_cfg; 298 u32 mac_adv_chk_cfg; 299 u32 mac_ifg_cfg; 300 u32 mac_hdx_cfg; 301 u32 mac_fc_mac_low_cfg; 302 u32 mac_fc_mac_high_cfg; 303 u32 mac_sticky; 304 }; 305 306 struct vsc9953_dev_gmii { 307 struct vsc9953_dev_gmii_port_mode port_mode; 308 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; 309 }; 310 311 /* END VSC9953 DEV_GMII structure */ 312 313 /* VSC9953 QSYS structure */ 314 315 struct vsc9953_qsys_hsch { 316 u32 cir_cfg; 317 u32 reserved1; 318 u32 se_cfg; 319 u32 se_dwrr_cfg[8]; 320 u32 cir_state; 321 u32 reserved2[20]; 322 }; 323 324 struct vsc9953_qsys_sys { 325 u32 port_mode[12]; 326 u32 switch_port_mode[11]; 327 u32 stat_cnt_cfg; 328 u32 eee_cfg[10]; 329 u32 eee_thrs; 330 u32 igr_no_sharing; 331 u32 egr_no_sharing; 332 u32 sw_status[11]; 333 u32 ext_cpu_cfg; 334 u32 cpu_group_map; 335 u32 reserved1[23]; 336 }; 337 338 struct vsc9953_qsys_qos_cfg { 339 u32 red_profile[16]; 340 u32 res_qos_mode; 341 }; 342 343 struct vsc9953_qsys_drop_cfg { 344 u32 egr_drop_mode; 345 }; 346 347 struct vsc9953_qsys_mmgt { 348 u32 eq_cntrl; 349 u32 reserved1; 350 }; 351 352 struct vsc9953_qsys_hsch_misc { 353 u32 hsch_misc_cfg; 354 u32 reserved1[546]; 355 }; 356 357 struct vsc9953_qsys_res_ctrl { 358 u32 res_cfg; 359 u32 res_stat; 360 361 }; 362 363 struct vsc9953_qsys_reg { 364 struct vsc9953_qsys_hsch hsch[108]; 365 struct vsc9953_qsys_sys sys; 366 struct vsc9953_qsys_qos_cfg qos_cfg; 367 struct vsc9953_qsys_drop_cfg drop_cfg; 368 struct vsc9953_qsys_mmgt mmgt; 369 struct vsc9953_qsys_hsch_misc hsch_misc; 370 struct vsc9953_qsys_res_ctrl res_ctrl[1024]; 371 }; 372 373 /* END VSC9953 QSYS structure */ 374 375 /* VSC9953 SYS structure */ 376 377 struct vsc9953_rx_cntrs { 378 u32 c_rx_oct; 379 u32 c_rx_uc; 380 u32 c_rx_mc; 381 u32 c_rx_bc; 382 u32 c_rx_short; 383 u32 c_rx_frag; 384 u32 c_rx_jabber; 385 u32 c_rx_crc; 386 u32 c_rx_symbol_err; 387 u32 c_rx_sz_64; 388 u32 c_rx_sz_65_127; 389 u32 c_rx_sz_128_255; 390 u32 c_rx_sz_256_511; 391 u32 c_rx_sz_512_1023; 392 u32 c_rx_sz_1024_1526; 393 u32 c_rx_sz_jumbo; 394 u32 c_rx_pause; 395 u32 c_rx_control; 396 u32 c_rx_long; 397 u32 c_rx_cat_drop; 398 u32 c_rx_red_prio_0; 399 u32 c_rx_red_prio_1; 400 u32 c_rx_red_prio_2; 401 u32 c_rx_red_prio_3; 402 u32 c_rx_red_prio_4; 403 u32 c_rx_red_prio_5; 404 u32 c_rx_red_prio_6; 405 u32 c_rx_red_prio_7; 406 u32 c_rx_yellow_prio_0; 407 u32 c_rx_yellow_prio_1; 408 u32 c_rx_yellow_prio_2; 409 u32 c_rx_yellow_prio_3; 410 u32 c_rx_yellow_prio_4; 411 u32 c_rx_yellow_prio_5; 412 u32 c_rx_yellow_prio_6; 413 u32 c_rx_yellow_prio_7; 414 u32 c_rx_green_prio_0; 415 u32 c_rx_green_prio_1; 416 u32 c_rx_green_prio_2; 417 u32 c_rx_green_prio_3; 418 u32 c_rx_green_prio_4; 419 u32 c_rx_green_prio_5; 420 u32 c_rx_green_prio_6; 421 u32 c_rx_green_prio_7; 422 u32 reserved[20]; 423 }; 424 425 struct vsc9953_tx_cntrs { 426 u32 c_tx_oct; 427 u32 c_tx_uc; 428 u32 c_tx_mc; 429 u32 c_tx_bc; 430 u32 c_tx_col; 431 u32 c_tx_drop; 432 u32 c_tx_pause; 433 u32 c_tx_sz_64; 434 u32 c_tx_sz_65_127; 435 u32 c_tx_sz_128_255; 436 u32 c_tx_sz_256_511; 437 u32 c_tx_sz_512_1023; 438 u32 c_tx_sz_1024_1526; 439 u32 c_tx_sz_jumbo; 440 u32 c_tx_yellow_prio_0; 441 u32 c_tx_yellow_prio_1; 442 u32 c_tx_yellow_prio_2; 443 u32 c_tx_yellow_prio_3; 444 u32 c_tx_yellow_prio_4; 445 u32 c_tx_yellow_prio_5; 446 u32 c_tx_yellow_prio_6; 447 u32 c_tx_yellow_prio_7; 448 u32 c_tx_green_prio_0; 449 u32 c_tx_green_prio_1; 450 u32 c_tx_green_prio_2; 451 u32 c_tx_green_prio_3; 452 u32 c_tx_green_prio_4; 453 u32 c_tx_green_prio_5; 454 u32 c_tx_green_prio_6; 455 u32 c_tx_green_prio_7; 456 u32 c_tx_aged; 457 u32 reserved[33]; 458 }; 459 460 struct vsc9953_drop_cntrs { 461 u32 c_dr_local; 462 u32 c_dr_tail; 463 u32 c_dr_yellow_prio_0; 464 u32 c_dr_yellow_prio_1; 465 u32 c_dr_yellow_prio_2; 466 u32 c_dr_yellow_prio_3; 467 u32 c_dr_yellow_prio_4; 468 u32 c_dr_yellow_prio_5; 469 u32 c_dr_yellow_prio_6; 470 u32 c_dr_yellow_prio_7; 471 u32 c_dr_green_prio_0; 472 u32 c_dr_green_prio_1; 473 u32 c_dr_green_prio_2; 474 u32 c_dr_green_prio_3; 475 u32 c_dr_green_prio_4; 476 u32 c_dr_green_prio_5; 477 u32 c_dr_green_prio_6; 478 u32 c_dr_green_prio_7; 479 u32 reserved[46]; 480 }; 481 482 struct vsc9953_sys_stat { 483 struct vsc9953_rx_cntrs rx_cntrs; 484 struct vsc9953_tx_cntrs tx_cntrs; 485 struct vsc9953_drop_cntrs drop_cntrs; 486 u32 reserved1[6]; 487 }; 488 489 struct vsc9953_sys_sys { 490 u32 reset_cfg; 491 u32 reserved1; 492 u32 vlan_etype_cfg; 493 u32 port_mode[12]; 494 u32 front_port_mode[10]; 495 u32 frame_aging; 496 u32 stat_cfg; 497 u32 reserved2[50]; 498 }; 499 500 struct vsc9953_sys_pause_cfg { 501 u32 pause_cfg[11]; 502 u32 pause_tot_cfg; 503 u32 tail_drop_level[11]; 504 u32 tot_tail_drop_lvl; 505 u32 mac_fc_cfg[10]; 506 }; 507 508 struct vsc9953_sys_mmgt { 509 u16 free_cnt; 510 }; 511 512 struct vsc9953_system_reg { 513 struct vsc9953_sys_stat stat; 514 struct vsc9953_sys_sys sys; 515 struct vsc9953_sys_pause_cfg pause_cfg; 516 struct vsc9953_sys_mmgt mmgt; 517 }; 518 519 /* END VSC9953 SYS structure */ 520 521 /* VSC9953 REW structure */ 522 523 struct vsc9953_rew_port { 524 u32 port_vlan_cfg; 525 u32 port_tag_cfg; 526 u32 port_port_cfg; 527 u32 port_dscp_cfg; 528 u32 port_pcp_dei_qos_map_cfg[16]; 529 u32 reserved[12]; 530 }; 531 532 struct vsc9953_rew_common { 533 u32 reserve[4]; 534 u32 dscp_remap_dp1_cfg[64]; 535 u32 dscp_remap_cfg[64]; 536 }; 537 538 struct vsc9953_rew_reg { 539 struct vsc9953_rew_port port[12]; 540 struct vsc9953_rew_common common; 541 }; 542 543 /* END VSC9953 REW structure */ 544 545 /* VSC9953 DEVCPU_GCB structure */ 546 547 struct vsc9953_chip_regs { 548 u32 chipd_id; 549 u32 gpr; 550 u32 soft_rst; 551 }; 552 553 struct vsc9953_gpio { 554 u32 gpio_out_set[10]; 555 u32 gpio_out_clr[10]; 556 u32 gpio_out[10]; 557 u32 gpio_in[10]; 558 }; 559 560 struct vsc9953_mii_mng { 561 u32 miimstatus; 562 u32 reserved1; 563 u32 miimcmd; 564 u32 miimdata; 565 u32 miimcfg; 566 u32 miimscan_0; 567 u32 miimscan_1; 568 u32 miiscan_lst_rslts; 569 u32 miiscan_lst_rslts_valid; 570 }; 571 572 struct vsc9953_mii_read_scan { 573 u32 mii_scan_results_sticky[2]; 574 }; 575 576 struct vsc9953_devcpu_gcb { 577 struct vsc9953_chip_regs chip_regs; 578 struct vsc9953_gpio gpio; 579 struct vsc9953_mii_mng mii_mng[2]; 580 struct vsc9953_mii_read_scan mii_read_scan; 581 }; 582 583 /* END VSC9953 DEVCPU_GCB structure */ 584 585 /* VSC9953 IS* structure */ 586 587 struct vsc9953_vcap_core_cfg { 588 u32 vcap_update_ctrl; 589 u32 vcap_mv_cfg; 590 }; 591 592 struct vsc9953_vcap { 593 struct vsc9953_vcap_core_cfg vcap_core_cfg; 594 }; 595 596 /* END VSC9953 IS* structure */ 597 598 #define VSC9953_PORT_INFO_INITIALIZER(idx) \ 599 { \ 600 .enabled = 0, \ 601 .phyaddr = 0, \ 602 .index = idx, \ 603 .phy_regs = NULL, \ 604 .enet_if = PHY_INTERFACE_MODE_NONE, \ 605 .bus = NULL, \ 606 .phydev = NULL, \ 607 } 608 609 /* Structure to describe a VSC9953 port */ 610 struct vsc9953_port_info { 611 u8 enabled; 612 u8 phyaddr; 613 int index; 614 void *phy_regs; 615 phy_interface_t enet_if; 616 struct mii_dev *bus; 617 struct phy_device *phydev; 618 }; 619 620 /* Structure to describe a VSC9953 switch */ 621 struct vsc9953_info { 622 struct vsc9953_port_info port[VSC9953_MAX_PORTS]; 623 }; 624 625 void vsc9953_init(bd_t *bis); 626 627 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); 628 void vsc9953_port_info_set_phy_address(int port_no, int address); 629 void vsc9953_port_enable(int port_no); 630 void vsc9953_port_disable(int port_no); 631 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); 632 633 #endif /* _VSC9953_H_ */ 634