1 /* 2 * vsc9953.h 3 * 4 * Driver for the Vitesse VSC9953 L2 Switch 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2013 Freescale Semiconductor, Inc. 11 * 12 */ 13 14 #ifndef _VSC9953_H_ 15 #define _VSC9953_H_ 16 17 #include <config.h> 18 #include <miiphy.h> 19 #include <asm/types.h> 20 21 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) 22 23 #define VSC9953_SYS_OFFSET 0x010000 24 #define VSC9953_REW_OFFSET 0x030000 25 #define VSC9953_DEV_GMII_OFFSET 0x100000 26 #define VSC9953_QSYS_OFFSET 0x200000 27 #define VSC9953_ANA_OFFSET 0x280000 28 #define VSC9953_DEVCPU_GCB 0x070000 29 #define VSC9953_ES0 0x040000 30 #define VSC9953_IS1 0x050000 31 #define VSC9953_IS2 0x060000 32 33 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 34 #define VSC9953_PHY_REGS_OFFST 0x0000AC 35 36 /* Macros for vsc9953_chip_regs.soft_rst register */ 37 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 38 39 /* Macros for vsc9953_sys_sys.reset_cfg register */ 40 #define VSC9953_CORE_ENABLE 0x80 41 #define VSC9953_MEM_ENABLE 0x40 42 #define VSC9953_MEM_INIT 0x20 43 44 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ 45 #define VSC9953_MAC_ENA_CFG 0x00000011 46 47 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ 48 #define VSC9953_MAC_MODE_CFG 0x00000011 49 50 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ 51 #define VSC9953_MAC_IFG_CFG 0x00000515 52 53 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ 54 #define VSC9953_MAC_HDX_CFG 0x00001043 55 56 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ 57 #define VSC9953_MAC_MAX_LEN 0x000005ee 58 59 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ 60 #define VSC9953_CLOCK_CFG 0x00000001 61 #define VSC9953_CLOCK_CFG_1000M 0x00000001 62 63 /* Macros for vsc9953_sys_sys.front_port_mode register */ 64 #define VSC9953_FRONT_PORT_MODE 0x00000000 65 66 /* Macros for vsc9953_ana_pfc.pfc_cfg register */ 67 #define VSC9953_PFC_FC 0x00000001 68 #define VSC9953_PFC_FC_QSGMII 0x00000000 69 70 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ 71 #define VSC9953_MAC_FC_CFG 0x04700000 72 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 73 74 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ 75 #define VSC9953_PAUSE_CFG 0x001ffffe 76 77 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ 78 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff 79 80 /* Macros for vsc9953_sys_sys.stat_cfg register */ 81 #define VSC9953_STAT_CLEAR_RX 0x00000400 82 #define VSC9953_STAT_CLEAR_TX 0x00000800 83 #define VSC9953_STAT_CLEAR_DR 0x00001000 84 85 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ 86 #define VSC9953_VCAP_MV_CFG 0x0000ffff 87 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 88 89 /* Macros for vsc9953_ana_port.vlan_cfg register */ 90 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 91 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 92 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff 93 94 /* Macros for vsc9953_rew_port.port_vlan_cfg register */ 95 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff 96 97 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ 98 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff 99 100 /* Macros for vsc9953_ana_ana_tables.vlan_access register */ 101 #define VSC9953_VLAN_PORT_MASK 0x00001ffc 102 #define VSC9953_VLAN_CMD_MASK 0x00000003 103 #define VSC9953_VLAN_CMD_IDLE 0x00000000 104 #define VSC9953_VLAN_CMD_READ 0x00000001 105 #define VSC9953_VLAN_CMD_WRITE 0x00000002 106 #define VSC9953_VLAN_CMD_INIT 0x00000003 107 108 /* Macros for vsc9953_qsys_sys.switch_port_mode register */ 109 #define VSC9953_PORT_ENA 0x00002000 110 111 /* Macros for vsc9953_ana_ana.adv_learn register */ 112 #define VSC9953_VLAN_CHK 0x00000400 113 114 /* Macros for vsc9953_rew_port.port_tag_cfg register */ 115 #define VSC9953_TAG_CFG_MASK 0x00000180 116 #define VSC9953_TAG_CFG_NONE 0x00000000 117 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 118 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 119 #define VSC9953_TAG_CFG_ALL 0x00000180 120 121 #define VSC9953_MAX_PORTS 10 122 #define VSC9953_PORT_CHECK(port) \ 123 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) 124 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \ 125 ( \ 126 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ 127 ) ? 0 : 1 \ 128 ) 129 #define VSC9953_MAX_VLAN 4096 130 #define VSC9953_VLAN_CHECK(vid) \ 131 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) 132 133 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" 134 135 #define MIIMIND_OPR_PEND 0x00000004 136 137 struct vsc9953_mdio_info { 138 struct vsc9953_mii_mng *regs; 139 char *name; 140 }; 141 142 /* VSC9953 ANA structure */ 143 144 struct vsc9953_ana_port { 145 u32 vlan_cfg; 146 u32 drop_cfg; 147 u32 qos_cfg; 148 u32 vcap_cfg; 149 u32 vcap_s1_key_cfg[3]; 150 u32 vcap_s2_cfg; 151 u32 qos_pcp_dei_map_cfg[16]; 152 u32 cpu_fwd_cfg; 153 u32 cpu_fwd_bpdu_cfg; 154 u32 cpu_fwd_garp_cfg; 155 u32 cpu_fwd_ccm_cfg; 156 u32 port_cfg; 157 u32 pol_cfg; 158 u32 reserved[34]; 159 }; 160 161 struct vsc9953_ana_pol { 162 u32 pol_pir_cfg; 163 u32 pol_cir_cfg; 164 u32 pol_mode_cfg; 165 u32 pol_pir_state; 166 u32 pol_cir_state; 167 u32 reserved1[3]; 168 }; 169 170 struct vsc9953_ana_ana_tables { 171 u32 entry_lim[11]; 172 u32 an_moved; 173 u32 mach_data; 174 u32 macl_data; 175 u32 mac_access; 176 u32 mact_indx; 177 u32 vlan_access; 178 u32 vlan_tidx; 179 }; 180 181 struct vsc9953_ana_ana { 182 u32 adv_learn; 183 u32 vlan_mask; 184 u32 reserved; 185 u32 anag_efil; 186 u32 an_events; 187 u32 storm_limit_burst; 188 u32 storm_limit_cfg[4]; 189 u32 isolated_prts; 190 u32 community_ports; 191 u32 auto_age; 192 u32 mac_options; 193 u32 learn_disc; 194 u32 agen_ctrl; 195 u32 mirror_ports; 196 u32 emirror_ports; 197 u32 flooding; 198 u32 flooding_ipmc; 199 u32 sflow_cfg[11]; 200 u32 port_mode[12]; 201 }; 202 203 struct vsc9953_ana_pgid { 204 u32 port_grp_id[91]; 205 }; 206 207 struct vsc9953_ana_pfc { 208 u32 pfc_cfg; 209 u32 reserved1[15]; 210 }; 211 212 struct vsc9953_ana_pol_misc { 213 u32 pol_flowc[10]; 214 u32 reserved1[17]; 215 u32 pol_hyst; 216 }; 217 218 struct vsc9953_ana_common { 219 u32 aggr_cfg; 220 u32 cpuq_cfg; 221 u32 cpuq_8021_cfg; 222 u32 dscp_cfg; 223 u32 dscp_rewr_cfg; 224 u32 vcap_rng_type_cfg; 225 u32 vcap_rng_val_cfg; 226 u32 discard_cfg; 227 u32 fid_cfg; 228 }; 229 230 struct vsc9953_analyzer { 231 struct vsc9953_ana_port port[11]; 232 u32 reserved1[9536]; 233 struct vsc9953_ana_pol pol[164]; 234 struct vsc9953_ana_ana_tables ana_tables; 235 u32 reserved2[14]; 236 struct vsc9953_ana_ana ana; 237 u32 reserved3[22]; 238 struct vsc9953_ana_pgid port_id_tbl; 239 u32 reserved4[549]; 240 struct vsc9953_ana_pfc pfc[10]; 241 struct vsc9953_ana_pol_misc pol_misc; 242 u32 reserved5[196]; 243 struct vsc9953_ana_common common; 244 }; 245 /* END VSC9953 ANA structure t*/ 246 247 /* VSC9953 DEV_GMII structure */ 248 249 struct vsc9953_dev_gmii_port_mode { 250 u32 clock_cfg; 251 u32 port_misc; 252 u32 reserved1; 253 u32 eee_cfg; 254 }; 255 256 struct vsc9953_dev_gmii_mac_cfg_status { 257 u32 mac_ena_cfg; 258 u32 mac_mode_cfg; 259 u32 mac_maxlen_cfg; 260 u32 mac_tags_cfg; 261 u32 mac_adv_chk_cfg; 262 u32 mac_ifg_cfg; 263 u32 mac_hdx_cfg; 264 u32 mac_fc_mac_low_cfg; 265 u32 mac_fc_mac_high_cfg; 266 u32 mac_sticky; 267 }; 268 269 struct vsc9953_dev_gmii { 270 struct vsc9953_dev_gmii_port_mode port_mode; 271 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; 272 }; 273 274 /* END VSC9953 DEV_GMII structure */ 275 276 /* VSC9953 QSYS structure */ 277 278 struct vsc9953_qsys_hsch { 279 u32 cir_cfg; 280 u32 reserved1; 281 u32 se_cfg; 282 u32 se_dwrr_cfg[8]; 283 u32 cir_state; 284 u32 reserved2[20]; 285 }; 286 287 struct vsc9953_qsys_sys { 288 u32 port_mode[12]; 289 u32 switch_port_mode[11]; 290 u32 stat_cnt_cfg; 291 u32 eee_cfg[10]; 292 u32 eee_thrs; 293 u32 igr_no_sharing; 294 u32 egr_no_sharing; 295 u32 sw_status[11]; 296 u32 ext_cpu_cfg; 297 u32 cpu_group_map; 298 u32 reserved1[23]; 299 }; 300 301 struct vsc9953_qsys_qos_cfg { 302 u32 red_profile[16]; 303 u32 res_qos_mode; 304 }; 305 306 struct vsc9953_qsys_drop_cfg { 307 u32 egr_drop_mode; 308 }; 309 310 struct vsc9953_qsys_mmgt { 311 u32 eq_cntrl; 312 u32 reserved1; 313 }; 314 315 struct vsc9953_qsys_hsch_misc { 316 u32 hsch_misc_cfg; 317 u32 reserved1[546]; 318 }; 319 320 struct vsc9953_qsys_res_ctrl { 321 u32 res_cfg; 322 u32 res_stat; 323 324 }; 325 326 struct vsc9953_qsys_reg { 327 struct vsc9953_qsys_hsch hsch[108]; 328 struct vsc9953_qsys_sys sys; 329 struct vsc9953_qsys_qos_cfg qos_cfg; 330 struct vsc9953_qsys_drop_cfg drop_cfg; 331 struct vsc9953_qsys_mmgt mmgt; 332 struct vsc9953_qsys_hsch_misc hsch_misc; 333 struct vsc9953_qsys_res_ctrl res_ctrl[1024]; 334 }; 335 336 /* END VSC9953 QSYS structure */ 337 338 /* VSC9953 SYS structure */ 339 340 struct vsc9953_rx_cntrs { 341 u32 c_rx_oct; 342 u32 c_rx_uc; 343 u32 c_rx_mc; 344 u32 c_rx_bc; 345 u32 c_rx_short; 346 u32 c_rx_frag; 347 u32 c_rx_jabber; 348 u32 c_rx_crc; 349 u32 c_rx_symbol_err; 350 u32 c_rx_sz_64; 351 u32 c_rx_sz_65_127; 352 u32 c_rx_sz_128_255; 353 u32 c_rx_sz_256_511; 354 u32 c_rx_sz_512_1023; 355 u32 c_rx_sz_1024_1526; 356 u32 c_rx_sz_jumbo; 357 u32 c_rx_pause; 358 u32 c_rx_control; 359 u32 c_rx_long; 360 u32 c_rx_cat_drop; 361 u32 c_rx_red_prio_0; 362 u32 c_rx_red_prio_1; 363 u32 c_rx_red_prio_2; 364 u32 c_rx_red_prio_3; 365 u32 c_rx_red_prio_4; 366 u32 c_rx_red_prio_5; 367 u32 c_rx_red_prio_6; 368 u32 c_rx_red_prio_7; 369 u32 c_rx_yellow_prio_0; 370 u32 c_rx_yellow_prio_1; 371 u32 c_rx_yellow_prio_2; 372 u32 c_rx_yellow_prio_3; 373 u32 c_rx_yellow_prio_4; 374 u32 c_rx_yellow_prio_5; 375 u32 c_rx_yellow_prio_6; 376 u32 c_rx_yellow_prio_7; 377 u32 c_rx_green_prio_0; 378 u32 c_rx_green_prio_1; 379 u32 c_rx_green_prio_2; 380 u32 c_rx_green_prio_3; 381 u32 c_rx_green_prio_4; 382 u32 c_rx_green_prio_5; 383 u32 c_rx_green_prio_6; 384 u32 c_rx_green_prio_7; 385 u32 reserved[20]; 386 }; 387 388 struct vsc9953_tx_cntrs { 389 u32 c_tx_oct; 390 u32 c_tx_uc; 391 u32 c_tx_mc; 392 u32 c_tx_bc; 393 u32 c_tx_col; 394 u32 c_tx_drop; 395 u32 c_tx_pause; 396 u32 c_tx_sz_64; 397 u32 c_tx_sz_65_127; 398 u32 c_tx_sz_128_255; 399 u32 c_tx_sz_256_511; 400 u32 c_tx_sz_512_1023; 401 u32 c_tx_sz_1024_1526; 402 u32 c_tx_sz_jumbo; 403 u32 c_tx_yellow_prio_0; 404 u32 c_tx_yellow_prio_1; 405 u32 c_tx_yellow_prio_2; 406 u32 c_tx_yellow_prio_3; 407 u32 c_tx_yellow_prio_4; 408 u32 c_tx_yellow_prio_5; 409 u32 c_tx_yellow_prio_6; 410 u32 c_tx_yellow_prio_7; 411 u32 c_tx_green_prio_0; 412 u32 c_tx_green_prio_1; 413 u32 c_tx_green_prio_2; 414 u32 c_tx_green_prio_3; 415 u32 c_tx_green_prio_4; 416 u32 c_tx_green_prio_5; 417 u32 c_tx_green_prio_6; 418 u32 c_tx_green_prio_7; 419 u32 c_tx_aged; 420 u32 reserved[33]; 421 }; 422 423 struct vsc9953_drop_cntrs { 424 u32 c_dr_local; 425 u32 c_dr_tail; 426 u32 c_dr_yellow_prio_0; 427 u32 c_dr_yellow_prio_1; 428 u32 c_dr_yellow_prio_2; 429 u32 c_dr_yellow_prio_3; 430 u32 c_dr_yellow_prio_4; 431 u32 c_dr_yellow_prio_5; 432 u32 c_dr_yellow_prio_6; 433 u32 c_dr_yellow_prio_7; 434 u32 c_dr_green_prio_0; 435 u32 c_dr_green_prio_1; 436 u32 c_dr_green_prio_2; 437 u32 c_dr_green_prio_3; 438 u32 c_dr_green_prio_4; 439 u32 c_dr_green_prio_5; 440 u32 c_dr_green_prio_6; 441 u32 c_dr_green_prio_7; 442 u32 reserved[46]; 443 }; 444 445 struct vsc9953_sys_stat { 446 struct vsc9953_rx_cntrs rx_cntrs; 447 struct vsc9953_tx_cntrs tx_cntrs; 448 struct vsc9953_drop_cntrs drop_cntrs; 449 u32 reserved1[6]; 450 }; 451 452 struct vsc9953_sys_sys { 453 u32 reset_cfg; 454 u32 reserved1; 455 u32 vlan_etype_cfg; 456 u32 port_mode[12]; 457 u32 front_port_mode[10]; 458 u32 frame_aging; 459 u32 stat_cfg; 460 u32 reserved2[50]; 461 }; 462 463 struct vsc9953_sys_pause_cfg { 464 u32 pause_cfg[11]; 465 u32 pause_tot_cfg; 466 u32 tail_drop_level[11]; 467 u32 tot_tail_drop_lvl; 468 u32 mac_fc_cfg[10]; 469 }; 470 471 struct vsc9953_sys_mmgt { 472 u16 free_cnt; 473 }; 474 475 struct vsc9953_system_reg { 476 struct vsc9953_sys_stat stat; 477 struct vsc9953_sys_sys sys; 478 struct vsc9953_sys_pause_cfg pause_cfg; 479 struct vsc9953_sys_mmgt mmgt; 480 }; 481 482 /* END VSC9953 SYS structure */ 483 484 /* VSC9953 REW structure */ 485 486 struct vsc9953_rew_port { 487 u32 port_vlan_cfg; 488 u32 port_tag_cfg; 489 u32 port_port_cfg; 490 u32 port_dscp_cfg; 491 u32 port_pcp_dei_qos_map_cfg[16]; 492 u32 reserved[12]; 493 }; 494 495 struct vsc9953_rew_common { 496 u32 reserve[4]; 497 u32 dscp_remap_dp1_cfg[64]; 498 u32 dscp_remap_cfg[64]; 499 }; 500 501 struct vsc9953_rew_reg { 502 struct vsc9953_rew_port port[12]; 503 struct vsc9953_rew_common common; 504 }; 505 506 /* END VSC9953 REW structure */ 507 508 /* VSC9953 DEVCPU_GCB structure */ 509 510 struct vsc9953_chip_regs { 511 u32 chipd_id; 512 u32 gpr; 513 u32 soft_rst; 514 }; 515 516 struct vsc9953_gpio { 517 u32 gpio_out_set[10]; 518 u32 gpio_out_clr[10]; 519 u32 gpio_out[10]; 520 u32 gpio_in[10]; 521 }; 522 523 struct vsc9953_mii_mng { 524 u32 miimstatus; 525 u32 reserved1; 526 u32 miimcmd; 527 u32 miimdata; 528 u32 miimcfg; 529 u32 miimscan_0; 530 u32 miimscan_1; 531 u32 miiscan_lst_rslts; 532 u32 miiscan_lst_rslts_valid; 533 }; 534 535 struct vsc9953_mii_read_scan { 536 u32 mii_scan_results_sticky[2]; 537 }; 538 539 struct vsc9953_devcpu_gcb { 540 struct vsc9953_chip_regs chip_regs; 541 struct vsc9953_gpio gpio; 542 struct vsc9953_mii_mng mii_mng[2]; 543 struct vsc9953_mii_read_scan mii_read_scan; 544 }; 545 546 /* END VSC9953 DEVCPU_GCB structure */ 547 548 /* VSC9953 IS* structure */ 549 550 struct vsc9953_vcap_core_cfg { 551 u32 vcap_update_ctrl; 552 u32 vcap_mv_cfg; 553 }; 554 555 struct vsc9953_vcap { 556 struct vsc9953_vcap_core_cfg vcap_core_cfg; 557 }; 558 559 /* END VSC9953 IS* structure */ 560 561 #define VSC9953_PORT_INFO_INITIALIZER(idx) \ 562 { \ 563 .enabled = 0, \ 564 .phyaddr = 0, \ 565 .index = idx, \ 566 .phy_regs = NULL, \ 567 .enet_if = PHY_INTERFACE_MODE_NONE, \ 568 .bus = NULL, \ 569 .phydev = NULL, \ 570 } 571 572 /* Structure to describe a VSC9953 port */ 573 struct vsc9953_port_info { 574 u8 enabled; 575 u8 phyaddr; 576 int index; 577 void *phy_regs; 578 phy_interface_t enet_if; 579 struct mii_dev *bus; 580 struct phy_device *phydev; 581 }; 582 583 /* Structure to describe a VSC9953 switch */ 584 struct vsc9953_info { 585 struct vsc9953_port_info port[VSC9953_MAX_PORTS]; 586 }; 587 588 void vsc9953_init(bd_t *bis); 589 590 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); 591 void vsc9953_port_info_set_phy_address(int port_no, int address); 592 void vsc9953_port_enable(int port_no); 593 void vsc9953_port_disable(int port_no); 594 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); 595 596 #endif /* _VSC9953_H_ */ 597