1 /* 2 * vsc9953.h 3 * 4 * Driver for the Vitesse VSC9953 L2 Switch 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2013 Freescale Semiconductor, Inc. 11 * 12 */ 13 14 #ifndef _VSC9953_H_ 15 #define _VSC9953_H_ 16 17 #include <config.h> 18 #include <miiphy.h> 19 #include <asm/types.h> 20 21 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) 22 23 #define VSC9953_SYS_OFFSET 0x010000 24 #define VSC9953_REW_OFFSET 0x030000 25 #define VSC9953_DEV_GMII_OFFSET 0x100000 26 #define VSC9953_QSYS_OFFSET 0x200000 27 #define VSC9953_ANA_OFFSET 0x280000 28 #define VSC9953_DEVCPU_GCB 0x070000 29 #define VSC9953_ES0 0x040000 30 #define VSC9953_IS1 0x050000 31 #define VSC9953_IS2 0x060000 32 33 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 34 #define VSC9953_PHY_REGS_OFFST 0x0000AC 35 36 /* Macros for vsc9953_chip_regs.soft_rst register */ 37 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 38 39 /* Macros for vsc9953_sys_sys.reset_cfg register */ 40 #define VSC9953_CORE_ENABLE 0x80 41 #define VSC9953_MEM_ENABLE 0x40 42 #define VSC9953_MEM_INIT 0x20 43 44 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ 45 #define VSC9953_MAC_ENA_CFG 0x00000011 46 47 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ 48 #define VSC9953_MAC_MODE_CFG 0x00000011 49 50 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ 51 #define VSC9953_MAC_IFG_CFG 0x00000515 52 53 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ 54 #define VSC9953_MAC_HDX_CFG 0x00001043 55 56 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ 57 #define VSC9953_MAC_MAX_LEN 0x000005ee 58 59 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ 60 #define VSC9953_CLOCK_CFG 0x00000001 61 #define VSC9953_CLOCK_CFG_1000M 0x00000001 62 63 /* Macros for vsc9953_sys_sys.front_port_mode register */ 64 #define VSC9953_FRONT_PORT_MODE 0x00000000 65 66 /* Macros for vsc9953_ana_pfc.pfc_cfg register */ 67 #define VSC9953_PFC_FC 0x00000001 68 #define VSC9953_PFC_FC_QSGMII 0x00000000 69 70 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ 71 #define VSC9953_MAC_FC_CFG 0x04700000 72 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 73 74 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ 75 #define VSC9953_PAUSE_CFG 0x001ffffe 76 77 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ 78 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff 79 80 /* Macros for vsc9953_sys_sys.stat_cfg register */ 81 #define VSC9953_STAT_CLEAR_RX 0x00000400 82 #define VSC9953_STAT_CLEAR_TX 0x00000800 83 #define VSC9953_STAT_CLEAR_DR 0x00001000 84 85 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ 86 #define VSC9953_VCAP_MV_CFG 0x0000ffff 87 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 88 89 /* Macros for vsc9953_ana_port.vlan_cfg register */ 90 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 91 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 92 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff 93 94 /* Macros for vsc9953_rew_port.port_vlan_cfg register */ 95 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff 96 97 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ 98 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff 99 100 /* Macros for vsc9953_ana_ana_tables.vlan_access register */ 101 #define VSC9953_VLAN_PORT_MASK 0x00001ffc 102 #define VSC9953_VLAN_CMD_MASK 0x00000003 103 #define VSC9953_VLAN_CMD_IDLE 0x00000000 104 #define VSC9953_VLAN_CMD_READ 0x00000001 105 #define VSC9953_VLAN_CMD_WRITE 0x00000002 106 #define VSC9953_VLAN_CMD_INIT 0x00000003 107 108 /* Macros for vsc9953_ana_port.port_cfg register */ 109 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080 110 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 111 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 112 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 113 114 /* Macros for vsc9953_qsys_sys.switch_port_mode register */ 115 #define VSC9953_PORT_ENA 0x00002000 116 117 /* Macros for vsc9953_ana_ana.adv_learn register */ 118 #define VSC9953_VLAN_CHK 0x00000400 119 120 /* Macros for vsc9953_rew_port.port_tag_cfg register */ 121 #define VSC9953_TAG_CFG_MASK 0x00000180 122 #define VSC9953_TAG_CFG_NONE 0x00000000 123 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 124 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 125 #define VSC9953_TAG_CFG_ALL 0x00000180 126 127 #define VSC9953_MAX_PORTS 10 128 #define VSC9953_PORT_CHECK(port) \ 129 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) 130 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \ 131 ( \ 132 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ 133 ) ? 0 : 1 \ 134 ) 135 #define VSC9953_MAX_VLAN 4096 136 #define VSC9953_VLAN_CHECK(vid) \ 137 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) 138 139 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" 140 141 #define MIIMIND_OPR_PEND 0x00000004 142 143 struct vsc9953_mdio_info { 144 struct vsc9953_mii_mng *regs; 145 char *name; 146 }; 147 148 /* VSC9953 ANA structure */ 149 150 struct vsc9953_ana_port { 151 u32 vlan_cfg; 152 u32 drop_cfg; 153 u32 qos_cfg; 154 u32 vcap_cfg; 155 u32 vcap_s1_key_cfg[3]; 156 u32 vcap_s2_cfg; 157 u32 qos_pcp_dei_map_cfg[16]; 158 u32 cpu_fwd_cfg; 159 u32 cpu_fwd_bpdu_cfg; 160 u32 cpu_fwd_garp_cfg; 161 u32 cpu_fwd_ccm_cfg; 162 u32 port_cfg; 163 u32 pol_cfg; 164 u32 reserved[34]; 165 }; 166 167 struct vsc9953_ana_pol { 168 u32 pol_pir_cfg; 169 u32 pol_cir_cfg; 170 u32 pol_mode_cfg; 171 u32 pol_pir_state; 172 u32 pol_cir_state; 173 u32 reserved1[3]; 174 }; 175 176 struct vsc9953_ana_ana_tables { 177 u32 entry_lim[11]; 178 u32 an_moved; 179 u32 mach_data; 180 u32 macl_data; 181 u32 mac_access; 182 u32 mact_indx; 183 u32 vlan_access; 184 u32 vlan_tidx; 185 }; 186 187 struct vsc9953_ana_ana { 188 u32 adv_learn; 189 u32 vlan_mask; 190 u32 reserved; 191 u32 anag_efil; 192 u32 an_events; 193 u32 storm_limit_burst; 194 u32 storm_limit_cfg[4]; 195 u32 isolated_prts; 196 u32 community_ports; 197 u32 auto_age; 198 u32 mac_options; 199 u32 learn_disc; 200 u32 agen_ctrl; 201 u32 mirror_ports; 202 u32 emirror_ports; 203 u32 flooding; 204 u32 flooding_ipmc; 205 u32 sflow_cfg[11]; 206 u32 port_mode[12]; 207 }; 208 209 struct vsc9953_ana_pgid { 210 u32 port_grp_id[91]; 211 }; 212 213 struct vsc9953_ana_pfc { 214 u32 pfc_cfg; 215 u32 reserved1[15]; 216 }; 217 218 struct vsc9953_ana_pol_misc { 219 u32 pol_flowc[10]; 220 u32 reserved1[17]; 221 u32 pol_hyst; 222 }; 223 224 struct vsc9953_ana_common { 225 u32 aggr_cfg; 226 u32 cpuq_cfg; 227 u32 cpuq_8021_cfg; 228 u32 dscp_cfg; 229 u32 dscp_rewr_cfg; 230 u32 vcap_rng_type_cfg; 231 u32 vcap_rng_val_cfg; 232 u32 discard_cfg; 233 u32 fid_cfg; 234 }; 235 236 struct vsc9953_analyzer { 237 struct vsc9953_ana_port port[11]; 238 u32 reserved1[9536]; 239 struct vsc9953_ana_pol pol[164]; 240 struct vsc9953_ana_ana_tables ana_tables; 241 u32 reserved2[14]; 242 struct vsc9953_ana_ana ana; 243 u32 reserved3[22]; 244 struct vsc9953_ana_pgid port_id_tbl; 245 u32 reserved4[549]; 246 struct vsc9953_ana_pfc pfc[10]; 247 struct vsc9953_ana_pol_misc pol_misc; 248 u32 reserved5[196]; 249 struct vsc9953_ana_common common; 250 }; 251 /* END VSC9953 ANA structure t*/ 252 253 /* VSC9953 DEV_GMII structure */ 254 255 struct vsc9953_dev_gmii_port_mode { 256 u32 clock_cfg; 257 u32 port_misc; 258 u32 reserved1; 259 u32 eee_cfg; 260 }; 261 262 struct vsc9953_dev_gmii_mac_cfg_status { 263 u32 mac_ena_cfg; 264 u32 mac_mode_cfg; 265 u32 mac_maxlen_cfg; 266 u32 mac_tags_cfg; 267 u32 mac_adv_chk_cfg; 268 u32 mac_ifg_cfg; 269 u32 mac_hdx_cfg; 270 u32 mac_fc_mac_low_cfg; 271 u32 mac_fc_mac_high_cfg; 272 u32 mac_sticky; 273 }; 274 275 struct vsc9953_dev_gmii { 276 struct vsc9953_dev_gmii_port_mode port_mode; 277 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; 278 }; 279 280 /* END VSC9953 DEV_GMII structure */ 281 282 /* VSC9953 QSYS structure */ 283 284 struct vsc9953_qsys_hsch { 285 u32 cir_cfg; 286 u32 reserved1; 287 u32 se_cfg; 288 u32 se_dwrr_cfg[8]; 289 u32 cir_state; 290 u32 reserved2[20]; 291 }; 292 293 struct vsc9953_qsys_sys { 294 u32 port_mode[12]; 295 u32 switch_port_mode[11]; 296 u32 stat_cnt_cfg; 297 u32 eee_cfg[10]; 298 u32 eee_thrs; 299 u32 igr_no_sharing; 300 u32 egr_no_sharing; 301 u32 sw_status[11]; 302 u32 ext_cpu_cfg; 303 u32 cpu_group_map; 304 u32 reserved1[23]; 305 }; 306 307 struct vsc9953_qsys_qos_cfg { 308 u32 red_profile[16]; 309 u32 res_qos_mode; 310 }; 311 312 struct vsc9953_qsys_drop_cfg { 313 u32 egr_drop_mode; 314 }; 315 316 struct vsc9953_qsys_mmgt { 317 u32 eq_cntrl; 318 u32 reserved1; 319 }; 320 321 struct vsc9953_qsys_hsch_misc { 322 u32 hsch_misc_cfg; 323 u32 reserved1[546]; 324 }; 325 326 struct vsc9953_qsys_res_ctrl { 327 u32 res_cfg; 328 u32 res_stat; 329 330 }; 331 332 struct vsc9953_qsys_reg { 333 struct vsc9953_qsys_hsch hsch[108]; 334 struct vsc9953_qsys_sys sys; 335 struct vsc9953_qsys_qos_cfg qos_cfg; 336 struct vsc9953_qsys_drop_cfg drop_cfg; 337 struct vsc9953_qsys_mmgt mmgt; 338 struct vsc9953_qsys_hsch_misc hsch_misc; 339 struct vsc9953_qsys_res_ctrl res_ctrl[1024]; 340 }; 341 342 /* END VSC9953 QSYS structure */ 343 344 /* VSC9953 SYS structure */ 345 346 struct vsc9953_rx_cntrs { 347 u32 c_rx_oct; 348 u32 c_rx_uc; 349 u32 c_rx_mc; 350 u32 c_rx_bc; 351 u32 c_rx_short; 352 u32 c_rx_frag; 353 u32 c_rx_jabber; 354 u32 c_rx_crc; 355 u32 c_rx_symbol_err; 356 u32 c_rx_sz_64; 357 u32 c_rx_sz_65_127; 358 u32 c_rx_sz_128_255; 359 u32 c_rx_sz_256_511; 360 u32 c_rx_sz_512_1023; 361 u32 c_rx_sz_1024_1526; 362 u32 c_rx_sz_jumbo; 363 u32 c_rx_pause; 364 u32 c_rx_control; 365 u32 c_rx_long; 366 u32 c_rx_cat_drop; 367 u32 c_rx_red_prio_0; 368 u32 c_rx_red_prio_1; 369 u32 c_rx_red_prio_2; 370 u32 c_rx_red_prio_3; 371 u32 c_rx_red_prio_4; 372 u32 c_rx_red_prio_5; 373 u32 c_rx_red_prio_6; 374 u32 c_rx_red_prio_7; 375 u32 c_rx_yellow_prio_0; 376 u32 c_rx_yellow_prio_1; 377 u32 c_rx_yellow_prio_2; 378 u32 c_rx_yellow_prio_3; 379 u32 c_rx_yellow_prio_4; 380 u32 c_rx_yellow_prio_5; 381 u32 c_rx_yellow_prio_6; 382 u32 c_rx_yellow_prio_7; 383 u32 c_rx_green_prio_0; 384 u32 c_rx_green_prio_1; 385 u32 c_rx_green_prio_2; 386 u32 c_rx_green_prio_3; 387 u32 c_rx_green_prio_4; 388 u32 c_rx_green_prio_5; 389 u32 c_rx_green_prio_6; 390 u32 c_rx_green_prio_7; 391 u32 reserved[20]; 392 }; 393 394 struct vsc9953_tx_cntrs { 395 u32 c_tx_oct; 396 u32 c_tx_uc; 397 u32 c_tx_mc; 398 u32 c_tx_bc; 399 u32 c_tx_col; 400 u32 c_tx_drop; 401 u32 c_tx_pause; 402 u32 c_tx_sz_64; 403 u32 c_tx_sz_65_127; 404 u32 c_tx_sz_128_255; 405 u32 c_tx_sz_256_511; 406 u32 c_tx_sz_512_1023; 407 u32 c_tx_sz_1024_1526; 408 u32 c_tx_sz_jumbo; 409 u32 c_tx_yellow_prio_0; 410 u32 c_tx_yellow_prio_1; 411 u32 c_tx_yellow_prio_2; 412 u32 c_tx_yellow_prio_3; 413 u32 c_tx_yellow_prio_4; 414 u32 c_tx_yellow_prio_5; 415 u32 c_tx_yellow_prio_6; 416 u32 c_tx_yellow_prio_7; 417 u32 c_tx_green_prio_0; 418 u32 c_tx_green_prio_1; 419 u32 c_tx_green_prio_2; 420 u32 c_tx_green_prio_3; 421 u32 c_tx_green_prio_4; 422 u32 c_tx_green_prio_5; 423 u32 c_tx_green_prio_6; 424 u32 c_tx_green_prio_7; 425 u32 c_tx_aged; 426 u32 reserved[33]; 427 }; 428 429 struct vsc9953_drop_cntrs { 430 u32 c_dr_local; 431 u32 c_dr_tail; 432 u32 c_dr_yellow_prio_0; 433 u32 c_dr_yellow_prio_1; 434 u32 c_dr_yellow_prio_2; 435 u32 c_dr_yellow_prio_3; 436 u32 c_dr_yellow_prio_4; 437 u32 c_dr_yellow_prio_5; 438 u32 c_dr_yellow_prio_6; 439 u32 c_dr_yellow_prio_7; 440 u32 c_dr_green_prio_0; 441 u32 c_dr_green_prio_1; 442 u32 c_dr_green_prio_2; 443 u32 c_dr_green_prio_3; 444 u32 c_dr_green_prio_4; 445 u32 c_dr_green_prio_5; 446 u32 c_dr_green_prio_6; 447 u32 c_dr_green_prio_7; 448 u32 reserved[46]; 449 }; 450 451 struct vsc9953_sys_stat { 452 struct vsc9953_rx_cntrs rx_cntrs; 453 struct vsc9953_tx_cntrs tx_cntrs; 454 struct vsc9953_drop_cntrs drop_cntrs; 455 u32 reserved1[6]; 456 }; 457 458 struct vsc9953_sys_sys { 459 u32 reset_cfg; 460 u32 reserved1; 461 u32 vlan_etype_cfg; 462 u32 port_mode[12]; 463 u32 front_port_mode[10]; 464 u32 frame_aging; 465 u32 stat_cfg; 466 u32 reserved2[50]; 467 }; 468 469 struct vsc9953_sys_pause_cfg { 470 u32 pause_cfg[11]; 471 u32 pause_tot_cfg; 472 u32 tail_drop_level[11]; 473 u32 tot_tail_drop_lvl; 474 u32 mac_fc_cfg[10]; 475 }; 476 477 struct vsc9953_sys_mmgt { 478 u16 free_cnt; 479 }; 480 481 struct vsc9953_system_reg { 482 struct vsc9953_sys_stat stat; 483 struct vsc9953_sys_sys sys; 484 struct vsc9953_sys_pause_cfg pause_cfg; 485 struct vsc9953_sys_mmgt mmgt; 486 }; 487 488 /* END VSC9953 SYS structure */ 489 490 /* VSC9953 REW structure */ 491 492 struct vsc9953_rew_port { 493 u32 port_vlan_cfg; 494 u32 port_tag_cfg; 495 u32 port_port_cfg; 496 u32 port_dscp_cfg; 497 u32 port_pcp_dei_qos_map_cfg[16]; 498 u32 reserved[12]; 499 }; 500 501 struct vsc9953_rew_common { 502 u32 reserve[4]; 503 u32 dscp_remap_dp1_cfg[64]; 504 u32 dscp_remap_cfg[64]; 505 }; 506 507 struct vsc9953_rew_reg { 508 struct vsc9953_rew_port port[12]; 509 struct vsc9953_rew_common common; 510 }; 511 512 /* END VSC9953 REW structure */ 513 514 /* VSC9953 DEVCPU_GCB structure */ 515 516 struct vsc9953_chip_regs { 517 u32 chipd_id; 518 u32 gpr; 519 u32 soft_rst; 520 }; 521 522 struct vsc9953_gpio { 523 u32 gpio_out_set[10]; 524 u32 gpio_out_clr[10]; 525 u32 gpio_out[10]; 526 u32 gpio_in[10]; 527 }; 528 529 struct vsc9953_mii_mng { 530 u32 miimstatus; 531 u32 reserved1; 532 u32 miimcmd; 533 u32 miimdata; 534 u32 miimcfg; 535 u32 miimscan_0; 536 u32 miimscan_1; 537 u32 miiscan_lst_rslts; 538 u32 miiscan_lst_rslts_valid; 539 }; 540 541 struct vsc9953_mii_read_scan { 542 u32 mii_scan_results_sticky[2]; 543 }; 544 545 struct vsc9953_devcpu_gcb { 546 struct vsc9953_chip_regs chip_regs; 547 struct vsc9953_gpio gpio; 548 struct vsc9953_mii_mng mii_mng[2]; 549 struct vsc9953_mii_read_scan mii_read_scan; 550 }; 551 552 /* END VSC9953 DEVCPU_GCB structure */ 553 554 /* VSC9953 IS* structure */ 555 556 struct vsc9953_vcap_core_cfg { 557 u32 vcap_update_ctrl; 558 u32 vcap_mv_cfg; 559 }; 560 561 struct vsc9953_vcap { 562 struct vsc9953_vcap_core_cfg vcap_core_cfg; 563 }; 564 565 /* END VSC9953 IS* structure */ 566 567 #define VSC9953_PORT_INFO_INITIALIZER(idx) \ 568 { \ 569 .enabled = 0, \ 570 .phyaddr = 0, \ 571 .index = idx, \ 572 .phy_regs = NULL, \ 573 .enet_if = PHY_INTERFACE_MODE_NONE, \ 574 .bus = NULL, \ 575 .phydev = NULL, \ 576 } 577 578 /* Structure to describe a VSC9953 port */ 579 struct vsc9953_port_info { 580 u8 enabled; 581 u8 phyaddr; 582 int index; 583 void *phy_regs; 584 phy_interface_t enet_if; 585 struct mii_dev *bus; 586 struct phy_device *phydev; 587 }; 588 589 /* Structure to describe a VSC9953 switch */ 590 struct vsc9953_info { 591 struct vsc9953_port_info port[VSC9953_MAX_PORTS]; 592 }; 593 594 void vsc9953_init(bd_t *bis); 595 596 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); 597 void vsc9953_port_info_set_phy_address(int port_no, int address); 598 void vsc9953_port_enable(int port_no); 599 void vsc9953_port_disable(int port_no); 600 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); 601 602 #endif /* _VSC9953_H_ */ 603