1 /* 2 * vsc9953.h 3 * 4 * Driver for the Vitesse VSC9953 L2 Switch 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2013 Freescale Semiconductor, Inc. 11 * 12 */ 13 14 #ifndef _VSC9953_H_ 15 #define _VSC9953_H_ 16 17 #include <config.h> 18 #include <miiphy.h> 19 #include <asm/types.h> 20 21 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) 22 23 #define VSC9953_SYS_OFFSET 0x010000 24 #define VSC9953_DEV_GMII_OFFSET 0x100000 25 #define VSC9953_QSYS_OFFSET 0x200000 26 #define VSC9953_ANA_OFFSET 0x280000 27 #define VSC9953_DEVCPU_GCB 0x070000 28 #define VSC9953_ES0 0x040000 29 #define VSC9953_IS1 0x050000 30 #define VSC9953_IS2 0x060000 31 32 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 33 #define VSC9953_PHY_REGS_OFFST 0x0000AC 34 35 /* Macros for vsc9953_chip_regs.soft_rst register */ 36 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 37 38 /* Macros for vsc9953_sys_sys.reset_cfg register */ 39 #define VSC9953_CORE_ENABLE 0x80 40 #define VSC9953_MEM_ENABLE 0x40 41 #define VSC9953_MEM_INIT 0x20 42 43 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ 44 #define VSC9953_MAC_ENA_CFG 0x00000011 45 46 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ 47 #define VSC9953_MAC_MODE_CFG 0x00000011 48 49 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ 50 #define VSC9953_MAC_IFG_CFG 0x00000515 51 52 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ 53 #define VSC9953_MAC_HDX_CFG 0x00001043 54 55 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ 56 #define VSC9953_MAC_MAX_LEN 0x000005ee 57 58 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ 59 #define VSC9953_CLOCK_CFG 0x00000001 60 #define VSC9953_CLOCK_CFG_1000M 0x00000001 61 62 /* Macros for vsc9953_sys_sys.front_port_mode register */ 63 #define VSC9953_FRONT_PORT_MODE 0x00000000 64 65 /* Macros for vsc9953_ana_pfc.pfc_cfg register */ 66 #define VSC9953_PFC_FC 0x00000001 67 #define VSC9953_PFC_FC_QSGMII 0x00000000 68 69 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ 70 #define VSC9953_MAC_FC_CFG 0x04700000 71 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 72 73 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ 74 #define VSC9953_PAUSE_CFG 0x001ffffe 75 76 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ 77 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff 78 79 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ 80 #define VSC9953_VCAP_MV_CFG 0x0000ffff 81 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 82 83 /* Macros for vsc9953_qsys_sys.switch_port_mode register */ 84 #define VSC9953_PORT_ENA 0x00002000 85 86 #define VSC9953_MAX_PORTS 10 87 #define VSC9953_PORT_CHECK(port) \ 88 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) 89 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \ 90 ( \ 91 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ 92 ) ? 0 : 1 \ 93 ) 94 95 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" 96 97 #define MIIMIND_OPR_PEND 0x00000004 98 99 struct vsc9953_mdio_info { 100 struct vsc9953_mii_mng *regs; 101 char *name; 102 }; 103 104 /* VSC9953 ANA structure */ 105 106 struct vsc9953_ana_port { 107 u32 vlan_cfg; 108 u32 drop_cfg; 109 u32 qos_cfg; 110 u32 vcap_cfg; 111 u32 vcap_s1_key_cfg[3]; 112 u32 vcap_s2_cfg; 113 u32 qos_pcp_dei_map_cfg[16]; 114 u32 cpu_fwd_cfg; 115 u32 cpu_fwd_bpdu_cfg; 116 u32 cpu_fwd_garp_cfg; 117 u32 cpu_fwd_ccm_cfg; 118 u32 port_cfg; 119 u32 pol_cfg; 120 u32 reserved[34]; 121 }; 122 123 struct vsc9953_ana_pol { 124 u32 pol_pir_cfg; 125 u32 pol_cir_cfg; 126 u32 pol_mode_cfg; 127 u32 pol_pir_state; 128 u32 pol_cir_state; 129 u32 reserved1[3]; 130 }; 131 132 struct vsc9953_ana_ana_tables { 133 u32 entry_lim[11]; 134 u32 an_moved; 135 u32 mach_data; 136 u32 macl_data; 137 u32 mac_access; 138 u32 mact_indx; 139 u32 vlan_access; 140 u32 vlan_tidx; 141 }; 142 143 struct vsc9953_ana_ana { 144 u32 adv_learn; 145 u32 vlan_mask; 146 u32 reserved; 147 u32 anag_efil; 148 u32 an_events; 149 u32 storm_limit_burst; 150 u32 storm_limit_cfg[4]; 151 u32 isolated_prts; 152 u32 community_ports; 153 u32 auto_age; 154 u32 mac_options; 155 u32 learn_disc; 156 u32 agen_ctrl; 157 u32 mirror_ports; 158 u32 emirror_ports; 159 u32 flooding; 160 u32 flooding_ipmc; 161 u32 sflow_cfg[11]; 162 u32 port_mode[12]; 163 }; 164 165 struct vsc9953_ana_pgid { 166 u32 port_grp_id[91]; 167 }; 168 169 struct vsc9953_ana_pfc { 170 u32 pfc_cfg; 171 u32 reserved1[15]; 172 }; 173 174 struct vsc9953_ana_pol_misc { 175 u32 pol_flowc[10]; 176 u32 reserved1[17]; 177 u32 pol_hyst; 178 }; 179 180 struct vsc9953_ana_common { 181 u32 aggr_cfg; 182 u32 cpuq_cfg; 183 u32 cpuq_8021_cfg; 184 u32 dscp_cfg; 185 u32 dscp_rewr_cfg; 186 u32 vcap_rng_type_cfg; 187 u32 vcap_rng_val_cfg; 188 u32 discard_cfg; 189 u32 fid_cfg; 190 }; 191 192 struct vsc9953_analyzer { 193 struct vsc9953_ana_port port[11]; 194 u32 reserved1[9536]; 195 struct vsc9953_ana_pol pol[164]; 196 struct vsc9953_ana_ana_tables ana_tables; 197 u32 reserved2[14]; 198 struct vsc9953_ana_ana ana; 199 u32 reserved3[22]; 200 struct vsc9953_ana_pgid port_id_tbl; 201 u32 reserved4[549]; 202 struct vsc9953_ana_pfc pfc[10]; 203 struct vsc9953_ana_pol_misc pol_misc; 204 u32 reserved5[196]; 205 struct vsc9953_ana_common common; 206 }; 207 /* END VSC9953 ANA structure t*/ 208 209 /* VSC9953 DEV_GMII structure */ 210 211 struct vsc9953_dev_gmii_port_mode { 212 u32 clock_cfg; 213 u32 port_misc; 214 u32 reserved1; 215 u32 eee_cfg; 216 }; 217 218 struct vsc9953_dev_gmii_mac_cfg_status { 219 u32 mac_ena_cfg; 220 u32 mac_mode_cfg; 221 u32 mac_maxlen_cfg; 222 u32 mac_tags_cfg; 223 u32 mac_adv_chk_cfg; 224 u32 mac_ifg_cfg; 225 u32 mac_hdx_cfg; 226 u32 mac_fc_mac_low_cfg; 227 u32 mac_fc_mac_high_cfg; 228 u32 mac_sticky; 229 }; 230 231 struct vsc9953_dev_gmii { 232 struct vsc9953_dev_gmii_port_mode port_mode; 233 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; 234 }; 235 236 /* END VSC9953 DEV_GMII structure */ 237 238 /* VSC9953 QSYS structure */ 239 240 struct vsc9953_qsys_hsch { 241 u32 cir_cfg; 242 u32 reserved1; 243 u32 se_cfg; 244 u32 se_dwrr_cfg[8]; 245 u32 cir_state; 246 u32 reserved2[20]; 247 }; 248 249 struct vsc9953_qsys_sys { 250 u32 port_mode[12]; 251 u32 switch_port_mode[11]; 252 u32 stat_cnt_cfg; 253 u32 eee_cfg[10]; 254 u32 eee_thrs; 255 u32 igr_no_sharing; 256 u32 egr_no_sharing; 257 u32 sw_status[11]; 258 u32 ext_cpu_cfg; 259 u32 cpu_group_map; 260 u32 reserved1[23]; 261 }; 262 263 struct vsc9953_qsys_qos_cfg { 264 u32 red_profile[16]; 265 u32 res_qos_mode; 266 }; 267 268 struct vsc9953_qsys_drop_cfg { 269 u32 egr_drop_mode; 270 }; 271 272 struct vsc9953_qsys_mmgt { 273 u32 eq_cntrl; 274 u32 reserved1; 275 }; 276 277 struct vsc9953_qsys_hsch_misc { 278 u32 hsch_misc_cfg; 279 u32 reserved1[546]; 280 }; 281 282 struct vsc9953_qsys_res_ctrl { 283 u32 res_cfg; 284 u32 res_stat; 285 286 }; 287 288 struct vsc9953_qsys_reg { 289 struct vsc9953_qsys_hsch hsch[108]; 290 struct vsc9953_qsys_sys sys; 291 struct vsc9953_qsys_qos_cfg qos_cfg; 292 struct vsc9953_qsys_drop_cfg drop_cfg; 293 struct vsc9953_qsys_mmgt mmgt; 294 struct vsc9953_qsys_hsch_misc hsch_misc; 295 struct vsc9953_qsys_res_ctrl res_ctrl[1024]; 296 }; 297 298 /* END VSC9953 QSYS structure */ 299 300 /* VSC9953 SYS structure */ 301 302 struct vsc9953_sys_stat { 303 u32 rx_cntrs[64]; 304 u32 tx_cntrs[64]; 305 u32 drop_cntrs[64]; 306 u32 reserved1[6]; 307 }; 308 309 struct vsc9953_sys_sys { 310 u32 reset_cfg; 311 u32 reserved1; 312 u32 vlan_etype_cfg; 313 u32 port_mode[12]; 314 u32 front_port_mode[10]; 315 u32 frame_aging; 316 u32 stat_cfg; 317 u32 reserved2[50]; 318 }; 319 320 struct vsc9953_sys_pause_cfg { 321 u32 pause_cfg[11]; 322 u32 pause_tot_cfg; 323 u32 tail_drop_level[11]; 324 u32 tot_tail_drop_lvl; 325 u32 mac_fc_cfg[10]; 326 }; 327 328 struct vsc9953_sys_mmgt { 329 u16 free_cnt; 330 }; 331 332 struct vsc9953_system_reg { 333 struct vsc9953_sys_stat stat; 334 struct vsc9953_sys_sys sys; 335 struct vsc9953_sys_pause_cfg pause_cfg; 336 struct vsc9953_sys_mmgt mmgt; 337 }; 338 339 /* END VSC9953 SYS structure */ 340 341 342 /* VSC9953 DEVCPU_GCB structure */ 343 344 struct vsc9953_chip_regs { 345 u32 chipd_id; 346 u32 gpr; 347 u32 soft_rst; 348 }; 349 350 struct vsc9953_gpio { 351 u32 gpio_out_set[10]; 352 u32 gpio_out_clr[10]; 353 u32 gpio_out[10]; 354 u32 gpio_in[10]; 355 }; 356 357 struct vsc9953_mii_mng { 358 u32 miimstatus; 359 u32 reserved1; 360 u32 miimcmd; 361 u32 miimdata; 362 u32 miimcfg; 363 u32 miimscan_0; 364 u32 miimscan_1; 365 u32 miiscan_lst_rslts; 366 u32 miiscan_lst_rslts_valid; 367 }; 368 369 struct vsc9953_mii_read_scan { 370 u32 mii_scan_results_sticky[2]; 371 }; 372 373 struct vsc9953_devcpu_gcb { 374 struct vsc9953_chip_regs chip_regs; 375 struct vsc9953_gpio gpio; 376 struct vsc9953_mii_mng mii_mng[2]; 377 struct vsc9953_mii_read_scan mii_read_scan; 378 }; 379 380 /* END VSC9953 DEVCPU_GCB structure */ 381 382 /* VSC9953 IS* structure */ 383 384 struct vsc9953_vcap_core_cfg { 385 u32 vcap_update_ctrl; 386 u32 vcap_mv_cfg; 387 }; 388 389 struct vsc9953_vcap { 390 struct vsc9953_vcap_core_cfg vcap_core_cfg; 391 }; 392 393 /* END VSC9953 IS* structure */ 394 395 #define VSC9953_PORT_INFO_INITIALIZER(idx) \ 396 { \ 397 .enabled = 0, \ 398 .phyaddr = 0, \ 399 .index = idx, \ 400 .phy_regs = NULL, \ 401 .enet_if = PHY_INTERFACE_MODE_NONE, \ 402 .bus = NULL, \ 403 .phydev = NULL, \ 404 } 405 406 /* Structure to describe a VSC9953 port */ 407 struct vsc9953_port_info { 408 u8 enabled; 409 u8 phyaddr; 410 int index; 411 void *phy_regs; 412 phy_interface_t enet_if; 413 struct mii_dev *bus; 414 struct phy_device *phydev; 415 }; 416 417 /* Structure to describe a VSC9953 switch */ 418 struct vsc9953_info { 419 struct vsc9953_port_info port[VSC9953_MAX_PORTS]; 420 }; 421 422 void vsc9953_init(bd_t *bis); 423 424 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); 425 void vsc9953_port_info_set_phy_address(int port_no, int address); 426 void vsc9953_port_enable(int port_no); 427 void vsc9953_port_disable(int port_no); 428 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); 429 430 #endif /* _VSC9953_H_ */ 431