1 /* 2 * vsc9953.h 3 * 4 * Driver for the Vitesse VSC9953 L2 Switch 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2013 Freescale Semiconductor, Inc. 11 * 12 */ 13 14 #ifndef _VSC9953_H_ 15 #define _VSC9953_H_ 16 17 #include <config.h> 18 #include <miiphy.h> 19 #include <asm/types.h> 20 21 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) 22 23 #define VSC9953_SYS_OFFSET 0x010000 24 #define VSC9953_REW_OFFSET 0x030000 25 #define VSC9953_DEV_GMII_OFFSET 0x100000 26 #define VSC9953_QSYS_OFFSET 0x200000 27 #define VSC9953_ANA_OFFSET 0x280000 28 #define VSC9953_DEVCPU_GCB 0x070000 29 #define VSC9953_ES0 0x040000 30 #define VSC9953_IS1 0x050000 31 #define VSC9953_IS2 0x060000 32 33 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 34 #define VSC9953_PHY_REGS_OFFST 0x0000AC 35 36 /* Macros for vsc9953_chip_regs.soft_rst register */ 37 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 38 39 /* Macros for vsc9953_sys_sys.reset_cfg register */ 40 #define VSC9953_CORE_ENABLE 0x80 41 #define VSC9953_MEM_ENABLE 0x40 42 #define VSC9953_MEM_INIT 0x20 43 44 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ 45 #define VSC9953_MAC_ENA_CFG 0x00000011 46 47 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ 48 #define VSC9953_MAC_MODE_CFG 0x00000011 49 50 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ 51 #define VSC9953_MAC_IFG_CFG 0x00000515 52 53 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ 54 #define VSC9953_MAC_HDX_CFG 0x00001043 55 56 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ 57 #define VSC9953_MAC_MAX_LEN 0x000005ee 58 59 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ 60 #define VSC9953_CLOCK_CFG 0x00000001 61 #define VSC9953_CLOCK_CFG_1000M 0x00000001 62 63 /* Macros for vsc9953_sys_sys.front_port_mode register */ 64 #define VSC9953_FRONT_PORT_MODE 0x00000000 65 66 /* Macros for vsc9953_ana_pfc.pfc_cfg register */ 67 #define VSC9953_PFC_FC 0x00000001 68 #define VSC9953_PFC_FC_QSGMII 0x00000000 69 70 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ 71 #define VSC9953_MAC_FC_CFG 0x04700000 72 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 73 74 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ 75 #define VSC9953_PAUSE_CFG 0x001ffffe 76 77 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ 78 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff 79 80 /* Macros for vsc9953_sys_sys.stat_cfg register */ 81 #define VSC9953_STAT_CLEAR_RX 0x00000400 82 #define VSC9953_STAT_CLEAR_TX 0x00000800 83 #define VSC9953_STAT_CLEAR_DR 0x00001000 84 85 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ 86 #define VSC9953_VCAP_MV_CFG 0x0000ffff 87 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 88 89 /* Macros for register vsc9953_ana_ana_tables.mac_access register */ 90 #define VSC9953_MAC_CMD_IDLE 0x00000000 91 #define VSC9953_MAC_CMD_LEARN 0x00000001 92 #define VSC9953_MAC_CMD_FORGET 0x00000002 93 #define VSC9953_MAC_CMD_AGE 0x00000003 94 #define VSC9953_MAC_CMD_NEXT 0x00000004 95 #define VSC9953_MAC_CMD_READ 0x00000006 96 #define VSC9953_MAC_CMD_WRITE 0x00000007 97 #define VSC9953_MAC_CMD_MASK 0x00000007 98 #define VSC9953_MAC_CMD_VALID 0x00000800 99 #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000 100 #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200 101 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400 102 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600 103 #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600 104 #define VSC9953_MAC_DESTIDX_MASK 0x000001f8 105 #define VSC9953_MAC_VID_MASK 0x1fff0000 106 #define VSC9953_MAC_MACH_MASK 0x0000ffff 107 108 /* Macros for vsc9953_ana_port.vlan_cfg register */ 109 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 110 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 111 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff 112 113 /* Macros for vsc9953_rew_port.port_vlan_cfg register */ 114 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff 115 116 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ 117 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff 118 119 /* Macros for vsc9953_ana_ana_tables.vlan_access register */ 120 #define VSC9953_VLAN_PORT_MASK 0x00001ffc 121 #define VSC9953_VLAN_CMD_MASK 0x00000003 122 #define VSC9953_VLAN_CMD_IDLE 0x00000000 123 #define VSC9953_VLAN_CMD_READ 0x00000001 124 #define VSC9953_VLAN_CMD_WRITE 0x00000002 125 #define VSC9953_VLAN_CMD_INIT 0x00000003 126 127 /* Macros for vsc9953_ana_port.port_cfg register */ 128 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080 129 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 130 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 131 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 132 133 /* Macros for vsc9953_qsys_sys.switch_port_mode register */ 134 #define VSC9953_PORT_ENA 0x00002000 135 136 /* Macros for vsc9953_ana_ana.adv_learn register */ 137 #define VSC9953_VLAN_CHK 0x00000400 138 139 /* Macros for vsc9953_rew_port.port_tag_cfg register */ 140 #define VSC9953_TAG_CFG_MASK 0x00000180 141 #define VSC9953_TAG_CFG_NONE 0x00000000 142 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 143 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 144 #define VSC9953_TAG_CFG_ALL 0x00000180 145 146 /* Macros for vsc9953_ana_ana.anag_efil register */ 147 #define VSC9953_AGE_PORT_EN 0x00080000 148 #define VSC9953_AGE_PORT_MASK 0x0007c000 149 #define VSC9953_AGE_VID_EN 0x00002000 150 #define VSC9953_AGE_VID_MASK 0x00001fff 151 152 /* Macros for vsc9953_ana_ana_tables.mach_data register */ 153 #define VSC9953_MACHDATA_VID_MASK 0x1fff0000 154 155 #define VSC9953_MAX_PORTS 10 156 #define VSC9953_PORT_CHECK(port) \ 157 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) 158 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \ 159 ( \ 160 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ 161 ) ? 0 : 1 \ 162 ) 163 #define VSC9953_MAX_VLAN 4096 164 #define VSC9953_VLAN_CHECK(vid) \ 165 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) 166 167 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" 168 169 #define MIIMIND_OPR_PEND 0x00000004 170 171 struct vsc9953_mdio_info { 172 struct vsc9953_mii_mng *regs; 173 char *name; 174 }; 175 176 /* VSC9953 ANA structure */ 177 178 struct vsc9953_ana_port { 179 u32 vlan_cfg; 180 u32 drop_cfg; 181 u32 qos_cfg; 182 u32 vcap_cfg; 183 u32 vcap_s1_key_cfg[3]; 184 u32 vcap_s2_cfg; 185 u32 qos_pcp_dei_map_cfg[16]; 186 u32 cpu_fwd_cfg; 187 u32 cpu_fwd_bpdu_cfg; 188 u32 cpu_fwd_garp_cfg; 189 u32 cpu_fwd_ccm_cfg; 190 u32 port_cfg; 191 u32 pol_cfg; 192 u32 reserved[34]; 193 }; 194 195 struct vsc9953_ana_pol { 196 u32 pol_pir_cfg; 197 u32 pol_cir_cfg; 198 u32 pol_mode_cfg; 199 u32 pol_pir_state; 200 u32 pol_cir_state; 201 u32 reserved1[3]; 202 }; 203 204 struct vsc9953_ana_ana_tables { 205 u32 entry_lim[11]; 206 u32 an_moved; 207 u32 mach_data; 208 u32 macl_data; 209 u32 mac_access; 210 u32 mact_indx; 211 u32 vlan_access; 212 u32 vlan_tidx; 213 }; 214 215 struct vsc9953_ana_ana { 216 u32 adv_learn; 217 u32 vlan_mask; 218 u32 reserved; 219 u32 anag_efil; 220 u32 an_events; 221 u32 storm_limit_burst; 222 u32 storm_limit_cfg[4]; 223 u32 isolated_prts; 224 u32 community_ports; 225 u32 auto_age; 226 u32 mac_options; 227 u32 learn_disc; 228 u32 agen_ctrl; 229 u32 mirror_ports; 230 u32 emirror_ports; 231 u32 flooding; 232 u32 flooding_ipmc; 233 u32 sflow_cfg[11]; 234 u32 port_mode[12]; 235 }; 236 237 struct vsc9953_ana_pgid { 238 u32 port_grp_id[91]; 239 }; 240 241 struct vsc9953_ana_pfc { 242 u32 pfc_cfg; 243 u32 reserved1[15]; 244 }; 245 246 struct vsc9953_ana_pol_misc { 247 u32 pol_flowc[10]; 248 u32 reserved1[17]; 249 u32 pol_hyst; 250 }; 251 252 struct vsc9953_ana_common { 253 u32 aggr_cfg; 254 u32 cpuq_cfg; 255 u32 cpuq_8021_cfg; 256 u32 dscp_cfg; 257 u32 dscp_rewr_cfg; 258 u32 vcap_rng_type_cfg; 259 u32 vcap_rng_val_cfg; 260 u32 discard_cfg; 261 u32 fid_cfg; 262 }; 263 264 struct vsc9953_analyzer { 265 struct vsc9953_ana_port port[11]; 266 u32 reserved1[9536]; 267 struct vsc9953_ana_pol pol[164]; 268 struct vsc9953_ana_ana_tables ana_tables; 269 u32 reserved2[14]; 270 struct vsc9953_ana_ana ana; 271 u32 reserved3[22]; 272 struct vsc9953_ana_pgid port_id_tbl; 273 u32 reserved4[549]; 274 struct vsc9953_ana_pfc pfc[10]; 275 struct vsc9953_ana_pol_misc pol_misc; 276 u32 reserved5[196]; 277 struct vsc9953_ana_common common; 278 }; 279 /* END VSC9953 ANA structure t*/ 280 281 /* VSC9953 DEV_GMII structure */ 282 283 struct vsc9953_dev_gmii_port_mode { 284 u32 clock_cfg; 285 u32 port_misc; 286 u32 reserved1; 287 u32 eee_cfg; 288 }; 289 290 struct vsc9953_dev_gmii_mac_cfg_status { 291 u32 mac_ena_cfg; 292 u32 mac_mode_cfg; 293 u32 mac_maxlen_cfg; 294 u32 mac_tags_cfg; 295 u32 mac_adv_chk_cfg; 296 u32 mac_ifg_cfg; 297 u32 mac_hdx_cfg; 298 u32 mac_fc_mac_low_cfg; 299 u32 mac_fc_mac_high_cfg; 300 u32 mac_sticky; 301 }; 302 303 struct vsc9953_dev_gmii { 304 struct vsc9953_dev_gmii_port_mode port_mode; 305 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; 306 }; 307 308 /* END VSC9953 DEV_GMII structure */ 309 310 /* VSC9953 QSYS structure */ 311 312 struct vsc9953_qsys_hsch { 313 u32 cir_cfg; 314 u32 reserved1; 315 u32 se_cfg; 316 u32 se_dwrr_cfg[8]; 317 u32 cir_state; 318 u32 reserved2[20]; 319 }; 320 321 struct vsc9953_qsys_sys { 322 u32 port_mode[12]; 323 u32 switch_port_mode[11]; 324 u32 stat_cnt_cfg; 325 u32 eee_cfg[10]; 326 u32 eee_thrs; 327 u32 igr_no_sharing; 328 u32 egr_no_sharing; 329 u32 sw_status[11]; 330 u32 ext_cpu_cfg; 331 u32 cpu_group_map; 332 u32 reserved1[23]; 333 }; 334 335 struct vsc9953_qsys_qos_cfg { 336 u32 red_profile[16]; 337 u32 res_qos_mode; 338 }; 339 340 struct vsc9953_qsys_drop_cfg { 341 u32 egr_drop_mode; 342 }; 343 344 struct vsc9953_qsys_mmgt { 345 u32 eq_cntrl; 346 u32 reserved1; 347 }; 348 349 struct vsc9953_qsys_hsch_misc { 350 u32 hsch_misc_cfg; 351 u32 reserved1[546]; 352 }; 353 354 struct vsc9953_qsys_res_ctrl { 355 u32 res_cfg; 356 u32 res_stat; 357 358 }; 359 360 struct vsc9953_qsys_reg { 361 struct vsc9953_qsys_hsch hsch[108]; 362 struct vsc9953_qsys_sys sys; 363 struct vsc9953_qsys_qos_cfg qos_cfg; 364 struct vsc9953_qsys_drop_cfg drop_cfg; 365 struct vsc9953_qsys_mmgt mmgt; 366 struct vsc9953_qsys_hsch_misc hsch_misc; 367 struct vsc9953_qsys_res_ctrl res_ctrl[1024]; 368 }; 369 370 /* END VSC9953 QSYS structure */ 371 372 /* VSC9953 SYS structure */ 373 374 struct vsc9953_rx_cntrs { 375 u32 c_rx_oct; 376 u32 c_rx_uc; 377 u32 c_rx_mc; 378 u32 c_rx_bc; 379 u32 c_rx_short; 380 u32 c_rx_frag; 381 u32 c_rx_jabber; 382 u32 c_rx_crc; 383 u32 c_rx_symbol_err; 384 u32 c_rx_sz_64; 385 u32 c_rx_sz_65_127; 386 u32 c_rx_sz_128_255; 387 u32 c_rx_sz_256_511; 388 u32 c_rx_sz_512_1023; 389 u32 c_rx_sz_1024_1526; 390 u32 c_rx_sz_jumbo; 391 u32 c_rx_pause; 392 u32 c_rx_control; 393 u32 c_rx_long; 394 u32 c_rx_cat_drop; 395 u32 c_rx_red_prio_0; 396 u32 c_rx_red_prio_1; 397 u32 c_rx_red_prio_2; 398 u32 c_rx_red_prio_3; 399 u32 c_rx_red_prio_4; 400 u32 c_rx_red_prio_5; 401 u32 c_rx_red_prio_6; 402 u32 c_rx_red_prio_7; 403 u32 c_rx_yellow_prio_0; 404 u32 c_rx_yellow_prio_1; 405 u32 c_rx_yellow_prio_2; 406 u32 c_rx_yellow_prio_3; 407 u32 c_rx_yellow_prio_4; 408 u32 c_rx_yellow_prio_5; 409 u32 c_rx_yellow_prio_6; 410 u32 c_rx_yellow_prio_7; 411 u32 c_rx_green_prio_0; 412 u32 c_rx_green_prio_1; 413 u32 c_rx_green_prio_2; 414 u32 c_rx_green_prio_3; 415 u32 c_rx_green_prio_4; 416 u32 c_rx_green_prio_5; 417 u32 c_rx_green_prio_6; 418 u32 c_rx_green_prio_7; 419 u32 reserved[20]; 420 }; 421 422 struct vsc9953_tx_cntrs { 423 u32 c_tx_oct; 424 u32 c_tx_uc; 425 u32 c_tx_mc; 426 u32 c_tx_bc; 427 u32 c_tx_col; 428 u32 c_tx_drop; 429 u32 c_tx_pause; 430 u32 c_tx_sz_64; 431 u32 c_tx_sz_65_127; 432 u32 c_tx_sz_128_255; 433 u32 c_tx_sz_256_511; 434 u32 c_tx_sz_512_1023; 435 u32 c_tx_sz_1024_1526; 436 u32 c_tx_sz_jumbo; 437 u32 c_tx_yellow_prio_0; 438 u32 c_tx_yellow_prio_1; 439 u32 c_tx_yellow_prio_2; 440 u32 c_tx_yellow_prio_3; 441 u32 c_tx_yellow_prio_4; 442 u32 c_tx_yellow_prio_5; 443 u32 c_tx_yellow_prio_6; 444 u32 c_tx_yellow_prio_7; 445 u32 c_tx_green_prio_0; 446 u32 c_tx_green_prio_1; 447 u32 c_tx_green_prio_2; 448 u32 c_tx_green_prio_3; 449 u32 c_tx_green_prio_4; 450 u32 c_tx_green_prio_5; 451 u32 c_tx_green_prio_6; 452 u32 c_tx_green_prio_7; 453 u32 c_tx_aged; 454 u32 reserved[33]; 455 }; 456 457 struct vsc9953_drop_cntrs { 458 u32 c_dr_local; 459 u32 c_dr_tail; 460 u32 c_dr_yellow_prio_0; 461 u32 c_dr_yellow_prio_1; 462 u32 c_dr_yellow_prio_2; 463 u32 c_dr_yellow_prio_3; 464 u32 c_dr_yellow_prio_4; 465 u32 c_dr_yellow_prio_5; 466 u32 c_dr_yellow_prio_6; 467 u32 c_dr_yellow_prio_7; 468 u32 c_dr_green_prio_0; 469 u32 c_dr_green_prio_1; 470 u32 c_dr_green_prio_2; 471 u32 c_dr_green_prio_3; 472 u32 c_dr_green_prio_4; 473 u32 c_dr_green_prio_5; 474 u32 c_dr_green_prio_6; 475 u32 c_dr_green_prio_7; 476 u32 reserved[46]; 477 }; 478 479 struct vsc9953_sys_stat { 480 struct vsc9953_rx_cntrs rx_cntrs; 481 struct vsc9953_tx_cntrs tx_cntrs; 482 struct vsc9953_drop_cntrs drop_cntrs; 483 u32 reserved1[6]; 484 }; 485 486 struct vsc9953_sys_sys { 487 u32 reset_cfg; 488 u32 reserved1; 489 u32 vlan_etype_cfg; 490 u32 port_mode[12]; 491 u32 front_port_mode[10]; 492 u32 frame_aging; 493 u32 stat_cfg; 494 u32 reserved2[50]; 495 }; 496 497 struct vsc9953_sys_pause_cfg { 498 u32 pause_cfg[11]; 499 u32 pause_tot_cfg; 500 u32 tail_drop_level[11]; 501 u32 tot_tail_drop_lvl; 502 u32 mac_fc_cfg[10]; 503 }; 504 505 struct vsc9953_sys_mmgt { 506 u16 free_cnt; 507 }; 508 509 struct vsc9953_system_reg { 510 struct vsc9953_sys_stat stat; 511 struct vsc9953_sys_sys sys; 512 struct vsc9953_sys_pause_cfg pause_cfg; 513 struct vsc9953_sys_mmgt mmgt; 514 }; 515 516 /* END VSC9953 SYS structure */ 517 518 /* VSC9953 REW structure */ 519 520 struct vsc9953_rew_port { 521 u32 port_vlan_cfg; 522 u32 port_tag_cfg; 523 u32 port_port_cfg; 524 u32 port_dscp_cfg; 525 u32 port_pcp_dei_qos_map_cfg[16]; 526 u32 reserved[12]; 527 }; 528 529 struct vsc9953_rew_common { 530 u32 reserve[4]; 531 u32 dscp_remap_dp1_cfg[64]; 532 u32 dscp_remap_cfg[64]; 533 }; 534 535 struct vsc9953_rew_reg { 536 struct vsc9953_rew_port port[12]; 537 struct vsc9953_rew_common common; 538 }; 539 540 /* END VSC9953 REW structure */ 541 542 /* VSC9953 DEVCPU_GCB structure */ 543 544 struct vsc9953_chip_regs { 545 u32 chipd_id; 546 u32 gpr; 547 u32 soft_rst; 548 }; 549 550 struct vsc9953_gpio { 551 u32 gpio_out_set[10]; 552 u32 gpio_out_clr[10]; 553 u32 gpio_out[10]; 554 u32 gpio_in[10]; 555 }; 556 557 struct vsc9953_mii_mng { 558 u32 miimstatus; 559 u32 reserved1; 560 u32 miimcmd; 561 u32 miimdata; 562 u32 miimcfg; 563 u32 miimscan_0; 564 u32 miimscan_1; 565 u32 miiscan_lst_rslts; 566 u32 miiscan_lst_rslts_valid; 567 }; 568 569 struct vsc9953_mii_read_scan { 570 u32 mii_scan_results_sticky[2]; 571 }; 572 573 struct vsc9953_devcpu_gcb { 574 struct vsc9953_chip_regs chip_regs; 575 struct vsc9953_gpio gpio; 576 struct vsc9953_mii_mng mii_mng[2]; 577 struct vsc9953_mii_read_scan mii_read_scan; 578 }; 579 580 /* END VSC9953 DEVCPU_GCB structure */ 581 582 /* VSC9953 IS* structure */ 583 584 struct vsc9953_vcap_core_cfg { 585 u32 vcap_update_ctrl; 586 u32 vcap_mv_cfg; 587 }; 588 589 struct vsc9953_vcap { 590 struct vsc9953_vcap_core_cfg vcap_core_cfg; 591 }; 592 593 /* END VSC9953 IS* structure */ 594 595 #define VSC9953_PORT_INFO_INITIALIZER(idx) \ 596 { \ 597 .enabled = 0, \ 598 .phyaddr = 0, \ 599 .index = idx, \ 600 .phy_regs = NULL, \ 601 .enet_if = PHY_INTERFACE_MODE_NONE, \ 602 .bus = NULL, \ 603 .phydev = NULL, \ 604 } 605 606 /* Structure to describe a VSC9953 port */ 607 struct vsc9953_port_info { 608 u8 enabled; 609 u8 phyaddr; 610 int index; 611 void *phy_regs; 612 phy_interface_t enet_if; 613 struct mii_dev *bus; 614 struct phy_device *phydev; 615 }; 616 617 /* Structure to describe a VSC9953 switch */ 618 struct vsc9953_info { 619 struct vsc9953_port_info port[VSC9953_MAX_PORTS]; 620 }; 621 622 void vsc9953_init(bd_t *bis); 623 624 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); 625 void vsc9953_port_info_set_phy_address(int port_no, int address); 626 void vsc9953_port_enable(int port_no); 627 void vsc9953_port_disable(int port_no); 628 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); 629 630 #endif /* _VSC9953_H_ */ 631