1 /* 2 * vsc9953.h 3 * 4 * Driver for the Vitesse VSC9953 L2 Switch 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2013 Freescale Semiconductor, Inc. 11 * 12 */ 13 14 #ifndef _VSC9953_H_ 15 #define _VSC9953_H_ 16 17 #include <config.h> 18 #include <miiphy.h> 19 #include <asm/types.h> 20 21 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) 22 23 #define VSC9953_SYS_OFFSET 0x010000 24 #define VSC9953_REW_OFFSET 0x030000 25 #define VSC9953_DEV_GMII_OFFSET 0x100000 26 #define VSC9953_QSYS_OFFSET 0x200000 27 #define VSC9953_ANA_OFFSET 0x280000 28 #define VSC9953_DEVCPU_GCB 0x070000 29 #define VSC9953_ES0 0x040000 30 #define VSC9953_IS1 0x050000 31 #define VSC9953_IS2 0x060000 32 33 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 34 #define VSC9953_PHY_REGS_OFFST 0x0000AC 35 36 /* Macros for vsc9953_chip_regs.soft_rst register */ 37 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 38 39 /* Macros for vsc9953_sys_sys.reset_cfg register */ 40 #define VSC9953_CORE_ENABLE 0x80 41 #define VSC9953_MEM_ENABLE 0x40 42 #define VSC9953_MEM_INIT 0x20 43 44 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ 45 #define VSC9953_MAC_ENA_CFG 0x00000011 46 47 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ 48 #define VSC9953_MAC_MODE_CFG 0x00000011 49 50 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ 51 #define VSC9953_MAC_IFG_CFG 0x00000515 52 53 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ 54 #define VSC9953_MAC_HDX_CFG 0x00001043 55 56 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ 57 #define VSC9953_MAC_MAX_LEN 0x000005ee 58 59 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ 60 #define VSC9953_CLOCK_CFG 0x00000001 61 #define VSC9953_CLOCK_CFG_1000M 0x00000001 62 63 /* Macros for vsc9953_sys_sys.front_port_mode register */ 64 #define VSC9953_FRONT_PORT_MODE 0x00000000 65 66 /* Macros for vsc9953_ana_pfc.pfc_cfg register */ 67 #define VSC9953_PFC_FC 0x00000001 68 #define VSC9953_PFC_FC_QSGMII 0x00000000 69 70 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ 71 #define VSC9953_MAC_FC_CFG 0x04700000 72 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 73 74 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ 75 #define VSC9953_PAUSE_CFG 0x001ffffe 76 77 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ 78 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff 79 80 /* Macros for vsc9953_sys_sys.stat_cfg register */ 81 #define VSC9953_STAT_CLEAR_RX 0x00000400 82 #define VSC9953_STAT_CLEAR_TX 0x00000800 83 #define VSC9953_STAT_CLEAR_DR 0x00001000 84 85 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ 86 #define VSC9953_VCAP_MV_CFG 0x0000ffff 87 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 88 89 /* Macros for register vsc9953_ana_ana_tables.mac_access register */ 90 #define VSC9953_MAC_CMD_IDLE 0x00000000 91 #define VSC9953_MAC_CMD_LEARN 0x00000001 92 #define VSC9953_MAC_CMD_FORGET 0x00000002 93 #define VSC9953_MAC_CMD_AGE 0x00000003 94 #define VSC9953_MAC_CMD_NEXT 0x00000004 95 #define VSC9953_MAC_CMD_READ 0x00000006 96 #define VSC9953_MAC_CMD_WRITE 0x00000007 97 #define VSC9953_MAC_CMD_MASK 0x00000007 98 #define VSC9953_MAC_CMD_VALID 0x00000800 99 #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000 100 #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200 101 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400 102 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600 103 #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600 104 #define VSC9953_MAC_DESTIDX_MASK 0x000001f8 105 #define VSC9953_MAC_VID_MASK 0x1fff0000 106 #define VSC9953_MAC_MACH_MASK 0x0000ffff 107 108 /* Macros for vsc9953_ana_port.vlan_cfg register */ 109 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 110 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 111 #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000 112 #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000 113 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff 114 115 /* Macros for vsc9953_rew_port.port_vlan_cfg register */ 116 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff 117 118 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ 119 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff 120 121 /* Macros for vsc9953_ana_ana_tables.vlan_access register */ 122 #define VSC9953_VLAN_PORT_MASK 0x00001ffc 123 #define VSC9953_VLAN_CMD_MASK 0x00000003 124 #define VSC9953_VLAN_CMD_IDLE 0x00000000 125 #define VSC9953_VLAN_CMD_READ 0x00000001 126 #define VSC9953_VLAN_CMD_WRITE 0x00000002 127 #define VSC9953_VLAN_CMD_INIT 0x00000003 128 129 /* Macros for vsc9953_ana_port.port_cfg register */ 130 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080 131 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 132 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 133 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 134 135 /* Macros for vsc9953_qsys_sys.switch_port_mode register */ 136 #define VSC9953_PORT_ENA 0x00002000 137 138 /* Macros for vsc9953_ana_ana.agen_ctrl register */ 139 #define VSC9953_FID_MASK_ALL 0x00fff000 140 141 /* Macros for vsc9953_ana_ana.adv_learn register */ 142 #define VSC9953_VLAN_CHK 0x00000400 143 144 /* Macros for vsc9953_rew_port.port_tag_cfg register */ 145 #define VSC9953_TAG_CFG_MASK 0x00000180 146 #define VSC9953_TAG_CFG_NONE 0x00000000 147 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 148 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 149 #define VSC9953_TAG_CFG_ALL 0x00000180 150 #define VSC9953_TAG_VID_PVID 0x00000010 151 152 /* Macros for vsc9953_ana_ana.anag_efil register */ 153 #define VSC9953_AGE_PORT_EN 0x00080000 154 #define VSC9953_AGE_PORT_MASK 0x0007c000 155 #define VSC9953_AGE_VID_EN 0x00002000 156 #define VSC9953_AGE_VID_MASK 0x00001fff 157 158 /* Macros for vsc9953_ana_ana_tables.mach_data register */ 159 #define VSC9953_MACHDATA_VID_MASK 0x1fff0000 160 161 #define VSC9953_MAX_PORTS 10 162 #define VSC9953_PORT_CHECK(port) \ 163 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) 164 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \ 165 ( \ 166 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ 167 ) ? 0 : 1 \ 168 ) 169 #define VSC9953_MAX_VLAN 4096 170 #define VSC9953_VLAN_CHECK(vid) \ 171 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) 172 173 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" 174 175 #define MIIMIND_OPR_PEND 0x00000004 176 177 struct vsc9953_mdio_info { 178 struct vsc9953_mii_mng *regs; 179 char *name; 180 }; 181 182 /* VSC9953 ANA structure */ 183 184 struct vsc9953_ana_port { 185 u32 vlan_cfg; 186 u32 drop_cfg; 187 u32 qos_cfg; 188 u32 vcap_cfg; 189 u32 vcap_s1_key_cfg[3]; 190 u32 vcap_s2_cfg; 191 u32 qos_pcp_dei_map_cfg[16]; 192 u32 cpu_fwd_cfg; 193 u32 cpu_fwd_bpdu_cfg; 194 u32 cpu_fwd_garp_cfg; 195 u32 cpu_fwd_ccm_cfg; 196 u32 port_cfg; 197 u32 pol_cfg; 198 u32 reserved[34]; 199 }; 200 201 struct vsc9953_ana_pol { 202 u32 pol_pir_cfg; 203 u32 pol_cir_cfg; 204 u32 pol_mode_cfg; 205 u32 pol_pir_state; 206 u32 pol_cir_state; 207 u32 reserved1[3]; 208 }; 209 210 struct vsc9953_ana_ana_tables { 211 u32 entry_lim[11]; 212 u32 an_moved; 213 u32 mach_data; 214 u32 macl_data; 215 u32 mac_access; 216 u32 mact_indx; 217 u32 vlan_access; 218 u32 vlan_tidx; 219 }; 220 221 struct vsc9953_ana_ana { 222 u32 adv_learn; 223 u32 vlan_mask; 224 u32 reserved; 225 u32 anag_efil; 226 u32 an_events; 227 u32 storm_limit_burst; 228 u32 storm_limit_cfg[4]; 229 u32 isolated_prts; 230 u32 community_ports; 231 u32 auto_age; 232 u32 mac_options; 233 u32 learn_disc; 234 u32 agen_ctrl; 235 u32 mirror_ports; 236 u32 emirror_ports; 237 u32 flooding; 238 u32 flooding_ipmc; 239 u32 sflow_cfg[11]; 240 u32 port_mode[12]; 241 }; 242 243 struct vsc9953_ana_pgid { 244 u32 port_grp_id[91]; 245 }; 246 247 struct vsc9953_ana_pfc { 248 u32 pfc_cfg; 249 u32 reserved1[15]; 250 }; 251 252 struct vsc9953_ana_pol_misc { 253 u32 pol_flowc[10]; 254 u32 reserved1[17]; 255 u32 pol_hyst; 256 }; 257 258 struct vsc9953_ana_common { 259 u32 aggr_cfg; 260 u32 cpuq_cfg; 261 u32 cpuq_8021_cfg; 262 u32 dscp_cfg; 263 u32 dscp_rewr_cfg; 264 u32 vcap_rng_type_cfg; 265 u32 vcap_rng_val_cfg; 266 u32 discard_cfg; 267 u32 fid_cfg; 268 }; 269 270 struct vsc9953_analyzer { 271 struct vsc9953_ana_port port[11]; 272 u32 reserved1[9536]; 273 struct vsc9953_ana_pol pol[164]; 274 struct vsc9953_ana_ana_tables ana_tables; 275 u32 reserved2[14]; 276 struct vsc9953_ana_ana ana; 277 u32 reserved3[22]; 278 struct vsc9953_ana_pgid port_id_tbl; 279 u32 reserved4[549]; 280 struct vsc9953_ana_pfc pfc[10]; 281 struct vsc9953_ana_pol_misc pol_misc; 282 u32 reserved5[196]; 283 struct vsc9953_ana_common common; 284 }; 285 /* END VSC9953 ANA structure t*/ 286 287 /* VSC9953 DEV_GMII structure */ 288 289 struct vsc9953_dev_gmii_port_mode { 290 u32 clock_cfg; 291 u32 port_misc; 292 u32 reserved1; 293 u32 eee_cfg; 294 }; 295 296 struct vsc9953_dev_gmii_mac_cfg_status { 297 u32 mac_ena_cfg; 298 u32 mac_mode_cfg; 299 u32 mac_maxlen_cfg; 300 u32 mac_tags_cfg; 301 u32 mac_adv_chk_cfg; 302 u32 mac_ifg_cfg; 303 u32 mac_hdx_cfg; 304 u32 mac_fc_mac_low_cfg; 305 u32 mac_fc_mac_high_cfg; 306 u32 mac_sticky; 307 }; 308 309 struct vsc9953_dev_gmii { 310 struct vsc9953_dev_gmii_port_mode port_mode; 311 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; 312 }; 313 314 /* END VSC9953 DEV_GMII structure */ 315 316 /* VSC9953 QSYS structure */ 317 318 struct vsc9953_qsys_hsch { 319 u32 cir_cfg; 320 u32 reserved1; 321 u32 se_cfg; 322 u32 se_dwrr_cfg[8]; 323 u32 cir_state; 324 u32 reserved2[20]; 325 }; 326 327 struct vsc9953_qsys_sys { 328 u32 port_mode[12]; 329 u32 switch_port_mode[11]; 330 u32 stat_cnt_cfg; 331 u32 eee_cfg[10]; 332 u32 eee_thrs; 333 u32 igr_no_sharing; 334 u32 egr_no_sharing; 335 u32 sw_status[11]; 336 u32 ext_cpu_cfg; 337 u32 cpu_group_map; 338 u32 reserved1[23]; 339 }; 340 341 struct vsc9953_qsys_qos_cfg { 342 u32 red_profile[16]; 343 u32 res_qos_mode; 344 }; 345 346 struct vsc9953_qsys_drop_cfg { 347 u32 egr_drop_mode; 348 }; 349 350 struct vsc9953_qsys_mmgt { 351 u32 eq_cntrl; 352 u32 reserved1; 353 }; 354 355 struct vsc9953_qsys_hsch_misc { 356 u32 hsch_misc_cfg; 357 u32 reserved1[546]; 358 }; 359 360 struct vsc9953_qsys_res_ctrl { 361 u32 res_cfg; 362 u32 res_stat; 363 364 }; 365 366 struct vsc9953_qsys_reg { 367 struct vsc9953_qsys_hsch hsch[108]; 368 struct vsc9953_qsys_sys sys; 369 struct vsc9953_qsys_qos_cfg qos_cfg; 370 struct vsc9953_qsys_drop_cfg drop_cfg; 371 struct vsc9953_qsys_mmgt mmgt; 372 struct vsc9953_qsys_hsch_misc hsch_misc; 373 struct vsc9953_qsys_res_ctrl res_ctrl[1024]; 374 }; 375 376 /* END VSC9953 QSYS structure */ 377 378 /* VSC9953 SYS structure */ 379 380 struct vsc9953_rx_cntrs { 381 u32 c_rx_oct; 382 u32 c_rx_uc; 383 u32 c_rx_mc; 384 u32 c_rx_bc; 385 u32 c_rx_short; 386 u32 c_rx_frag; 387 u32 c_rx_jabber; 388 u32 c_rx_crc; 389 u32 c_rx_symbol_err; 390 u32 c_rx_sz_64; 391 u32 c_rx_sz_65_127; 392 u32 c_rx_sz_128_255; 393 u32 c_rx_sz_256_511; 394 u32 c_rx_sz_512_1023; 395 u32 c_rx_sz_1024_1526; 396 u32 c_rx_sz_jumbo; 397 u32 c_rx_pause; 398 u32 c_rx_control; 399 u32 c_rx_long; 400 u32 c_rx_cat_drop; 401 u32 c_rx_red_prio_0; 402 u32 c_rx_red_prio_1; 403 u32 c_rx_red_prio_2; 404 u32 c_rx_red_prio_3; 405 u32 c_rx_red_prio_4; 406 u32 c_rx_red_prio_5; 407 u32 c_rx_red_prio_6; 408 u32 c_rx_red_prio_7; 409 u32 c_rx_yellow_prio_0; 410 u32 c_rx_yellow_prio_1; 411 u32 c_rx_yellow_prio_2; 412 u32 c_rx_yellow_prio_3; 413 u32 c_rx_yellow_prio_4; 414 u32 c_rx_yellow_prio_5; 415 u32 c_rx_yellow_prio_6; 416 u32 c_rx_yellow_prio_7; 417 u32 c_rx_green_prio_0; 418 u32 c_rx_green_prio_1; 419 u32 c_rx_green_prio_2; 420 u32 c_rx_green_prio_3; 421 u32 c_rx_green_prio_4; 422 u32 c_rx_green_prio_5; 423 u32 c_rx_green_prio_6; 424 u32 c_rx_green_prio_7; 425 u32 reserved[20]; 426 }; 427 428 struct vsc9953_tx_cntrs { 429 u32 c_tx_oct; 430 u32 c_tx_uc; 431 u32 c_tx_mc; 432 u32 c_tx_bc; 433 u32 c_tx_col; 434 u32 c_tx_drop; 435 u32 c_tx_pause; 436 u32 c_tx_sz_64; 437 u32 c_tx_sz_65_127; 438 u32 c_tx_sz_128_255; 439 u32 c_tx_sz_256_511; 440 u32 c_tx_sz_512_1023; 441 u32 c_tx_sz_1024_1526; 442 u32 c_tx_sz_jumbo; 443 u32 c_tx_yellow_prio_0; 444 u32 c_tx_yellow_prio_1; 445 u32 c_tx_yellow_prio_2; 446 u32 c_tx_yellow_prio_3; 447 u32 c_tx_yellow_prio_4; 448 u32 c_tx_yellow_prio_5; 449 u32 c_tx_yellow_prio_6; 450 u32 c_tx_yellow_prio_7; 451 u32 c_tx_green_prio_0; 452 u32 c_tx_green_prio_1; 453 u32 c_tx_green_prio_2; 454 u32 c_tx_green_prio_3; 455 u32 c_tx_green_prio_4; 456 u32 c_tx_green_prio_5; 457 u32 c_tx_green_prio_6; 458 u32 c_tx_green_prio_7; 459 u32 c_tx_aged; 460 u32 reserved[33]; 461 }; 462 463 struct vsc9953_drop_cntrs { 464 u32 c_dr_local; 465 u32 c_dr_tail; 466 u32 c_dr_yellow_prio_0; 467 u32 c_dr_yellow_prio_1; 468 u32 c_dr_yellow_prio_2; 469 u32 c_dr_yellow_prio_3; 470 u32 c_dr_yellow_prio_4; 471 u32 c_dr_yellow_prio_5; 472 u32 c_dr_yellow_prio_6; 473 u32 c_dr_yellow_prio_7; 474 u32 c_dr_green_prio_0; 475 u32 c_dr_green_prio_1; 476 u32 c_dr_green_prio_2; 477 u32 c_dr_green_prio_3; 478 u32 c_dr_green_prio_4; 479 u32 c_dr_green_prio_5; 480 u32 c_dr_green_prio_6; 481 u32 c_dr_green_prio_7; 482 u32 reserved[46]; 483 }; 484 485 struct vsc9953_sys_stat { 486 struct vsc9953_rx_cntrs rx_cntrs; 487 struct vsc9953_tx_cntrs tx_cntrs; 488 struct vsc9953_drop_cntrs drop_cntrs; 489 u32 reserved1[6]; 490 }; 491 492 struct vsc9953_sys_sys { 493 u32 reset_cfg; 494 u32 reserved1; 495 u32 vlan_etype_cfg; 496 u32 port_mode[12]; 497 u32 front_port_mode[10]; 498 u32 frame_aging; 499 u32 stat_cfg; 500 u32 reserved2[50]; 501 }; 502 503 struct vsc9953_sys_pause_cfg { 504 u32 pause_cfg[11]; 505 u32 pause_tot_cfg; 506 u32 tail_drop_level[11]; 507 u32 tot_tail_drop_lvl; 508 u32 mac_fc_cfg[10]; 509 }; 510 511 struct vsc9953_sys_mmgt { 512 u16 free_cnt; 513 }; 514 515 struct vsc9953_system_reg { 516 struct vsc9953_sys_stat stat; 517 struct vsc9953_sys_sys sys; 518 struct vsc9953_sys_pause_cfg pause_cfg; 519 struct vsc9953_sys_mmgt mmgt; 520 }; 521 522 /* END VSC9953 SYS structure */ 523 524 /* VSC9953 REW structure */ 525 526 struct vsc9953_rew_port { 527 u32 port_vlan_cfg; 528 u32 port_tag_cfg; 529 u32 port_port_cfg; 530 u32 port_dscp_cfg; 531 u32 port_pcp_dei_qos_map_cfg[16]; 532 u32 reserved[12]; 533 }; 534 535 struct vsc9953_rew_common { 536 u32 reserve[4]; 537 u32 dscp_remap_dp1_cfg[64]; 538 u32 dscp_remap_cfg[64]; 539 }; 540 541 struct vsc9953_rew_reg { 542 struct vsc9953_rew_port port[12]; 543 struct vsc9953_rew_common common; 544 }; 545 546 /* END VSC9953 REW structure */ 547 548 /* VSC9953 DEVCPU_GCB structure */ 549 550 struct vsc9953_chip_regs { 551 u32 chipd_id; 552 u32 gpr; 553 u32 soft_rst; 554 }; 555 556 struct vsc9953_gpio { 557 u32 gpio_out_set[10]; 558 u32 gpio_out_clr[10]; 559 u32 gpio_out[10]; 560 u32 gpio_in[10]; 561 }; 562 563 struct vsc9953_mii_mng { 564 u32 miimstatus; 565 u32 reserved1; 566 u32 miimcmd; 567 u32 miimdata; 568 u32 miimcfg; 569 u32 miimscan_0; 570 u32 miimscan_1; 571 u32 miiscan_lst_rslts; 572 u32 miiscan_lst_rslts_valid; 573 }; 574 575 struct vsc9953_mii_read_scan { 576 u32 mii_scan_results_sticky[2]; 577 }; 578 579 struct vsc9953_devcpu_gcb { 580 struct vsc9953_chip_regs chip_regs; 581 struct vsc9953_gpio gpio; 582 struct vsc9953_mii_mng mii_mng[2]; 583 struct vsc9953_mii_read_scan mii_read_scan; 584 }; 585 586 /* END VSC9953 DEVCPU_GCB structure */ 587 588 /* VSC9953 IS* structure */ 589 590 struct vsc9953_vcap_core_cfg { 591 u32 vcap_update_ctrl; 592 u32 vcap_mv_cfg; 593 }; 594 595 struct vsc9953_vcap { 596 struct vsc9953_vcap_core_cfg vcap_core_cfg; 597 }; 598 599 /* END VSC9953 IS* structure */ 600 601 #define VSC9953_PORT_INFO_INITIALIZER(idx) \ 602 { \ 603 .enabled = 0, \ 604 .phyaddr = 0, \ 605 .index = idx, \ 606 .phy_regs = NULL, \ 607 .enet_if = PHY_INTERFACE_MODE_NONE, \ 608 .bus = NULL, \ 609 .phydev = NULL, \ 610 } 611 612 /* Structure to describe a VSC9953 port */ 613 struct vsc9953_port_info { 614 u8 enabled; 615 u8 phyaddr; 616 int index; 617 void *phy_regs; 618 phy_interface_t enet_if; 619 struct mii_dev *bus; 620 struct phy_device *phydev; 621 }; 622 623 /* Structure to describe a VSC9953 switch */ 624 struct vsc9953_info { 625 struct vsc9953_port_info port[VSC9953_MAX_PORTS]; 626 }; 627 628 void vsc9953_init(bd_t *bis); 629 630 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); 631 void vsc9953_port_info_set_phy_address(int port_no, int address); 632 void vsc9953_port_enable(int port_no); 633 void vsc9953_port_disable(int port_no); 634 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); 635 636 #endif /* _VSC9953_H_ */ 637