1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Andy Fleming <afleming@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h 8 */ 9 10 #ifndef _PHY_H 11 #define _PHY_H 12 13 #include <linux/list.h> 14 #include <linux/mii.h> 15 #include <linux/ethtool.h> 16 #include <linux/mdio.h> 17 18 #define PHY_MAX_ADDR 32 19 20 #define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ 21 22 #define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ 23 SUPPORTED_TP | \ 24 SUPPORTED_MII) 25 26 #define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ 27 SUPPORTED_10baseT_Full) 28 29 #define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ 30 SUPPORTED_100baseT_Full) 31 32 #define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ 33 SUPPORTED_1000baseT_Full) 34 35 #define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \ 36 PHY_100BT_FEATURES | \ 37 PHY_DEFAULT_FEATURES) 38 39 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ 40 PHY_1000BT_FEATURES) 41 42 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ 43 SUPPORTED_10000baseT_Full) 44 45 #ifndef PHY_ANEG_TIMEOUT 46 #define PHY_ANEG_TIMEOUT 4000 47 #endif 48 49 50 typedef enum { 51 PHY_INTERFACE_MODE_MII, 52 PHY_INTERFACE_MODE_GMII, 53 PHY_INTERFACE_MODE_SGMII, 54 PHY_INTERFACE_MODE_SGMII_2500, 55 PHY_INTERFACE_MODE_QSGMII, 56 PHY_INTERFACE_MODE_TBI, 57 PHY_INTERFACE_MODE_RMII, 58 PHY_INTERFACE_MODE_RGMII, 59 PHY_INTERFACE_MODE_RGMII_ID, 60 PHY_INTERFACE_MODE_RGMII_RXID, 61 PHY_INTERFACE_MODE_RGMII_TXID, 62 PHY_INTERFACE_MODE_RTBI, 63 PHY_INTERFACE_MODE_XGMII, 64 PHY_INTERFACE_MODE_XAUI, 65 PHY_INTERFACE_MODE_RXAUI, 66 PHY_INTERFACE_MODE_SFI, 67 PHY_INTERFACE_MODE_NONE, /* Must be last */ 68 69 PHY_INTERFACE_MODE_COUNT, 70 } phy_interface_t; 71 72 static const char *phy_interface_strings[] = { 73 [PHY_INTERFACE_MODE_MII] = "mii", 74 [PHY_INTERFACE_MODE_GMII] = "gmii", 75 [PHY_INTERFACE_MODE_SGMII] = "sgmii", 76 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", 77 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", 78 [PHY_INTERFACE_MODE_TBI] = "tbi", 79 [PHY_INTERFACE_MODE_RMII] = "rmii", 80 [PHY_INTERFACE_MODE_RGMII] = "rgmii", 81 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", 82 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", 83 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", 84 [PHY_INTERFACE_MODE_RTBI] = "rtbi", 85 [PHY_INTERFACE_MODE_XGMII] = "xgmii", 86 [PHY_INTERFACE_MODE_XAUI] = "xaui", 87 [PHY_INTERFACE_MODE_RXAUI] = "rxaui", 88 [PHY_INTERFACE_MODE_SFI] = "sfi", 89 [PHY_INTERFACE_MODE_NONE] = "", 90 }; 91 92 static inline const char *phy_string_for_interface(phy_interface_t i) 93 { 94 /* Default to unknown */ 95 if (i > PHY_INTERFACE_MODE_NONE) 96 i = PHY_INTERFACE_MODE_NONE; 97 98 return phy_interface_strings[i]; 99 } 100 101 102 struct phy_device; 103 104 #define MDIO_NAME_LEN 32 105 106 struct mii_dev { 107 struct list_head link; 108 char name[MDIO_NAME_LEN]; 109 void *priv; 110 int (*read)(struct mii_dev *bus, int addr, int devad, int reg); 111 int (*write)(struct mii_dev *bus, int addr, int devad, int reg, 112 u16 val); 113 int (*reset)(struct mii_dev *bus); 114 struct phy_device *phymap[PHY_MAX_ADDR]; 115 u32 phy_mask; 116 }; 117 118 /* struct phy_driver: a structure which defines PHY behavior 119 * 120 * uid will contain a number which represents the PHY. During 121 * startup, the driver will poll the PHY to find out what its 122 * UID--as defined by registers 2 and 3--is. The 32-bit result 123 * gotten from the PHY will be masked to 124 * discard any bits which may change based on revision numbers 125 * unimportant to functionality 126 * 127 */ 128 struct phy_driver { 129 char *name; 130 unsigned int uid; 131 unsigned int mask; 132 unsigned int mmds; 133 134 u32 features; 135 136 /* Called to do any driver startup necessities */ 137 /* Will be called during phy_connect */ 138 int (*probe)(struct phy_device *phydev); 139 140 /* Called to configure the PHY, and modify the controller 141 * based on the results. Should be called after phy_connect */ 142 int (*config)(struct phy_device *phydev); 143 144 /* Called when starting up the controller */ 145 int (*startup)(struct phy_device *phydev); 146 147 /* Called when bringing down the controller */ 148 int (*shutdown)(struct phy_device *phydev); 149 150 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); 151 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, 152 u16 val); 153 struct list_head list; 154 }; 155 156 struct phy_device { 157 /* Information about the PHY type */ 158 /* And management functions */ 159 struct mii_dev *bus; 160 struct phy_driver *drv; 161 void *priv; 162 163 #ifdef CONFIG_DM_ETH 164 struct udevice *dev; 165 #else 166 struct eth_device *dev; 167 #endif 168 169 /* forced speed & duplex (no autoneg) 170 * partner speed & duplex & pause (autoneg) 171 */ 172 int speed; 173 int duplex; 174 175 /* The most recently read link state */ 176 int link; 177 int port; 178 phy_interface_t interface; 179 180 u32 advertising; 181 u32 supported; 182 u32 mmds; 183 184 int autoneg; 185 int addr; 186 int pause; 187 int asym_pause; 188 u32 phy_id; 189 u32 flags; 190 }; 191 192 struct fixed_link { 193 int phy_id; 194 int duplex; 195 int link_speed; 196 int pause; 197 int asym_pause; 198 }; 199 200 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) 201 { 202 struct mii_dev *bus = phydev->bus; 203 204 return bus->read(bus, phydev->addr, devad, regnum); 205 } 206 207 static inline int phy_write(struct phy_device *phydev, int devad, int regnum, 208 u16 val) 209 { 210 struct mii_dev *bus = phydev->bus; 211 212 return bus->write(bus, phydev->addr, devad, regnum, val); 213 } 214 215 #ifdef CONFIG_PHYLIB_10G 216 extern struct phy_driver gen10g_driver; 217 218 /* For now, XGMII is the only 10G interface */ 219 static inline int is_10g_interface(phy_interface_t interface) 220 { 221 return interface == PHY_INTERFACE_MODE_XGMII; 222 } 223 224 #endif 225 226 int phy_init(void); 227 int phy_reset(struct phy_device *phydev); 228 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, 229 phy_interface_t interface); 230 #ifdef CONFIG_DM_ETH 231 void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); 232 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 233 struct udevice *dev, 234 phy_interface_t interface); 235 #else 236 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); 237 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 238 struct eth_device *dev, 239 phy_interface_t interface); 240 #endif 241 int phy_startup(struct phy_device *phydev); 242 int phy_config(struct phy_device *phydev); 243 int phy_shutdown(struct phy_device *phydev); 244 int phy_register(struct phy_driver *drv); 245 int phy_set_supported(struct phy_device *phydev, u32 max_speed); 246 int genphy_config_aneg(struct phy_device *phydev); 247 int genphy_restart_aneg(struct phy_device *phydev); 248 int genphy_update_link(struct phy_device *phydev); 249 int genphy_parse_link(struct phy_device *phydev); 250 int genphy_config(struct phy_device *phydev); 251 int genphy_startup(struct phy_device *phydev); 252 int genphy_shutdown(struct phy_device *phydev); 253 int gen10g_config(struct phy_device *phydev); 254 int gen10g_startup(struct phy_device *phydev); 255 int gen10g_shutdown(struct phy_device *phydev); 256 int gen10g_discover_mmds(struct phy_device *phydev); 257 258 int phy_mv88e61xx_init(void); 259 int phy_aquantia_init(void); 260 int phy_atheros_init(void); 261 int phy_broadcom_init(void); 262 int phy_cortina_init(void); 263 int phy_davicom_init(void); 264 int phy_et1011c_init(void); 265 int phy_lxt_init(void); 266 int phy_marvell_init(void); 267 int phy_micrel_init(void); 268 int phy_natsemi_init(void); 269 int phy_realtek_init(void); 270 int phy_smsc_init(void); 271 int phy_teranetics_init(void); 272 int phy_ti_init(void); 273 int phy_vitesse_init(void); 274 int phy_xilinx_init(void); 275 int phy_mscc_init(void); 276 277 int board_phy_config(struct phy_device *phydev); 278 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); 279 280 /** 281 * phy_get_interface_by_name() - Look up a PHY interface name 282 * 283 * @str: PHY interface name, e.g. "mii" 284 * @return PHY_INTERFACE_MODE_... value, or -1 if not found 285 */ 286 int phy_get_interface_by_name(const char *str); 287 288 /** 289 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 290 * is RGMII (all variants) 291 * @phydev: the phy_device struct 292 */ 293 static inline bool phy_interface_is_rgmii(struct phy_device *phydev) 294 { 295 return phydev->interface >= PHY_INTERFACE_MODE_RGMII && 296 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; 297 } 298 299 /** 300 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface 301 * is SGMII (all variants) 302 * @phydev: the phy_device struct 303 */ 304 static inline bool phy_interface_is_sgmii(struct phy_device *phydev) 305 { 306 return phydev->interface >= PHY_INTERFACE_MODE_SGMII && 307 phydev->interface <= PHY_INTERFACE_MODE_QSGMII; 308 } 309 310 /* PHY UIDs for various PHYs that are referenced in external code */ 311 #define PHY_UID_CS4340 0x13e51002 312 #define PHY_UID_TN2020 0x00a19410 313 314 #endif 315