1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Andy Fleming <afleming@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h 8 */ 9 10 #ifndef _PHY_H 11 #define _PHY_H 12 13 #include <dm.h> 14 #include <linux/list.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/mdio.h> 18 #include <phy_interface.h> 19 20 #define PHY_FIXED_ID 0xa5a55a5a 21 22 #define PHY_MAX_ADDR 32 23 24 #define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ 25 26 #define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ 27 SUPPORTED_TP | \ 28 SUPPORTED_MII) 29 30 #define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ 31 SUPPORTED_10baseT_Full) 32 33 #define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ 34 SUPPORTED_100baseT_Full) 35 36 #define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ 37 SUPPORTED_1000baseT_Full) 38 39 #define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \ 40 PHY_100BT_FEATURES | \ 41 PHY_DEFAULT_FEATURES) 42 43 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ 44 PHY_1000BT_FEATURES) 45 46 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ 47 SUPPORTED_10000baseT_Full) 48 49 #ifndef PHY_ANEG_TIMEOUT 50 #define PHY_ANEG_TIMEOUT 4000 51 #endif 52 53 54 struct phy_device; 55 56 #define MDIO_NAME_LEN 32 57 58 struct mii_dev { 59 struct list_head link; 60 char name[MDIO_NAME_LEN]; 61 void *priv; 62 int (*read)(struct mii_dev *bus, int addr, int devad, int reg); 63 int (*write)(struct mii_dev *bus, int addr, int devad, int reg, 64 u16 val); 65 int (*reset)(struct mii_dev *bus); 66 struct phy_device *phymap[PHY_MAX_ADDR]; 67 u32 phy_mask; 68 }; 69 70 /* struct phy_driver: a structure which defines PHY behavior 71 * 72 * uid will contain a number which represents the PHY. During 73 * startup, the driver will poll the PHY to find out what its 74 * UID--as defined by registers 2 and 3--is. The 32-bit result 75 * gotten from the PHY will be masked to 76 * discard any bits which may change based on revision numbers 77 * unimportant to functionality 78 * 79 */ 80 struct phy_driver { 81 char *name; 82 unsigned int uid; 83 unsigned int mask; 84 unsigned int mmds; 85 86 u32 features; 87 88 /* Called to do any driver startup necessities */ 89 /* Will be called during phy_connect */ 90 int (*probe)(struct phy_device *phydev); 91 92 /* Called to configure the PHY, and modify the controller 93 * based on the results. Should be called after phy_connect */ 94 int (*config)(struct phy_device *phydev); 95 96 /* Called when starting up the controller */ 97 int (*startup)(struct phy_device *phydev); 98 99 /* Called when bringing down the controller */ 100 int (*shutdown)(struct phy_device *phydev); 101 102 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); 103 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, 104 u16 val); 105 106 /* Phy specific driver override for reading a MMD register */ 107 int (*read_mmd)(struct phy_device *phydev, int devad, int reg); 108 109 /* Phy specific driver override for writing a MMD register */ 110 int (*write_mmd)(struct phy_device *phydev, int devad, int reg, 111 u16 val); 112 113 struct list_head list; 114 }; 115 116 struct phy_device { 117 /* Information about the PHY type */ 118 /* And management functions */ 119 struct mii_dev *bus; 120 struct phy_driver *drv; 121 void *priv; 122 123 #ifdef CONFIG_DM_ETH 124 struct udevice *dev; 125 ofnode node; 126 #else 127 struct eth_device *dev; 128 #endif 129 130 /* forced speed & duplex (no autoneg) 131 * partner speed & duplex & pause (autoneg) 132 */ 133 int speed; 134 int duplex; 135 136 /* The most recently read link state */ 137 int link; 138 int port; 139 phy_interface_t interface; 140 141 u32 advertising; 142 u32 supported; 143 u32 mmds; 144 145 int autoneg; 146 int addr; 147 int pause; 148 int asym_pause; 149 u32 phy_id; 150 bool is_c45; 151 u32 flags; 152 }; 153 154 struct fixed_link { 155 int phy_id; 156 int duplex; 157 int link_speed; 158 int pause; 159 int asym_pause; 160 }; 161 162 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) 163 { 164 struct mii_dev *bus = phydev->bus; 165 166 return bus->read(bus, phydev->addr, devad, regnum); 167 } 168 169 static inline int phy_write(struct phy_device *phydev, int devad, int regnum, 170 u16 val) 171 { 172 struct mii_dev *bus = phydev->bus; 173 174 return bus->write(bus, phydev->addr, devad, regnum, val); 175 } 176 177 static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad, 178 int regnum) 179 { 180 /* Write the desired MMD Devad */ 181 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad); 182 183 /* Write the desired MMD register address */ 184 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum); 185 186 /* Select the Function : DATA with no post increment */ 187 phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, 188 (devad | MII_MMD_CTRL_NOINCR)); 189 } 190 191 static inline int phy_read_mmd(struct phy_device *phydev, int devad, 192 int regnum) 193 { 194 struct phy_driver *drv = phydev->drv; 195 196 if (regnum > (u16)~0 || devad > 32) 197 return -EINVAL; 198 199 /* driver-specific access */ 200 if (drv->read_mmd) 201 return drv->read_mmd(phydev, devad, regnum); 202 203 /* direct C45 / C22 access */ 204 if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES || 205 devad == MDIO_DEVAD_NONE || !devad) 206 return phy_read(phydev, devad, regnum); 207 208 /* indirect C22 access */ 209 phy_mmd_start_indirect(phydev, devad, regnum); 210 211 /* Read the content of the MMD's selected register */ 212 return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA); 213 } 214 215 static inline int phy_write_mmd(struct phy_device *phydev, int devad, 216 int regnum, u16 val) 217 { 218 struct phy_driver *drv = phydev->drv; 219 220 if (regnum > (u16)~0 || devad > 32) 221 return -EINVAL; 222 223 /* driver-specific access */ 224 if (drv->write_mmd) 225 return drv->write_mmd(phydev, devad, regnum, val); 226 227 /* direct C45 / C22 access */ 228 if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES || 229 devad == MDIO_DEVAD_NONE || !devad) 230 return phy_write(phydev, devad, regnum, val); 231 232 /* indirect C22 access */ 233 phy_mmd_start_indirect(phydev, devad, regnum); 234 235 /* Write the data into MMD's selected register */ 236 return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val); 237 } 238 239 #ifdef CONFIG_PHYLIB_10G 240 extern struct phy_driver gen10g_driver; 241 242 /* For now, XGMII is the only 10G interface */ 243 static inline int is_10g_interface(phy_interface_t interface) 244 { 245 return interface == PHY_INTERFACE_MODE_XGMII; 246 } 247 248 #endif 249 250 int phy_init(void); 251 int phy_reset(struct phy_device *phydev); 252 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, 253 phy_interface_t interface); 254 #ifdef CONFIG_DM_ETH 255 void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); 256 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 257 struct udevice *dev, 258 phy_interface_t interface); 259 static inline ofnode phy_get_ofnode(struct phy_device *phydev) 260 { 261 if (ofnode_valid(phydev->node)) 262 return phydev->node; 263 else 264 return dev_ofnode(phydev->dev); 265 } 266 #else 267 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); 268 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 269 struct eth_device *dev, 270 phy_interface_t interface); 271 static inline ofnode phy_get_ofnode(struct phy_device *phydev) 272 { 273 return ofnode_null(); 274 } 275 #endif 276 int phy_startup(struct phy_device *phydev); 277 int phy_config(struct phy_device *phydev); 278 int phy_shutdown(struct phy_device *phydev); 279 int phy_register(struct phy_driver *drv); 280 int phy_set_supported(struct phy_device *phydev, u32 max_speed); 281 int genphy_config_aneg(struct phy_device *phydev); 282 int genphy_restart_aneg(struct phy_device *phydev); 283 int genphy_update_link(struct phy_device *phydev); 284 int genphy_parse_link(struct phy_device *phydev); 285 int genphy_config(struct phy_device *phydev); 286 int genphy_startup(struct phy_device *phydev); 287 int genphy_shutdown(struct phy_device *phydev); 288 int gen10g_config(struct phy_device *phydev); 289 int gen10g_startup(struct phy_device *phydev); 290 int gen10g_shutdown(struct phy_device *phydev); 291 int gen10g_discover_mmds(struct phy_device *phydev); 292 293 int phy_mv88e61xx_init(void); 294 int phy_aquantia_init(void); 295 int phy_atheros_init(void); 296 int phy_broadcom_init(void); 297 int phy_cortina_init(void); 298 int phy_davicom_init(void); 299 int phy_et1011c_init(void); 300 int phy_lxt_init(void); 301 int phy_marvell_init(void); 302 int phy_micrel_ksz8xxx_init(void); 303 int phy_micrel_ksz90x1_init(void); 304 int phy_natsemi_init(void); 305 int phy_realtek_init(void); 306 int phy_smsc_init(void); 307 int phy_teranetics_init(void); 308 int phy_ti_init(void); 309 int phy_vitesse_init(void); 310 int phy_xilinx_init(void); 311 int phy_mscc_init(void); 312 int phy_fixed_init(void); 313 314 int board_phy_config(struct phy_device *phydev); 315 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); 316 317 /** 318 * phy_get_interface_by_name() - Look up a PHY interface name 319 * 320 * @str: PHY interface name, e.g. "mii" 321 * @return PHY_INTERFACE_MODE_... value, or -1 if not found 322 */ 323 int phy_get_interface_by_name(const char *str); 324 325 /** 326 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 327 * is RGMII (all variants) 328 * @phydev: the phy_device struct 329 */ 330 static inline bool phy_interface_is_rgmii(struct phy_device *phydev) 331 { 332 return phydev->interface >= PHY_INTERFACE_MODE_RGMII && 333 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; 334 } 335 336 /** 337 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface 338 * is SGMII (all variants) 339 * @phydev: the phy_device struct 340 */ 341 static inline bool phy_interface_is_sgmii(struct phy_device *phydev) 342 { 343 return phydev->interface >= PHY_INTERFACE_MODE_SGMII && 344 phydev->interface <= PHY_INTERFACE_MODE_QSGMII; 345 } 346 347 /* PHY UIDs for various PHYs that are referenced in external code */ 348 #define PHY_UID_CS4340 0x13e51002 349 #define PHY_UID_CS4223 0x03e57003 350 #define PHY_UID_TN2020 0x00a19410 351 #define PHY_UID_IN112525_S03 0x02107440 352 353 #endif 354