1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _PCI_H 12 #define _PCI_H 13 14 #define PCI_CFG_SPACE_SIZE 256 15 #define PCI_CFG_SPACE_EXP_SIZE 4096 16 17 /* 18 * Under PCI, each device has 256 bytes of configuration address space, 19 * of which the first 64 bytes are standardized as follows: 20 */ 21 #define PCI_STD_HEADER_SIZEOF 64 22 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 23 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 24 #define PCI_COMMAND 0x04 /* 16 bits */ 25 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 26 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 27 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 28 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 29 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 30 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 31 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 32 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 33 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 34 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 35 36 #define PCI_STATUS 0x06 /* 16 bits */ 37 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 38 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 39 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 40 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 41 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 42 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 43 #define PCI_STATUS_DEVSEL_FAST 0x000 44 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 45 #define PCI_STATUS_DEVSEL_SLOW 0x400 46 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 47 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 48 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 49 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 50 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 51 52 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 53 revision */ 54 #define PCI_REVISION_ID 0x08 /* Revision ID */ 55 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 56 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 57 #define PCI_CLASS_CODE 0x0b /* Device class code */ 58 #define PCI_CLASS_CODE_TOO_OLD 0x00 59 #define PCI_CLASS_CODE_STORAGE 0x01 60 #define PCI_CLASS_CODE_NETWORK 0x02 61 #define PCI_CLASS_CODE_DISPLAY 0x03 62 #define PCI_CLASS_CODE_MULTIMEDIA 0x04 63 #define PCI_CLASS_CODE_MEMORY 0x05 64 #define PCI_CLASS_CODE_BRIDGE 0x06 65 #define PCI_CLASS_CODE_COMM 0x07 66 #define PCI_CLASS_CODE_PERIPHERAL 0x08 67 #define PCI_CLASS_CODE_INPUT 0x09 68 #define PCI_CLASS_CODE_DOCKING 0x0A 69 #define PCI_CLASS_CODE_PROCESSOR 0x0B 70 #define PCI_CLASS_CODE_SERIAL 0x0C 71 #define PCI_CLASS_CODE_WIRELESS 0x0D 72 #define PCI_CLASS_CODE_I2O 0x0E 73 #define PCI_CLASS_CODE_SATELLITE 0x0F 74 #define PCI_CLASS_CODE_CRYPTO 0x10 75 #define PCI_CLASS_CODE_DATA 0x11 76 /* Base Class 0x12 - 0xFE is reserved */ 77 #define PCI_CLASS_CODE_OTHER 0xFF 78 79 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 80 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 81 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 82 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 83 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 84 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 85 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 86 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 87 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 88 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 89 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 90 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 91 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 92 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 93 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 94 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 95 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 96 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 97 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 98 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 99 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 100 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 101 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 102 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 105 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 106 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 107 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 108 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 109 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 110 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 111 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 112 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 113 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 114 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 115 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 116 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 117 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 118 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 119 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 120 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A 121 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 122 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 123 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 124 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 125 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 126 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 127 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 128 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 134 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 135 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 136 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 137 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 138 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 139 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 140 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 141 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 142 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 143 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 144 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 145 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 146 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 147 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 148 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 149 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 150 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 151 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 152 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 153 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 154 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 155 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 156 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 157 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 158 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 159 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 160 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 161 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 162 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 163 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 164 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 165 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 166 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 167 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 168 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 169 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 170 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 171 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 172 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 173 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 174 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 175 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 176 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 177 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 178 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 179 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 180 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 181 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 182 183 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 184 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 185 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 186 #define PCI_HEADER_TYPE_NORMAL 0 187 #define PCI_HEADER_TYPE_BRIDGE 1 188 #define PCI_HEADER_TYPE_CARDBUS 2 189 190 #define PCI_BIST 0x0f /* 8 bits */ 191 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 192 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 193 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 194 195 /* 196 * Base addresses specify locations in memory or I/O space. 197 * Decoded size can be determined by writing a value of 198 * 0xffffffff to the register, and reading it back. Only 199 * 1 bits are decoded. 200 */ 201 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 202 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 203 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 204 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 205 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 206 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 207 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 208 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 209 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 210 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 211 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 212 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 213 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 214 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 215 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 216 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 217 /* bit 1 is reserved if address_space = 1 */ 218 219 /* Header type 0 (normal devices) */ 220 #define PCI_CARDBUS_CIS 0x28 221 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 222 #define PCI_SUBSYSTEM_ID 0x2e 223 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 224 #define PCI_ROM_ADDRESS_ENABLE 0x01 225 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 226 227 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 228 229 /* 0x35-0x3b are reserved */ 230 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 231 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 232 #define PCI_MIN_GNT 0x3e /* 8 bits */ 233 #define PCI_MAX_LAT 0x3f /* 8 bits */ 234 235 #define PCI_INTERRUPT_LINE_DISABLE 0xff 236 237 /* Header type 1 (PCI-to-PCI bridges) */ 238 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 239 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 240 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 241 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 242 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 243 #define PCI_IO_LIMIT 0x1d 244 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 245 #define PCI_IO_RANGE_TYPE_16 0x00 246 #define PCI_IO_RANGE_TYPE_32 0x01 247 #define PCI_IO_RANGE_MASK ~0x0f 248 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 249 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 250 #define PCI_MEMORY_LIMIT 0x22 251 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 252 #define PCI_MEMORY_RANGE_MASK ~0x0f 253 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 254 #define PCI_PREF_MEMORY_LIMIT 0x26 255 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 256 #define PCI_PREF_RANGE_TYPE_32 0x00 257 #define PCI_PREF_RANGE_TYPE_64 0x01 258 #define PCI_PREF_RANGE_MASK ~0x0f 259 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 260 #define PCI_PREF_LIMIT_UPPER32 0x2c 261 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 262 #define PCI_IO_LIMIT_UPPER16 0x32 263 /* 0x34 same as for htype 0 */ 264 /* 0x35-0x3b is reserved */ 265 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 266 /* 0x3c-0x3d are same as for htype 0 */ 267 #define PCI_BRIDGE_CONTROL 0x3e 268 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 269 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 270 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 271 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 272 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 273 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 274 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 275 276 /* From 440ep */ 277 #define PCI_ERREN 0x48 /* Error Enable */ 278 #define PCI_ERRSTS 0x49 /* Error Status */ 279 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ 280 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ 281 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ 282 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ 283 #define PCI_CAPID 0x58 /* Capability Identifier */ 284 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ 285 #define PCI_PMC 0x5A /* Power Management Capabilities */ 286 #define PCI_PMCSR 0x5C /* Power Management Control Status */ 287 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ 288 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ 289 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ 290 291 /* Header type 2 (CardBus bridges) */ 292 #define PCI_CB_CAPABILITY_LIST 0x14 293 /* 0x15 reserved */ 294 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 295 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 296 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 297 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 298 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 299 #define PCI_CB_MEMORY_BASE_0 0x1c 300 #define PCI_CB_MEMORY_LIMIT_0 0x20 301 #define PCI_CB_MEMORY_BASE_1 0x24 302 #define PCI_CB_MEMORY_LIMIT_1 0x28 303 #define PCI_CB_IO_BASE_0 0x2c 304 #define PCI_CB_IO_BASE_0_HI 0x2e 305 #define PCI_CB_IO_LIMIT_0 0x30 306 #define PCI_CB_IO_LIMIT_0_HI 0x32 307 #define PCI_CB_IO_BASE_1 0x34 308 #define PCI_CB_IO_BASE_1_HI 0x36 309 #define PCI_CB_IO_LIMIT_1 0x38 310 #define PCI_CB_IO_LIMIT_1_HI 0x3a 311 #define PCI_CB_IO_RANGE_MASK ~0x03 312 /* 0x3c-0x3d are same as for htype 0 */ 313 #define PCI_CB_BRIDGE_CONTROL 0x3e 314 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 315 #define PCI_CB_BRIDGE_CTL_SERR 0x02 316 #define PCI_CB_BRIDGE_CTL_ISA 0x04 317 #define PCI_CB_BRIDGE_CTL_VGA 0x08 318 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 319 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 320 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 321 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 322 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 323 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 324 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 325 #define PCI_CB_SUBSYSTEM_ID 0x42 326 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 327 /* 0x48-0x7f reserved */ 328 329 /* Capability lists */ 330 331 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 332 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 333 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 334 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 335 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 336 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 337 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 338 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 339 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 340 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 341 #define PCI_CAP_SIZEOF 4 342 343 /* Power Management Registers */ 344 345 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 346 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 347 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 348 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 349 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 350 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 351 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 352 #define PCI_PM_CTRL 4 /* PM control and status register */ 353 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 354 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 355 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 356 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 357 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 358 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 359 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 360 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 361 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 362 #define PCI_PM_SIZEOF 8 363 364 /* AGP registers */ 365 366 #define PCI_AGP_VERSION 2 /* BCD version number */ 367 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 368 #define PCI_AGP_STATUS 4 /* Status register */ 369 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 370 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 371 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 372 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 373 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 374 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 375 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 376 #define PCI_AGP_COMMAND 8 /* Control register */ 377 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 378 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 379 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 380 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 381 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 382 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 383 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 384 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 385 #define PCI_AGP_SIZEOF 12 386 387 /* PCI-X registers */ 388 389 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 390 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 391 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 392 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 393 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 394 395 396 /* Slot Identification */ 397 398 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 399 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 400 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 401 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 402 403 /* Message Signalled Interrupts registers */ 404 405 #define PCI_MSI_FLAGS 2 /* Various flags */ 406 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 407 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 408 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 409 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 410 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 411 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 412 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 413 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 414 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 415 416 #define PCI_MAX_PCI_DEVICES 32 417 #define PCI_MAX_PCI_FUNCTIONS 8 418 419 #define PCI_FIND_CAP_TTL 0x48 420 #define CAP_START_POS 0x40 421 422 /* AER register offsets (relative to the AER Capability base address) */ 423 #define PCI_AER_STATUS 0x08 /* AER Status Register */ 424 #define PCI_AER_MASK 0x0C /* AER Mask Register */ 425 #define PCI_AER_SEVERITY 0x10 /* AER Severity Register */ 426 427 /* Extended Capabilities (PCI-X 2.0 and Express) */ 428 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 429 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 430 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 431 432 /* PCIe Capability Registers */ 433 #define PCI_EXP_DEVCAP 0x04 /* Device capabilities */ 434 #define PCI_EXP_LNKCTL 0x10 /* Link Control Register */ 435 #define PCI_EXP_LNKSTA 0x12 /* Link Status Register */ 436 #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ 437 438 /* Link Status Register bits */ 439 #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ 440 #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 441 #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ 442 443 #define PCI_EXP_DEVCTL 8 /* Device Control Register offset */ 444 #define PCI_EXP_DEVCTL_FLR 0x8000 /* FLR bit in Device Control Register */ 445 446 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 447 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 448 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 449 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 450 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 451 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 452 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 453 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 454 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 455 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 456 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 457 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 458 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 459 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 460 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 461 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 462 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 463 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 464 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 465 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 466 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 467 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 468 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 469 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 470 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 471 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 472 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 473 474 /* Include the ID list */ 475 476 #include <pci_ids.h> 477 478 #ifndef __ASSEMBLY__ 479 480 #ifdef CONFIG_SYS_PCI_64BIT 481 typedef u64 pci_addr_t; 482 typedef u64 pci_size_t; 483 #else 484 typedef u32 pci_addr_t; 485 typedef u32 pci_size_t; 486 #endif 487 488 struct pci_region { 489 pci_addr_t bus_start; /* Start on the bus */ 490 phys_addr_t phys_start; /* Start in physical address space */ 491 pci_size_t size; /* Size */ 492 unsigned long flags; /* Resource flags */ 493 494 pci_addr_t bus_lower; 495 }; 496 497 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 498 #define PCI_REGION_IO 0x00000001 /* PCI IO space */ 499 #define PCI_REGION_TYPE 0x00000001 500 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 501 502 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 503 #define PCI_REGION_RO 0x00000200 /* Read-only memory */ 504 505 static inline void pci_set_region(struct pci_region *reg, 506 pci_addr_t bus_start, 507 phys_addr_t phys_start, 508 pci_size_t size, 509 unsigned long flags) { 510 reg->bus_start = bus_start; 511 reg->phys_start = phys_start; 512 reg->size = size; 513 reg->flags = flags; 514 } 515 516 typedef int pci_dev_t; 517 518 #define PCI_BUS(d) (((d) >> 16) & 0xff) 519 #define PCI_DEV(d) (((d) >> 11) & 0x1f) 520 #define PCI_FUNC(d) (((d) >> 8) & 0x7) 521 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) 522 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) 523 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) 524 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) 525 #define PCI_VENDEV(v, d) (((v) << 16) | (d)) 526 #define PCI_ANY_ID (~0) 527 528 struct pci_device_id { 529 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 530 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ 531 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ 532 unsigned long driver_data; /* Data private to the driver */ 533 }; 534 535 struct pci_device_state { 536 u32 bar[6]; /* Saved BARs */ 537 u16 command; /* Saved Command Register */ 538 u8 primary_bus; /* Saved Primary Bus Number (for bridge) */ 539 u8 secondary_bus; /* Saved Secondary Bus Number (for bridge) */ 540 u8 subordinate_bus; /* Saved Subordinate Bus Number (for bridge) */ 541 }; 542 543 struct pci_controller; 544 545 struct pci_config_table { 546 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 547 unsigned int class; /* Class ID, or PCI_ANY_ID */ 548 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 549 unsigned int dev; /* Device number, or PCI_ANY_ID */ 550 unsigned int func; /* Function number, or PCI_ANY_ID */ 551 552 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 553 struct pci_config_table *); 554 unsigned long priv[3]; 555 }; 556 557 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 558 struct pci_config_table *); 559 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 560 struct pci_config_table *); 561 562 #define MAX_PCI_REGIONS 7 563 564 #define INDIRECT_TYPE_NO_PCIE_LINK 1 565 566 /* 567 * Structure of a PCI controller (host bridge) 568 * 569 * With driver model this is dev_get_uclass_priv(bus) 570 */ 571 struct pci_controller { 572 #ifdef CONFIG_DM_PCI 573 struct udevice *bus; 574 struct udevice *ctlr; 575 #else 576 struct pci_controller *next; 577 #endif 578 579 int first_busno; 580 int last_busno; 581 582 volatile unsigned int *cfg_addr; 583 volatile unsigned char *cfg_data; 584 585 int indirect_type; 586 587 /* 588 * TODO(sjg@chromium.org): With driver model we use struct 589 * pci_controller for both the controller and any bridge devices 590 * attached to it. But there is only one region list and it is in the 591 * top-level controller. 592 * 593 * This could be changed so that struct pci_controller is only used 594 * for PCI controllers and a separate UCLASS (or perhaps 595 * UCLASS_PCI_GENERIC) is used for bridges. 596 */ 597 struct pci_region regions[MAX_PCI_REGIONS]; 598 int region_count; 599 600 struct pci_config_table *config_table; 601 602 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 603 #ifndef CONFIG_DM_PCI 604 /* Low-level architecture-dependent routines */ 605 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); 606 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); 607 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); 608 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); 609 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); 610 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); 611 #endif 612 613 /* Used by auto config */ 614 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 615 616 /* Used by ppc405 autoconfig*/ 617 struct pci_region *pci_fb; 618 #ifndef CONFIG_DM_PCI 619 int current_busno; 620 621 void *priv_data; 622 #endif 623 }; 624 625 #ifndef CONFIG_DM_PCI 626 static inline void pci_set_ops(struct pci_controller *hose, 627 int (*read_byte)(struct pci_controller*, 628 pci_dev_t, int where, u8 *), 629 int (*read_word)(struct pci_controller*, 630 pci_dev_t, int where, u16 *), 631 int (*read_dword)(struct pci_controller*, 632 pci_dev_t, int where, u32 *), 633 int (*write_byte)(struct pci_controller*, 634 pci_dev_t, int where, u8), 635 int (*write_word)(struct pci_controller*, 636 pci_dev_t, int where, u16), 637 int (*write_dword)(struct pci_controller*, 638 pci_dev_t, int where, u32)) { 639 hose->read_byte = read_byte; 640 hose->read_word = read_word; 641 hose->read_dword = read_dword; 642 hose->write_byte = write_byte; 643 hose->write_word = write_word; 644 hose->write_dword = write_dword; 645 } 646 #endif 647 648 #ifdef CONFIG_PCI_INDIRECT_BRIDGE 649 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); 650 #endif 651 652 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 653 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 654 pci_addr_t addr, unsigned long flags); 655 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 656 phys_addr_t addr, unsigned long flags); 657 658 #define pci_phys_to_bus(dev, addr, flags) \ 659 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 660 #define pci_bus_to_phys(dev, addr, flags) \ 661 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 662 663 #define pci_virt_to_bus(dev, addr, flags) \ 664 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 665 (virt_to_phys(addr)), (flags)) 666 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 667 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 668 (addr), (flags)), \ 669 (len), (map_flags)) 670 671 #define pci_phys_to_mem(dev, addr) \ 672 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 673 #define pci_mem_to_phys(dev, addr) \ 674 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 675 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 676 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 677 678 #define pci_virt_to_mem(dev, addr) \ 679 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 680 #define pci_mem_to_virt(dev, addr, len, map_flags) \ 681 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 682 #define pci_virt_to_io(dev, addr) \ 683 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 684 #define pci_io_to_virt(dev, addr, len, map_flags) \ 685 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 686 687 /* For driver model these are defined in macros in pci_compat.c */ 688 extern int pci_hose_read_config_byte(struct pci_controller *hose, 689 pci_dev_t dev, int where, u8 *val); 690 extern int pci_hose_read_config_word(struct pci_controller *hose, 691 pci_dev_t dev, int where, u16 *val); 692 extern int pci_hose_read_config_dword(struct pci_controller *hose, 693 pci_dev_t dev, int where, u32 *val); 694 extern int pci_hose_write_config_byte(struct pci_controller *hose, 695 pci_dev_t dev, int where, u8 val); 696 extern int pci_hose_write_config_word(struct pci_controller *hose, 697 pci_dev_t dev, int where, u16 val); 698 extern int pci_hose_write_config_dword(struct pci_controller *hose, 699 pci_dev_t dev, int where, u32 val); 700 #endif 701 702 #ifndef CONFIG_DM_PCI 703 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); 704 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); 705 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); 706 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); 707 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); 708 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); 709 #endif 710 711 void pciauto_region_init(struct pci_region *res); 712 void pciauto_region_align(struct pci_region *res, pci_size_t size); 713 void pciauto_config_init(struct pci_controller *hose); 714 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 715 pci_addr_t *bar); 716 717 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 718 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 719 pci_dev_t dev, int where, u8 *val); 720 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 721 pci_dev_t dev, int where, u16 *val); 722 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 723 pci_dev_t dev, int where, u8 val); 724 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 725 pci_dev_t dev, int where, u16 val); 726 727 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 728 extern void pci_register_hose(struct pci_controller* hose); 729 extern struct pci_controller* pci_bus_to_hose(int bus); 730 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 731 extern struct pci_controller *pci_get_hose_head(void); 732 733 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); 734 extern int pci_hose_scan(struct pci_controller *hose); 735 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 736 737 extern void pciauto_setup_device(struct pci_controller *hose, 738 pci_dev_t dev, int bars_num, 739 struct pci_region *mem, 740 struct pci_region *prefetch, 741 struct pci_region *io); 742 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 743 pci_dev_t dev, int sub_bus); 744 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 745 pci_dev_t dev, int sub_bus); 746 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 747 748 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 749 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 750 pci_dev_t pci_find_class(unsigned int find_class, int index); 751 752 extern int pci_hose_config_device(struct pci_controller *hose, 753 pci_dev_t dev, 754 unsigned long io, 755 pci_addr_t mem, 756 unsigned long command); 757 758 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 759 int cap); 760 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 761 u8 hdr_type); 762 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 763 int cap); 764 765 int pci_find_next_ext_capability(struct pci_controller *hose, 766 pci_dev_t dev, int start, int cap); 767 int pci_hose_find_ext_capability(struct pci_controller *hose, 768 pci_dev_t dev, int cap); 769 770 #ifdef CONFIG_PCI_FIXUP_DEV 771 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 772 unsigned short vendor, 773 unsigned short device, 774 unsigned short class); 775 #endif 776 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ 777 778 const char * pci_class_str(u8 class); 779 int pci_last_busno(void); 780 781 #ifdef CONFIG_MPC85xx 782 extern void pci_mpc85xx_init (struct pci_controller *hose); 783 #endif 784 785 #ifdef CONFIG_PCIE_IMX 786 extern void imx_pcie_remove(void); 787 #endif 788 789 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 790 /** 791 * pci_write_bar32() - Write the address of a BAR including control bits 792 * 793 * This writes a raw address (with control bits) to a bar. This can be used 794 * with devices which require hard-coded addresses, not part of the normal 795 * PCI enumeration process. 796 * 797 * @hose: PCI hose to use 798 * @dev: PCI device to update 799 * @barnum: BAR number (0-5) 800 * @addr: BAR address with control bits 801 */ 802 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, 803 u32 addr); 804 805 /** 806 * pci_read_bar32() - read the address of a bar 807 * 808 * @hose: PCI hose to use 809 * @dev: PCI device to inspect 810 * @barnum: BAR number (0-5) 811 * @return address of the bar, masking out any control bits 812 * */ 813 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); 814 815 /** 816 * pci_hose_find_devices() - Find devices by vendor/device ID 817 * 818 * @hose: PCI hose to search 819 * @busnum: Bus number to search 820 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 821 * @indexp: Pointer to device index to find. To find the first matching 822 * device, pass 0; to find the second, pass 1, etc. This 823 * parameter is decremented for each non-matching device so 824 * can be called repeatedly. 825 */ 826 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, 827 struct pci_device_id *ids, int *indexp); 828 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ 829 830 /* Access sizes for PCI reads and writes */ 831 enum pci_size_t { 832 PCI_SIZE_8, 833 PCI_SIZE_16, 834 PCI_SIZE_32, 835 }; 836 837 struct udevice; 838 839 #ifdef CONFIG_DM_PCI 840 /** 841 * struct pci_child_platdata - information stored about each PCI device 842 * 843 * Every device on a PCI bus has this per-child data. 844 * 845 * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a 846 * PCI bus (i.e. UCLASS_PCI) 847 * 848 * @devfn: Encoded device and function index - see PCI_DEVFN() 849 * @vendor: PCI vendor ID (see pci_ids.h) 850 * @device: PCI device ID (see pci_ids.h) 851 * @class: PCI class, 3 bytes: (base, sub, prog-if) 852 */ 853 struct pci_child_platdata { 854 int devfn; 855 unsigned short vendor; 856 unsigned short device; 857 unsigned int class; 858 }; 859 860 /* PCI bus operations */ 861 struct dm_pci_ops { 862 /** 863 * read_config() - Read a PCI configuration value 864 * 865 * PCI buses must support reading and writing configuration values 866 * so that the bus can be scanned and its devices configured. 867 * 868 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. 869 * If bridges exist it is possible to use the top-level bus to 870 * access a sub-bus. In that case @bus will be the top-level bus 871 * and PCI_BUS(bdf) will be a different (higher) value 872 * 873 * @bus: Bus to read from 874 * @bdf: Bus, device and function to read 875 * @offset: Byte offset within the device's configuration space 876 * @valuep: Place to put the returned value 877 * @size: Access size 878 * @return 0 if OK, -ve on error 879 */ 880 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 881 ulong *valuep, enum pci_size_t size); 882 /** 883 * write_config() - Write a PCI configuration value 884 * 885 * @bus: Bus to write to 886 * @bdf: Bus, device and function to write 887 * @offset: Byte offset within the device's configuration space 888 * @value: Value to write 889 * @size: Access size 890 * @return 0 if OK, -ve on error 891 */ 892 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 893 ulong value, enum pci_size_t size); 894 /** 895 * vendor_aer_dump() - Dump vendor-specific aer information 896 * 897 * @bus: Bus of pci_controller 898 * @return 0 if OK, -ve on error 899 */ 900 int (*vendor_aer_dump)(struct udevice *bus); 901 }; 902 903 /* Get access to a PCI bus' operations */ 904 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) 905 906 /** 907 * dm_pci_get_bdf() - Get the BDF value for a device 908 * 909 * @dev: Device to check 910 * @return bus/device/function value (see PCI_BDF()) 911 */ 912 pci_dev_t dm_pci_get_bdf(struct udevice *dev); 913 914 /** 915 * pci_bind_bus_devices() - scan a PCI bus and bind devices 916 * 917 * Scan a PCI bus looking for devices. Bind each one that is found. If 918 * devices are already bound that match the scanned devices, just update the 919 * child data so that the device can be used correctly (this happens when 920 * the device tree describes devices we expect to see on the bus). 921 * 922 * Devices that are bound in this way will use a generic PCI driver which 923 * does nothing. The device can still be accessed but will not provide any 924 * driver interface. 925 * 926 * @bus: Bus containing devices to bind 927 * @return 0 if OK, -ve on error 928 */ 929 int pci_bind_bus_devices(struct udevice *bus); 930 931 /** 932 * pci_auto_config_devices() - configure bus devices ready for use 933 * 934 * This works through all devices on a bus by scanning the driver model 935 * data structures (normally these have been set up by pci_bind_bus_devices() 936 * earlier). 937 * 938 * Space is allocated for each PCI base address register (BAR) so that the 939 * devices are mapped into memory and I/O space ready for use. 940 * 941 * @bus: Bus containing devices to bind 942 * @return 0 if OK, -ve on error 943 */ 944 int pci_auto_config_devices(struct udevice *bus); 945 946 /** 947 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address 948 * 949 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 950 * @devp: Returns the device for this address, if found 951 * @return 0 if OK, -ENODEV if not found 952 */ 953 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); 954 955 /** 956 * pci_bus_find_devfn() - Find a device on a bus 957 * 958 * @find_devfn: PCI device address (device and function only) 959 * @devp: Returns the device for this address, if found 960 * @return 0 if OK, -ENODEV if not found 961 */ 962 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 963 struct udevice **devp); 964 965 /** 966 * pci_find_first_device() - return the first available PCI device 967 * 968 * This function and pci_find_first_device() allow iteration through all 969 * available PCI devices on all buses. Assuming there are any, this will 970 * return the first one. 971 * 972 * @devp: Set to the first available device, or NULL if no more are left 973 * or we got an error 974 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 975 */ 976 int pci_find_first_device(struct udevice **devp); 977 978 /** 979 * pci_find_next_device() - return the next available PCI device 980 * 981 * Finds the next available PCI device after the one supplied, or sets @devp 982 * to NULL if there are no more. 983 * 984 * @devp: On entry, the last device returned. Set to the next available 985 * device, or NULL if no more are left or we got an error 986 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 987 */ 988 int pci_find_next_device(struct udevice **devp); 989 990 /** 991 * pci_get_ff() - Returns a mask for the given access size 992 * 993 * @size: Access size 994 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for 995 * PCI_SIZE_32 996 */ 997 int pci_get_ff(enum pci_size_t size); 998 999 /** 1000 * pci_bus_find_devices () - Find devices on a bus 1001 * 1002 * @bus: Bus to search 1003 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 1004 * @indexp: Pointer to device index to find. To find the first matching 1005 * device, pass 0; to find the second, pass 1, etc. This 1006 * parameter is decremented for each non-matching device so 1007 * can be called repeatedly. 1008 * @devp: Returns matching device if found 1009 * @return 0 if found, -ENODEV if not 1010 */ 1011 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 1012 int *indexp, struct udevice **devp); 1013 1014 /** 1015 * pci_find_device_id() - Find a device on any bus 1016 * 1017 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 1018 * @index: Index number of device to find, 0 for the first match, 1 for 1019 * the second, etc. 1020 * @devp: Returns matching device if found 1021 * @return 0 if found, -ENODEV if not 1022 */ 1023 int pci_find_device_id(struct pci_device_id *ids, int index, 1024 struct udevice **devp); 1025 1026 /** 1027 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices 1028 * 1029 * This probes the given bus which causes it to be scanned for devices. The 1030 * devices will be bound but not probed. 1031 * 1032 * @hose specifies the PCI hose that will be used for the scan. This is 1033 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is 1034 * in @bdf, and is a subordinate bus reachable from @hose. 1035 * 1036 * @hose: PCI hose to scan 1037 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) 1038 * @return 0 if OK, -ve on error 1039 */ 1040 int dm_pci_hose_probe_bus(struct udevice *bus); 1041 1042 /** 1043 * pci_bus_read_config() - Read a configuration value from a device 1044 * 1045 * TODO(sjg@chromium.org): We should be able to pass just a device and have 1046 * it do the right thing. It would be good to have that function also. 1047 * 1048 * @bus: Bus to read from 1049 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1050 * @offset: Register offset to read 1051 * @valuep: Place to put the returned value 1052 * @size: Access size 1053 * @return 0 if OK, -ve on error 1054 */ 1055 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 1056 unsigned long *valuep, enum pci_size_t size); 1057 1058 /** 1059 * pci_bus_write_config() - Write a configuration value to a device 1060 * 1061 * @bus: Bus to write from 1062 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1063 * @offset: Register offset to write 1064 * @value: Value to write 1065 * @size: Access size 1066 * @return 0 if OK, -ve on error 1067 */ 1068 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 1069 unsigned long value, enum pci_size_t size); 1070 1071 /** 1072 * pci_bus_clrset_config32() - Update a configuration value for a device 1073 * 1074 * The register at @offset is updated to (oldvalue & ~clr) | set. 1075 * 1076 * @bus: Bus to access 1077 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1078 * @offset: Register offset to update 1079 * @clr: Bits to clear 1080 * @set: Bits to set 1081 * @return 0 if OK, -ve on error 1082 */ 1083 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, 1084 u32 clr, u32 set); 1085 1086 /** 1087 * Driver model PCI config access functions. Use these in preference to others 1088 * when you have a valid device 1089 */ 1090 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, 1091 enum pci_size_t size); 1092 1093 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep); 1094 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep); 1095 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep); 1096 1097 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, 1098 enum pci_size_t size); 1099 1100 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value); 1101 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value); 1102 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); 1103 1104 /** 1105 * These permit convenient read/modify/write on PCI configuration. The 1106 * register is updated to (oldvalue & ~clr) | set. 1107 */ 1108 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set); 1109 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set); 1110 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set); 1111 1112 /* 1113 * The following functions provide access to the above without needing the 1114 * size parameter. We are trying to encourage the use of the 8/16/32-style 1115 * functions, rather than byte/word/dword. But both are supported. 1116 */ 1117 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); 1118 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); 1119 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); 1120 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); 1121 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); 1122 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); 1123 1124 #ifdef CONFIG_DM_PCI_COMPAT 1125 /* Compatibility with old naming */ 1126 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, 1127 u32 value) 1128 { 1129 return pci_write_config32(pcidev, offset, value); 1130 } 1131 1132 /* Compatibility with old naming */ 1133 static inline int pci_write_config_word(pci_dev_t pcidev, int offset, 1134 u16 value) 1135 { 1136 return pci_write_config16(pcidev, offset, value); 1137 } 1138 1139 /* Compatibility with old naming */ 1140 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, 1141 u8 value) 1142 { 1143 return pci_write_config8(pcidev, offset, value); 1144 } 1145 1146 /* Compatibility with old naming */ 1147 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, 1148 u32 *valuep) 1149 { 1150 return pci_read_config32(pcidev, offset, valuep); 1151 } 1152 1153 /* Compatibility with old naming */ 1154 static inline int pci_read_config_word(pci_dev_t pcidev, int offset, 1155 u16 *valuep) 1156 { 1157 return pci_read_config16(pcidev, offset, valuep); 1158 } 1159 1160 /* Compatibility with old naming */ 1161 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, 1162 u8 *valuep) 1163 { 1164 return pci_read_config8(pcidev, offset, valuep); 1165 } 1166 #endif /* CONFIG_DM_PCI_COMPAT */ 1167 1168 /** 1169 * dm_pciauto_config_device() - configure a device ready for use 1170 * 1171 * Space is allocated for each PCI base address register (BAR) so that the 1172 * devices are mapped into memory and I/O space ready for use. 1173 * 1174 * @dev: Device to configure 1175 * @return 0 if OK, -ve on error 1176 */ 1177 int dm_pciauto_config_device(struct udevice *dev); 1178 1179 /** 1180 * pci_conv_32_to_size() - convert a 32-bit read value to the given size 1181 * 1182 * Some PCI buses must always perform 32-bit reads. The data must then be 1183 * shifted and masked to reflect the required access size and offset. This 1184 * function performs this transformation. 1185 * 1186 * @value: Value to transform (32-bit value read from @offset & ~3) 1187 * @offset: Register offset that was read 1188 * @size: Required size of the result 1189 * @return the value that would have been obtained if the read had been 1190 * performed at the given offset with the correct size 1191 */ 1192 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); 1193 1194 /** 1195 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write 1196 * 1197 * Some PCI buses must always perform 32-bit writes. To emulate a smaller 1198 * write the old 32-bit data must be read, updated with the required new data 1199 * and written back as a 32-bit value. This function performs the 1200 * transformation from the old value to the new value. 1201 * 1202 * @value: Value to transform (32-bit value read from @offset & ~3) 1203 * @offset: Register offset that should be written 1204 * @size: Required size of the write 1205 * @return the value that should be written as a 32-bit access to @offset & ~3. 1206 */ 1207 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, 1208 enum pci_size_t size); 1209 1210 /** 1211 * pci_get_controller() - obtain the controller to use for a bus 1212 * 1213 * @dev: Device to check 1214 * @return pointer to the controller device for this bus 1215 */ 1216 struct udevice *pci_get_controller(struct udevice *dev); 1217 1218 /** 1219 * pci_get_regions() - obtain pointers to all the region types 1220 * 1221 * @dev: Device to check 1222 * @iop: Returns a pointer to the I/O region, or NULL if none 1223 * @memp: Returns a pointer to the memory region, or NULL if none 1224 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none 1225 * @return the number of non-NULL regions returned, normally 3 1226 */ 1227 int pci_get_regions(struct udevice *dev, struct pci_region **iop, 1228 struct pci_region **memp, struct pci_region **prefp); 1229 1230 /** 1231 * pci_aer_dump() - dump AER (Advanced Error Reporting) information for a PCIe device 1232 * 1233 * @udev: PCI device to dump AER information 1234 * @dev: PCI device and function address 1235 * @return: 0 if successful, negative error code on failure 1236 */ 1237 int pci_aer_dump(struct udevice *udev, pci_dev_t dev); 1238 1239 /** 1240 * pci_retrain_link - Trigger PCIe link retrain for a device 1241 * @udev: PCI device to retrain link 1242 * @dev: PCI device and function address 1243 * 1244 * Return: 0 on success, negative error code on failure. 1245 */ 1246 int pci_retrain_link(struct udevice *udev, pci_dev_t dev); 1247 1248 /** 1249 * pci_reset_function - Reset a PCI/PCIe function using Function Level Reset (FLR). 1250 * 1251 * This function performs the following steps: 1252 * 1. Saves the device's config space (BARs, Command Register, Bus Numbers for bridges). 1253 * 2. Triggers a FLR to reset the device. 1254 * 3. Restores the saved configuration space state after the FLR completes. 1255 * 1256 * @udev: PCI function device to be reset 1257 * @dev: The PCI device identifier (BDF: Bus, Device, Function). 1258 * @return 0 on success, -1 on failure. 1259 */ 1260 int pci_reset_function(struct udevice *udev, pci_dev_t dev); 1261 1262 /** 1263 * dm_pci_write_bar32() - Write the address of a BAR 1264 * 1265 * This writes a raw address to a bar 1266 * 1267 * @dev: PCI device to update 1268 * @barnum: BAR number (0-5) 1269 * @addr: BAR address 1270 */ 1271 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); 1272 1273 /** 1274 * dm_pci_read_bar32() - read a base address register from a device 1275 * 1276 * @dev: Device to check 1277 * @barnum: Bar number to read (numbered from 0) 1278 * @return: value of BAR 1279 */ 1280 u32 dm_pci_read_bar32(struct udevice *dev, int barnum); 1281 1282 /** 1283 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address 1284 * 1285 * @dev: Device containing the PCI address 1286 * @addr: PCI address to convert 1287 * @flags: Flags for the region type (PCI_REGION_...) 1288 * @return physical address corresponding to that PCI bus address 1289 */ 1290 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, 1291 unsigned long flags); 1292 1293 /** 1294 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address 1295 * 1296 * @dev: Device containing the bus address 1297 * @addr: Physical address to convert 1298 * @flags: Flags for the region type (PCI_REGION_...) 1299 * @return PCI bus address corresponding to that physical address 1300 */ 1301 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, 1302 unsigned long flags); 1303 1304 /** 1305 * dm_pci_map_bar() - get a virtual address associated with a BAR region 1306 * 1307 * Looks up a base address register and finds the physical memory address 1308 * that corresponds to it 1309 * 1310 * @dev: Device to check 1311 * @bar: Bar number to read (numbered from 0) 1312 * @flags: Flags for the region type (PCI_REGION_...) 1313 * @return: pointer to the virtual address to use 1314 */ 1315 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); 1316 1317 /** 1318 * dm_pci_find_next_capability() - find a capability starting from an offset 1319 * 1320 * Tell if a device supports a given PCI capability. Returns the 1321 * address of the requested capability structure within the device's 1322 * PCI configuration space or 0 in case the device does not support it. 1323 * 1324 * Possible values for @cap: 1325 * 1326 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1327 * %PCI_CAP_ID_PCIX PCI-X 1328 * %PCI_CAP_ID_EXP PCI Express 1329 * %PCI_CAP_ID_MSIX MSI-X 1330 * 1331 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1332 * 1333 * @dev: PCI device to query 1334 * @start: offset to start from 1335 * @cap: capability code 1336 * @return: capability address or 0 if not supported 1337 */ 1338 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap); 1339 1340 /** 1341 * dm_pci_find_capability() - find a capability 1342 * 1343 * Tell if a device supports a given PCI capability. Returns the 1344 * address of the requested capability structure within the device's 1345 * PCI configuration space or 0 in case the device does not support it. 1346 * 1347 * Possible values for @cap: 1348 * 1349 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1350 * %PCI_CAP_ID_PCIX PCI-X 1351 * %PCI_CAP_ID_EXP PCI Express 1352 * %PCI_CAP_ID_MSIX MSI-X 1353 * 1354 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1355 * 1356 * @dev: PCI device to query 1357 * @cap: capability code 1358 * @return: capability address or 0 if not supported 1359 */ 1360 int dm_pci_find_capability(struct udevice *dev, int cap); 1361 1362 /** 1363 * dm_pci_find_next_ext_capability() - find an extended capability 1364 * starting from an offset 1365 * 1366 * Tell if a device supports a given PCI express extended capability. 1367 * Returns the address of the requested extended capability structure 1368 * within the device's PCI configuration space or 0 in case the device 1369 * does not support it. 1370 * 1371 * Possible values for @cap: 1372 * 1373 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1374 * %PCI_EXT_CAP_ID_VC Virtual Channel 1375 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1376 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1377 * 1378 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1379 * 1380 * @dev: PCI device to query 1381 * @start: offset to start from 1382 * @cap: extended capability code 1383 * @return: extended capability address or 0 if not supported 1384 */ 1385 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap); 1386 1387 /** 1388 * dm_pci_find_ext_capability() - find an extended capability 1389 * 1390 * Tell if a device supports a given PCI express extended capability. 1391 * Returns the address of the requested extended capability structure 1392 * within the device's PCI configuration space or 0 in case the device 1393 * does not support it. 1394 * 1395 * Possible values for @cap: 1396 * 1397 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1398 * %PCI_EXT_CAP_ID_VC Virtual Channel 1399 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1400 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1401 * 1402 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1403 * 1404 * @dev: PCI device to query 1405 * @cap: extended capability code 1406 * @return: extended capability address or 0 if not supported 1407 */ 1408 int dm_pci_find_ext_capability(struct udevice *dev, int cap); 1409 1410 #define dm_pci_virt_to_bus(dev, addr, flags) \ 1411 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) 1412 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 1413 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \ 1414 (len), (map_flags)) 1415 1416 #define dm_pci_phys_to_mem(dev, addr) \ 1417 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 1418 #define dm_pci_mem_to_phys(dev, addr) \ 1419 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 1420 #define dm_pci_phys_to_io(dev, addr) \ 1421 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 1422 #define dm_pci_io_to_phys(dev, addr) \ 1423 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 1424 1425 #define dm_pci_virt_to_mem(dev, addr) \ 1426 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 1427 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ 1428 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 1429 #define dm_pci_virt_to_io(dev, addr) \ 1430 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 1431 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \ 1432 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 1433 1434 /** 1435 * dm_pci_find_device() - find a device by vendor/device ID 1436 * 1437 * @vendor: Vendor ID 1438 * @device: Device ID 1439 * @index: 0 to find the first match, 1 for second, etc. 1440 * @devp: Returns pointer to the device, if found 1441 * @return 0 if found, -ve on error 1442 */ 1443 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, 1444 struct udevice **devp); 1445 1446 /** 1447 * dm_pci_find_class() - find a device by class 1448 * 1449 * @find_class: 3-byte (24-bit) class value to find 1450 * @index: 0 to find the first match, 1 for second, etc. 1451 * @devp: Returns pointer to the device, if found 1452 * @return 0 if found, -ve on error 1453 */ 1454 int dm_pci_find_class(uint find_class, int index, struct udevice **devp); 1455 1456 /** 1457 * struct dm_pci_emul_ops - PCI device emulator operations 1458 */ 1459 struct dm_pci_emul_ops { 1460 /** 1461 * get_devfn(): Check which device and function this emulators 1462 * 1463 * @dev: device to check 1464 * @return the device and function this emulates, or -ve on error 1465 */ 1466 int (*get_devfn)(struct udevice *dev); 1467 /** 1468 * read_config() - Read a PCI configuration value 1469 * 1470 * @dev: Emulated device to read from 1471 * @offset: Byte offset within the device's configuration space 1472 * @valuep: Place to put the returned value 1473 * @size: Access size 1474 * @return 0 if OK, -ve on error 1475 */ 1476 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep, 1477 enum pci_size_t size); 1478 /** 1479 * write_config() - Write a PCI configuration value 1480 * 1481 * @dev: Emulated device to write to 1482 * @offset: Byte offset within the device's configuration space 1483 * @value: Value to write 1484 * @size: Access size 1485 * @return 0 if OK, -ve on error 1486 */ 1487 int (*write_config)(struct udevice *dev, uint offset, ulong value, 1488 enum pci_size_t size); 1489 /** 1490 * read_io() - Read a PCI I/O value 1491 * 1492 * @dev: Emulated device to read from 1493 * @addr: I/O address to read 1494 * @valuep: Place to put the returned value 1495 * @size: Access size 1496 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1497 * other -ve value on error 1498 */ 1499 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, 1500 enum pci_size_t size); 1501 /** 1502 * write_io() - Write a PCI I/O value 1503 * 1504 * @dev: Emulated device to write from 1505 * @addr: I/O address to write 1506 * @value: Value to write 1507 * @size: Access size 1508 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1509 * other -ve value on error 1510 */ 1511 int (*write_io)(struct udevice *dev, unsigned int addr, 1512 ulong value, enum pci_size_t size); 1513 /** 1514 * map_physmem() - Map a device into sandbox memory 1515 * 1516 * @dev: Emulated device to map 1517 * @addr: Memory address, normally corresponding to a PCI BAR. 1518 * The device should have been configured to have a BAR 1519 * at this address. 1520 * @lenp: On entry, the size of the area to map, On exit it is 1521 * updated to the size actually mapped, which may be less 1522 * if the device has less space 1523 * @ptrp: Returns a pointer to the mapped address. The device's 1524 * space can be accessed as @lenp bytes starting here 1525 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1526 * other -ve value on error 1527 */ 1528 int (*map_physmem)(struct udevice *dev, phys_addr_t addr, 1529 unsigned long *lenp, void **ptrp); 1530 /** 1531 * unmap_physmem() - undo a memory mapping 1532 * 1533 * This must be called after map_physmem() to undo the mapping. 1534 * Some devices can use this to check what has been written into 1535 * their mapped memory and perform an operations they require on it. 1536 * In this way, map/unmap can be used as a sort of handshake between 1537 * the emulated device and its users. 1538 * 1539 * @dev: Emuated device to unmap 1540 * @vaddr: Mapped memory address, as passed to map_physmem() 1541 * @len: Size of area mapped, as returned by map_physmem() 1542 * @return 0 if OK, -ve on error 1543 */ 1544 int (*unmap_physmem)(struct udevice *dev, const void *vaddr, 1545 unsigned long len); 1546 }; 1547 1548 /* Get access to a PCI device emulator's operations */ 1549 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) 1550 1551 /** 1552 * sandbox_pci_get_emul() - Get the emulation device for a PCI device 1553 * 1554 * Searches for a suitable emulator for the given PCI bus device 1555 * 1556 * @bus: PCI bus to search 1557 * @find_devfn: PCI device and function address (PCI_DEVFN()) 1558 * @emulp: Returns emulated device if found 1559 * @return 0 if found, -ENODEV if not found 1560 */ 1561 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, 1562 struct udevice **emulp); 1563 1564 #endif /* CONFIG_DM_PCI */ 1565 1566 /** 1567 * PCI_DEVICE - macro used to describe a specific pci device 1568 * @vend: the 16 bit PCI Vendor ID 1569 * @dev: the 16 bit PCI Device ID 1570 * 1571 * This macro is used to create a struct pci_device_id that matches a 1572 * specific device. The subvendor and subdevice fields will be set to 1573 * PCI_ANY_ID. 1574 */ 1575 #define PCI_DEVICE(vend, dev) \ 1576 .vendor = (vend), .device = (dev), \ 1577 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1578 1579 /** 1580 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 1581 * @vend: the 16 bit PCI Vendor ID 1582 * @dev: the 16 bit PCI Device ID 1583 * @subvend: the 16 bit PCI Subvendor ID 1584 * @subdev: the 16 bit PCI Subdevice ID 1585 * 1586 * This macro is used to create a struct pci_device_id that matches a 1587 * specific device with subsystem information. 1588 */ 1589 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1590 .vendor = (vend), .device = (dev), \ 1591 .subvendor = (subvend), .subdevice = (subdev) 1592 1593 /** 1594 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 1595 * @dev_class: the class, subclass, prog-if triple for this device 1596 * @dev_class_mask: the class mask for this device 1597 * 1598 * This macro is used to create a struct pci_device_id that matches a 1599 * specific PCI class. The vendor, device, subvendor, and subdevice 1600 * fields will be set to PCI_ANY_ID. 1601 */ 1602 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ 1603 .class = (dev_class), .class_mask = (dev_class_mask), \ 1604 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1605 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1606 1607 /** 1608 * PCI_VDEVICE - macro used to describe a specific pci device in short form 1609 * @vend: the vendor name 1610 * @dev: the 16 bit PCI Device ID 1611 * 1612 * This macro is used to create a struct pci_device_id that matches a 1613 * specific PCI device. The subvendor, and subdevice fields will be set 1614 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1615 * private data. 1616 */ 1617 1618 #define PCI_VDEVICE(vend, dev) \ 1619 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1620 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1621 1622 /** 1623 * struct pci_driver_entry - Matches a driver to its pci_device_id list 1624 * @driver: Driver to use 1625 * @match: List of match records for this driver, terminated by {} 1626 */ 1627 struct pci_driver_entry { 1628 struct driver *driver; 1629 const struct pci_device_id *match; 1630 }; 1631 1632 #define U_BOOT_PCI_DEVICE(__name, __match) \ 1633 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\ 1634 .driver = llsym(struct driver, __name, driver), \ 1635 .match = __match, \ 1636 } 1637 1638 #endif /* __ASSEMBLY__ */ 1639 #endif /* _PCI_H */ 1640