1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _PCI_H 12 #define _PCI_H 13 14 #define PCI_CFG_SPACE_SIZE 256 15 #define PCI_CFG_SPACE_EXP_SIZE 4096 16 17 /* 18 * Under PCI, each device has 256 bytes of configuration address space, 19 * of which the first 64 bytes are standardized as follows: 20 */ 21 #define PCI_STD_HEADER_SIZEOF 64 22 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 23 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 24 #define PCI_COMMAND 0x04 /* 16 bits */ 25 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 26 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 27 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 28 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 29 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 30 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 31 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 32 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 33 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 34 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 35 36 #define PCI_STATUS 0x06 /* 16 bits */ 37 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 38 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 39 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 40 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 41 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 42 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 43 #define PCI_STATUS_DEVSEL_FAST 0x000 44 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 45 #define PCI_STATUS_DEVSEL_SLOW 0x400 46 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 47 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 48 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 49 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 50 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 51 52 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 53 revision */ 54 #define PCI_REVISION_ID 0x08 /* Revision ID */ 55 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 56 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 57 #define PCI_CLASS_CODE 0x0b /* Device class code */ 58 #define PCI_CLASS_CODE_TOO_OLD 0x00 59 #define PCI_CLASS_CODE_STORAGE 0x01 60 #define PCI_CLASS_CODE_NETWORK 0x02 61 #define PCI_CLASS_CODE_DISPLAY 0x03 62 #define PCI_CLASS_CODE_MULTIMEDIA 0x04 63 #define PCI_CLASS_CODE_MEMORY 0x05 64 #define PCI_CLASS_CODE_BRIDGE 0x06 65 #define PCI_CLASS_CODE_COMM 0x07 66 #define PCI_CLASS_CODE_PERIPHERAL 0x08 67 #define PCI_CLASS_CODE_INPUT 0x09 68 #define PCI_CLASS_CODE_DOCKING 0x0A 69 #define PCI_CLASS_CODE_PROCESSOR 0x0B 70 #define PCI_CLASS_CODE_SERIAL 0x0C 71 #define PCI_CLASS_CODE_WIRELESS 0x0D 72 #define PCI_CLASS_CODE_I2O 0x0E 73 #define PCI_CLASS_CODE_SATELLITE 0x0F 74 #define PCI_CLASS_CODE_CRYPTO 0x10 75 #define PCI_CLASS_CODE_DATA 0x11 76 /* Base Class 0x12 - 0xFE is reserved */ 77 #define PCI_CLASS_CODE_OTHER 0xFF 78 79 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 80 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 81 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 82 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 83 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 84 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 85 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 86 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 87 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 88 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 89 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 90 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 91 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 92 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 93 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 94 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 95 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 96 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 97 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 98 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 99 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 100 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 101 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 102 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 105 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 106 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 107 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 108 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 109 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 110 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 111 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 112 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 113 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 114 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 115 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 116 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 117 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 118 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 119 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 120 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A 121 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 122 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 123 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 124 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 125 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 126 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 127 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 128 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 134 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 135 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 136 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 137 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 138 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 139 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 140 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 141 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 142 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 143 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 144 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 145 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 146 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 147 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 148 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 149 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 150 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 151 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 152 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 153 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 154 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 155 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 156 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 157 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 158 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 159 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 160 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 161 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 162 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 163 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 164 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 165 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 166 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 167 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 168 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 169 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 170 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 171 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 172 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 173 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 174 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 175 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 176 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 177 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 178 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 179 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 180 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 181 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 182 183 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 184 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 185 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 186 #define PCI_HEADER_TYPE_NORMAL 0 187 #define PCI_HEADER_TYPE_BRIDGE 1 188 #define PCI_HEADER_TYPE_CARDBUS 2 189 190 #define PCI_BIST 0x0f /* 8 bits */ 191 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 192 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 193 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 194 195 /* 196 * Base addresses specify locations in memory or I/O space. 197 * Decoded size can be determined by writing a value of 198 * 0xffffffff to the register, and reading it back. Only 199 * 1 bits are decoded. 200 */ 201 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 202 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 203 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 204 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 205 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 206 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 207 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 208 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 209 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 210 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 211 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 212 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 213 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 214 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 215 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 216 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 217 /* bit 1 is reserved if address_space = 1 */ 218 219 /* Header type 0 (normal devices) */ 220 #define PCI_CARDBUS_CIS 0x28 221 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 222 #define PCI_SUBSYSTEM_ID 0x2e 223 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 224 #define PCI_ROM_ADDRESS_ENABLE 0x01 225 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 226 227 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 228 229 /* 0x35-0x3b are reserved */ 230 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 231 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 232 #define PCI_MIN_GNT 0x3e /* 8 bits */ 233 #define PCI_MAX_LAT 0x3f /* 8 bits */ 234 235 #define PCI_INTERRUPT_LINE_DISABLE 0xff 236 237 /* Header type 1 (PCI-to-PCI bridges) */ 238 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 239 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 240 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 241 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 242 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 243 #define PCI_IO_LIMIT 0x1d 244 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 245 #define PCI_IO_RANGE_TYPE_16 0x00 246 #define PCI_IO_RANGE_TYPE_32 0x01 247 #define PCI_IO_RANGE_MASK ~0x0f 248 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 249 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 250 #define PCI_MEMORY_LIMIT 0x22 251 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 252 #define PCI_MEMORY_RANGE_MASK ~0x0f 253 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 254 #define PCI_PREF_MEMORY_LIMIT 0x26 255 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 256 #define PCI_PREF_RANGE_TYPE_32 0x00 257 #define PCI_PREF_RANGE_TYPE_64 0x01 258 #define PCI_PREF_RANGE_MASK ~0x0f 259 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 260 #define PCI_PREF_LIMIT_UPPER32 0x2c 261 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 262 #define PCI_IO_LIMIT_UPPER16 0x32 263 /* 0x34 same as for htype 0 */ 264 /* 0x35-0x3b is reserved */ 265 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 266 /* 0x3c-0x3d are same as for htype 0 */ 267 #define PCI_BRIDGE_CONTROL 0x3e 268 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 269 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 270 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 271 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 272 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 273 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 274 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 275 276 /* From 440ep */ 277 #define PCI_ERREN 0x48 /* Error Enable */ 278 #define PCI_ERRSTS 0x49 /* Error Status */ 279 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ 280 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ 281 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ 282 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ 283 #define PCI_CAPID 0x58 /* Capability Identifier */ 284 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ 285 #define PCI_PMC 0x5A /* Power Management Capabilities */ 286 #define PCI_PMCSR 0x5C /* Power Management Control Status */ 287 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ 288 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ 289 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ 290 291 /* Header type 2 (CardBus bridges) */ 292 #define PCI_CB_CAPABILITY_LIST 0x14 293 /* 0x15 reserved */ 294 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 295 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 296 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 297 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 298 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 299 #define PCI_CB_MEMORY_BASE_0 0x1c 300 #define PCI_CB_MEMORY_LIMIT_0 0x20 301 #define PCI_CB_MEMORY_BASE_1 0x24 302 #define PCI_CB_MEMORY_LIMIT_1 0x28 303 #define PCI_CB_IO_BASE_0 0x2c 304 #define PCI_CB_IO_BASE_0_HI 0x2e 305 #define PCI_CB_IO_LIMIT_0 0x30 306 #define PCI_CB_IO_LIMIT_0_HI 0x32 307 #define PCI_CB_IO_BASE_1 0x34 308 #define PCI_CB_IO_BASE_1_HI 0x36 309 #define PCI_CB_IO_LIMIT_1 0x38 310 #define PCI_CB_IO_LIMIT_1_HI 0x3a 311 #define PCI_CB_IO_RANGE_MASK ~0x03 312 /* 0x3c-0x3d are same as for htype 0 */ 313 #define PCI_CB_BRIDGE_CONTROL 0x3e 314 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 315 #define PCI_CB_BRIDGE_CTL_SERR 0x02 316 #define PCI_CB_BRIDGE_CTL_ISA 0x04 317 #define PCI_CB_BRIDGE_CTL_VGA 0x08 318 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 319 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 320 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 321 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 322 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 323 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 324 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 325 #define PCI_CB_SUBSYSTEM_ID 0x42 326 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 327 /* 0x48-0x7f reserved */ 328 329 /* Capability lists */ 330 331 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 332 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 333 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 334 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 335 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 336 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 337 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 338 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 339 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 340 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 341 #define PCI_CAP_SIZEOF 4 342 343 /* Power Management Registers */ 344 345 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 346 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 347 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 348 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 349 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 350 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 351 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 352 #define PCI_PM_CTRL 4 /* PM control and status register */ 353 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 354 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 355 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 356 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 357 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 358 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 359 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 360 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 361 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 362 #define PCI_PM_SIZEOF 8 363 364 /* AGP registers */ 365 366 #define PCI_AGP_VERSION 2 /* BCD version number */ 367 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 368 #define PCI_AGP_STATUS 4 /* Status register */ 369 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 370 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 371 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 372 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 373 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 374 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 375 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 376 #define PCI_AGP_COMMAND 8 /* Control register */ 377 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 378 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 379 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 380 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 381 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 382 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 383 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 384 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 385 #define PCI_AGP_SIZEOF 12 386 387 /* PCI-X registers */ 388 389 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 390 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 391 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 392 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 393 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 394 395 396 /* Slot Identification */ 397 398 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 399 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 400 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 401 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 402 403 /* Message Signalled Interrupts registers */ 404 405 #define PCI_MSI_FLAGS 2 /* Various flags */ 406 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 407 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 408 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 409 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 410 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 411 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 412 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 413 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 414 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 415 416 #define PCI_MAX_PCI_DEVICES 32 417 #define PCI_MAX_PCI_FUNCTIONS 8 418 419 #define PCI_FIND_CAP_TTL 0x48 420 #define CAP_START_POS 0x40 421 422 /* AER register offsets (relative to the AER Capability base address) */ 423 #define PCI_AER_STATUS 0x08 /* AER Status Register */ 424 #define PCI_AER_MASK 0x0C /* AER Mask Register */ 425 #define PCI_AER_SEVERITY 0x10 /* AER Severity Register */ 426 427 /* Extended Capabilities (PCI-X 2.0 and Express) */ 428 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 429 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 430 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 431 432 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 433 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 434 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 435 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 436 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 437 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 438 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 439 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 440 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 441 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 442 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 443 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 444 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 445 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 446 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 447 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 448 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 449 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 450 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 451 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 452 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 453 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 454 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 455 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 456 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 457 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 458 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 459 460 /* Include the ID list */ 461 462 #include <pci_ids.h> 463 464 #ifndef __ASSEMBLY__ 465 466 #ifdef CONFIG_SYS_PCI_64BIT 467 typedef u64 pci_addr_t; 468 typedef u64 pci_size_t; 469 #else 470 typedef u32 pci_addr_t; 471 typedef u32 pci_size_t; 472 #endif 473 474 struct pci_region { 475 pci_addr_t bus_start; /* Start on the bus */ 476 phys_addr_t phys_start; /* Start in physical address space */ 477 pci_size_t size; /* Size */ 478 unsigned long flags; /* Resource flags */ 479 480 pci_addr_t bus_lower; 481 }; 482 483 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 484 #define PCI_REGION_IO 0x00000001 /* PCI IO space */ 485 #define PCI_REGION_TYPE 0x00000001 486 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 487 488 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 489 #define PCI_REGION_RO 0x00000200 /* Read-only memory */ 490 491 static inline void pci_set_region(struct pci_region *reg, 492 pci_addr_t bus_start, 493 phys_addr_t phys_start, 494 pci_size_t size, 495 unsigned long flags) { 496 reg->bus_start = bus_start; 497 reg->phys_start = phys_start; 498 reg->size = size; 499 reg->flags = flags; 500 } 501 502 typedef int pci_dev_t; 503 504 #define PCI_BUS(d) (((d) >> 16) & 0xff) 505 #define PCI_DEV(d) (((d) >> 11) & 0x1f) 506 #define PCI_FUNC(d) (((d) >> 8) & 0x7) 507 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) 508 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) 509 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) 510 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) 511 #define PCI_VENDEV(v, d) (((v) << 16) | (d)) 512 #define PCI_ANY_ID (~0) 513 514 struct pci_device_id { 515 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 516 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ 517 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ 518 unsigned long driver_data; /* Data private to the driver */ 519 }; 520 521 struct pci_controller; 522 523 struct pci_config_table { 524 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 525 unsigned int class; /* Class ID, or PCI_ANY_ID */ 526 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 527 unsigned int dev; /* Device number, or PCI_ANY_ID */ 528 unsigned int func; /* Function number, or PCI_ANY_ID */ 529 530 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 531 struct pci_config_table *); 532 unsigned long priv[3]; 533 }; 534 535 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 536 struct pci_config_table *); 537 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 538 struct pci_config_table *); 539 540 #define MAX_PCI_REGIONS 7 541 542 #define INDIRECT_TYPE_NO_PCIE_LINK 1 543 544 /* 545 * Structure of a PCI controller (host bridge) 546 * 547 * With driver model this is dev_get_uclass_priv(bus) 548 */ 549 struct pci_controller { 550 #ifdef CONFIG_DM_PCI 551 struct udevice *bus; 552 struct udevice *ctlr; 553 #else 554 struct pci_controller *next; 555 #endif 556 557 int first_busno; 558 int last_busno; 559 560 volatile unsigned int *cfg_addr; 561 volatile unsigned char *cfg_data; 562 563 int indirect_type; 564 565 /* 566 * TODO(sjg@chromium.org): With driver model we use struct 567 * pci_controller for both the controller and any bridge devices 568 * attached to it. But there is only one region list and it is in the 569 * top-level controller. 570 * 571 * This could be changed so that struct pci_controller is only used 572 * for PCI controllers and a separate UCLASS (or perhaps 573 * UCLASS_PCI_GENERIC) is used for bridges. 574 */ 575 struct pci_region regions[MAX_PCI_REGIONS]; 576 int region_count; 577 578 struct pci_config_table *config_table; 579 580 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 581 #ifndef CONFIG_DM_PCI 582 /* Low-level architecture-dependent routines */ 583 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); 584 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); 585 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); 586 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); 587 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); 588 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); 589 #endif 590 591 /* Used by auto config */ 592 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 593 594 /* Used by ppc405 autoconfig*/ 595 struct pci_region *pci_fb; 596 #ifndef CONFIG_DM_PCI 597 int current_busno; 598 599 void *priv_data; 600 #endif 601 }; 602 603 #ifndef CONFIG_DM_PCI 604 static inline void pci_set_ops(struct pci_controller *hose, 605 int (*read_byte)(struct pci_controller*, 606 pci_dev_t, int where, u8 *), 607 int (*read_word)(struct pci_controller*, 608 pci_dev_t, int where, u16 *), 609 int (*read_dword)(struct pci_controller*, 610 pci_dev_t, int where, u32 *), 611 int (*write_byte)(struct pci_controller*, 612 pci_dev_t, int where, u8), 613 int (*write_word)(struct pci_controller*, 614 pci_dev_t, int where, u16), 615 int (*write_dword)(struct pci_controller*, 616 pci_dev_t, int where, u32)) { 617 hose->read_byte = read_byte; 618 hose->read_word = read_word; 619 hose->read_dword = read_dword; 620 hose->write_byte = write_byte; 621 hose->write_word = write_word; 622 hose->write_dword = write_dword; 623 } 624 #endif 625 626 #ifdef CONFIG_PCI_INDIRECT_BRIDGE 627 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); 628 #endif 629 630 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 631 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 632 pci_addr_t addr, unsigned long flags); 633 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 634 phys_addr_t addr, unsigned long flags); 635 636 #define pci_phys_to_bus(dev, addr, flags) \ 637 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 638 #define pci_bus_to_phys(dev, addr, flags) \ 639 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 640 641 #define pci_virt_to_bus(dev, addr, flags) \ 642 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 643 (virt_to_phys(addr)), (flags)) 644 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 645 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 646 (addr), (flags)), \ 647 (len), (map_flags)) 648 649 #define pci_phys_to_mem(dev, addr) \ 650 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 651 #define pci_mem_to_phys(dev, addr) \ 652 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 653 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 654 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 655 656 #define pci_virt_to_mem(dev, addr) \ 657 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 658 #define pci_mem_to_virt(dev, addr, len, map_flags) \ 659 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 660 #define pci_virt_to_io(dev, addr) \ 661 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 662 #define pci_io_to_virt(dev, addr, len, map_flags) \ 663 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 664 665 /* For driver model these are defined in macros in pci_compat.c */ 666 extern int pci_hose_read_config_byte(struct pci_controller *hose, 667 pci_dev_t dev, int where, u8 *val); 668 extern int pci_hose_read_config_word(struct pci_controller *hose, 669 pci_dev_t dev, int where, u16 *val); 670 extern int pci_hose_read_config_dword(struct pci_controller *hose, 671 pci_dev_t dev, int where, u32 *val); 672 extern int pci_hose_write_config_byte(struct pci_controller *hose, 673 pci_dev_t dev, int where, u8 val); 674 extern int pci_hose_write_config_word(struct pci_controller *hose, 675 pci_dev_t dev, int where, u16 val); 676 extern int pci_hose_write_config_dword(struct pci_controller *hose, 677 pci_dev_t dev, int where, u32 val); 678 #endif 679 680 #ifndef CONFIG_DM_PCI 681 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); 682 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); 683 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); 684 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); 685 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); 686 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); 687 #endif 688 689 void pciauto_region_init(struct pci_region *res); 690 void pciauto_region_align(struct pci_region *res, pci_size_t size); 691 void pciauto_config_init(struct pci_controller *hose); 692 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 693 pci_addr_t *bar); 694 695 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 696 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 697 pci_dev_t dev, int where, u8 *val); 698 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 699 pci_dev_t dev, int where, u16 *val); 700 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 701 pci_dev_t dev, int where, u8 val); 702 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 703 pci_dev_t dev, int where, u16 val); 704 705 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 706 extern void pci_register_hose(struct pci_controller* hose); 707 extern struct pci_controller* pci_bus_to_hose(int bus); 708 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 709 extern struct pci_controller *pci_get_hose_head(void); 710 711 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); 712 extern int pci_hose_scan(struct pci_controller *hose); 713 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 714 715 extern void pciauto_setup_device(struct pci_controller *hose, 716 pci_dev_t dev, int bars_num, 717 struct pci_region *mem, 718 struct pci_region *prefetch, 719 struct pci_region *io); 720 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 721 pci_dev_t dev, int sub_bus); 722 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 723 pci_dev_t dev, int sub_bus); 724 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 725 726 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 727 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 728 pci_dev_t pci_find_class(unsigned int find_class, int index); 729 730 extern int pci_hose_config_device(struct pci_controller *hose, 731 pci_dev_t dev, 732 unsigned long io, 733 pci_addr_t mem, 734 unsigned long command); 735 736 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 737 int cap); 738 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 739 u8 hdr_type); 740 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 741 int cap); 742 743 int pci_find_next_ext_capability(struct pci_controller *hose, 744 pci_dev_t dev, int start, int cap); 745 int pci_hose_find_ext_capability(struct pci_controller *hose, 746 pci_dev_t dev, int cap); 747 748 #ifdef CONFIG_PCI_FIXUP_DEV 749 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 750 unsigned short vendor, 751 unsigned short device, 752 unsigned short class); 753 #endif 754 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ 755 756 const char * pci_class_str(u8 class); 757 int pci_last_busno(void); 758 759 #ifdef CONFIG_MPC85xx 760 extern void pci_mpc85xx_init (struct pci_controller *hose); 761 #endif 762 763 #ifdef CONFIG_PCIE_IMX 764 extern void imx_pcie_remove(void); 765 #endif 766 767 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 768 /** 769 * pci_write_bar32() - Write the address of a BAR including control bits 770 * 771 * This writes a raw address (with control bits) to a bar. This can be used 772 * with devices which require hard-coded addresses, not part of the normal 773 * PCI enumeration process. 774 * 775 * @hose: PCI hose to use 776 * @dev: PCI device to update 777 * @barnum: BAR number (0-5) 778 * @addr: BAR address with control bits 779 */ 780 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, 781 u32 addr); 782 783 /** 784 * pci_read_bar32() - read the address of a bar 785 * 786 * @hose: PCI hose to use 787 * @dev: PCI device to inspect 788 * @barnum: BAR number (0-5) 789 * @return address of the bar, masking out any control bits 790 * */ 791 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); 792 793 /** 794 * pci_hose_find_devices() - Find devices by vendor/device ID 795 * 796 * @hose: PCI hose to search 797 * @busnum: Bus number to search 798 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 799 * @indexp: Pointer to device index to find. To find the first matching 800 * device, pass 0; to find the second, pass 1, etc. This 801 * parameter is decremented for each non-matching device so 802 * can be called repeatedly. 803 */ 804 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, 805 struct pci_device_id *ids, int *indexp); 806 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ 807 808 /* Access sizes for PCI reads and writes */ 809 enum pci_size_t { 810 PCI_SIZE_8, 811 PCI_SIZE_16, 812 PCI_SIZE_32, 813 }; 814 815 struct udevice; 816 817 #ifdef CONFIG_DM_PCI 818 /** 819 * struct pci_child_platdata - information stored about each PCI device 820 * 821 * Every device on a PCI bus has this per-child data. 822 * 823 * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a 824 * PCI bus (i.e. UCLASS_PCI) 825 * 826 * @devfn: Encoded device and function index - see PCI_DEVFN() 827 * @vendor: PCI vendor ID (see pci_ids.h) 828 * @device: PCI device ID (see pci_ids.h) 829 * @class: PCI class, 3 bytes: (base, sub, prog-if) 830 */ 831 struct pci_child_platdata { 832 int devfn; 833 unsigned short vendor; 834 unsigned short device; 835 unsigned int class; 836 }; 837 838 /* PCI bus operations */ 839 struct dm_pci_ops { 840 /** 841 * read_config() - Read a PCI configuration value 842 * 843 * PCI buses must support reading and writing configuration values 844 * so that the bus can be scanned and its devices configured. 845 * 846 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. 847 * If bridges exist it is possible to use the top-level bus to 848 * access a sub-bus. In that case @bus will be the top-level bus 849 * and PCI_BUS(bdf) will be a different (higher) value 850 * 851 * @bus: Bus to read from 852 * @bdf: Bus, device and function to read 853 * @offset: Byte offset within the device's configuration space 854 * @valuep: Place to put the returned value 855 * @size: Access size 856 * @return 0 if OK, -ve on error 857 */ 858 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 859 ulong *valuep, enum pci_size_t size); 860 /** 861 * write_config() - Write a PCI configuration value 862 * 863 * @bus: Bus to write to 864 * @bdf: Bus, device and function to write 865 * @offset: Byte offset within the device's configuration space 866 * @value: Value to write 867 * @size: Access size 868 * @return 0 if OK, -ve on error 869 */ 870 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 871 ulong value, enum pci_size_t size); 872 }; 873 874 /* Get access to a PCI bus' operations */ 875 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) 876 877 /** 878 * dm_pci_get_bdf() - Get the BDF value for a device 879 * 880 * @dev: Device to check 881 * @return bus/device/function value (see PCI_BDF()) 882 */ 883 pci_dev_t dm_pci_get_bdf(struct udevice *dev); 884 885 /** 886 * pci_bind_bus_devices() - scan a PCI bus and bind devices 887 * 888 * Scan a PCI bus looking for devices. Bind each one that is found. If 889 * devices are already bound that match the scanned devices, just update the 890 * child data so that the device can be used correctly (this happens when 891 * the device tree describes devices we expect to see on the bus). 892 * 893 * Devices that are bound in this way will use a generic PCI driver which 894 * does nothing. The device can still be accessed but will not provide any 895 * driver interface. 896 * 897 * @bus: Bus containing devices to bind 898 * @return 0 if OK, -ve on error 899 */ 900 int pci_bind_bus_devices(struct udevice *bus); 901 902 /** 903 * pci_auto_config_devices() - configure bus devices ready for use 904 * 905 * This works through all devices on a bus by scanning the driver model 906 * data structures (normally these have been set up by pci_bind_bus_devices() 907 * earlier). 908 * 909 * Space is allocated for each PCI base address register (BAR) so that the 910 * devices are mapped into memory and I/O space ready for use. 911 * 912 * @bus: Bus containing devices to bind 913 * @return 0 if OK, -ve on error 914 */ 915 int pci_auto_config_devices(struct udevice *bus); 916 917 /** 918 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address 919 * 920 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 921 * @devp: Returns the device for this address, if found 922 * @return 0 if OK, -ENODEV if not found 923 */ 924 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); 925 926 /** 927 * pci_bus_find_devfn() - Find a device on a bus 928 * 929 * @find_devfn: PCI device address (device and function only) 930 * @devp: Returns the device for this address, if found 931 * @return 0 if OK, -ENODEV if not found 932 */ 933 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 934 struct udevice **devp); 935 936 /** 937 * pci_find_first_device() - return the first available PCI device 938 * 939 * This function and pci_find_first_device() allow iteration through all 940 * available PCI devices on all buses. Assuming there are any, this will 941 * return the first one. 942 * 943 * @devp: Set to the first available device, or NULL if no more are left 944 * or we got an error 945 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 946 */ 947 int pci_find_first_device(struct udevice **devp); 948 949 /** 950 * pci_find_next_device() - return the next available PCI device 951 * 952 * Finds the next available PCI device after the one supplied, or sets @devp 953 * to NULL if there are no more. 954 * 955 * @devp: On entry, the last device returned. Set to the next available 956 * device, or NULL if no more are left or we got an error 957 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 958 */ 959 int pci_find_next_device(struct udevice **devp); 960 961 /** 962 * pci_get_ff() - Returns a mask for the given access size 963 * 964 * @size: Access size 965 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for 966 * PCI_SIZE_32 967 */ 968 int pci_get_ff(enum pci_size_t size); 969 970 /** 971 * pci_bus_find_devices () - Find devices on a bus 972 * 973 * @bus: Bus to search 974 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 975 * @indexp: Pointer to device index to find. To find the first matching 976 * device, pass 0; to find the second, pass 1, etc. This 977 * parameter is decremented for each non-matching device so 978 * can be called repeatedly. 979 * @devp: Returns matching device if found 980 * @return 0 if found, -ENODEV if not 981 */ 982 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 983 int *indexp, struct udevice **devp); 984 985 /** 986 * pci_find_device_id() - Find a device on any bus 987 * 988 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 989 * @index: Index number of device to find, 0 for the first match, 1 for 990 * the second, etc. 991 * @devp: Returns matching device if found 992 * @return 0 if found, -ENODEV if not 993 */ 994 int pci_find_device_id(struct pci_device_id *ids, int index, 995 struct udevice **devp); 996 997 /** 998 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices 999 * 1000 * This probes the given bus which causes it to be scanned for devices. The 1001 * devices will be bound but not probed. 1002 * 1003 * @hose specifies the PCI hose that will be used for the scan. This is 1004 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is 1005 * in @bdf, and is a subordinate bus reachable from @hose. 1006 * 1007 * @hose: PCI hose to scan 1008 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) 1009 * @return 0 if OK, -ve on error 1010 */ 1011 int dm_pci_hose_probe_bus(struct udevice *bus); 1012 1013 /** 1014 * pci_bus_read_config() - Read a configuration value from a device 1015 * 1016 * TODO(sjg@chromium.org): We should be able to pass just a device and have 1017 * it do the right thing. It would be good to have that function also. 1018 * 1019 * @bus: Bus to read from 1020 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1021 * @offset: Register offset to read 1022 * @valuep: Place to put the returned value 1023 * @size: Access size 1024 * @return 0 if OK, -ve on error 1025 */ 1026 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 1027 unsigned long *valuep, enum pci_size_t size); 1028 1029 /** 1030 * pci_bus_write_config() - Write a configuration value to a device 1031 * 1032 * @bus: Bus to write from 1033 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1034 * @offset: Register offset to write 1035 * @value: Value to write 1036 * @size: Access size 1037 * @return 0 if OK, -ve on error 1038 */ 1039 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 1040 unsigned long value, enum pci_size_t size); 1041 1042 /** 1043 * pci_bus_clrset_config32() - Update a configuration value for a device 1044 * 1045 * The register at @offset is updated to (oldvalue & ~clr) | set. 1046 * 1047 * @bus: Bus to access 1048 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1049 * @offset: Register offset to update 1050 * @clr: Bits to clear 1051 * @set: Bits to set 1052 * @return 0 if OK, -ve on error 1053 */ 1054 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, 1055 u32 clr, u32 set); 1056 1057 /** 1058 * Driver model PCI config access functions. Use these in preference to others 1059 * when you have a valid device 1060 */ 1061 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, 1062 enum pci_size_t size); 1063 1064 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep); 1065 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep); 1066 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep); 1067 1068 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, 1069 enum pci_size_t size); 1070 1071 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value); 1072 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value); 1073 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); 1074 1075 /** 1076 * These permit convenient read/modify/write on PCI configuration. The 1077 * register is updated to (oldvalue & ~clr) | set. 1078 */ 1079 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set); 1080 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set); 1081 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set); 1082 1083 /* 1084 * The following functions provide access to the above without needing the 1085 * size parameter. We are trying to encourage the use of the 8/16/32-style 1086 * functions, rather than byte/word/dword. But both are supported. 1087 */ 1088 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); 1089 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); 1090 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); 1091 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); 1092 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); 1093 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); 1094 1095 #ifdef CONFIG_DM_PCI_COMPAT 1096 /* Compatibility with old naming */ 1097 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, 1098 u32 value) 1099 { 1100 return pci_write_config32(pcidev, offset, value); 1101 } 1102 1103 /* Compatibility with old naming */ 1104 static inline int pci_write_config_word(pci_dev_t pcidev, int offset, 1105 u16 value) 1106 { 1107 return pci_write_config16(pcidev, offset, value); 1108 } 1109 1110 /* Compatibility with old naming */ 1111 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, 1112 u8 value) 1113 { 1114 return pci_write_config8(pcidev, offset, value); 1115 } 1116 1117 /* Compatibility with old naming */ 1118 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, 1119 u32 *valuep) 1120 { 1121 return pci_read_config32(pcidev, offset, valuep); 1122 } 1123 1124 /* Compatibility with old naming */ 1125 static inline int pci_read_config_word(pci_dev_t pcidev, int offset, 1126 u16 *valuep) 1127 { 1128 return pci_read_config16(pcidev, offset, valuep); 1129 } 1130 1131 /* Compatibility with old naming */ 1132 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, 1133 u8 *valuep) 1134 { 1135 return pci_read_config8(pcidev, offset, valuep); 1136 } 1137 #endif /* CONFIG_DM_PCI_COMPAT */ 1138 1139 /** 1140 * dm_pciauto_config_device() - configure a device ready for use 1141 * 1142 * Space is allocated for each PCI base address register (BAR) so that the 1143 * devices are mapped into memory and I/O space ready for use. 1144 * 1145 * @dev: Device to configure 1146 * @return 0 if OK, -ve on error 1147 */ 1148 int dm_pciauto_config_device(struct udevice *dev); 1149 1150 /** 1151 * pci_conv_32_to_size() - convert a 32-bit read value to the given size 1152 * 1153 * Some PCI buses must always perform 32-bit reads. The data must then be 1154 * shifted and masked to reflect the required access size and offset. This 1155 * function performs this transformation. 1156 * 1157 * @value: Value to transform (32-bit value read from @offset & ~3) 1158 * @offset: Register offset that was read 1159 * @size: Required size of the result 1160 * @return the value that would have been obtained if the read had been 1161 * performed at the given offset with the correct size 1162 */ 1163 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); 1164 1165 /** 1166 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write 1167 * 1168 * Some PCI buses must always perform 32-bit writes. To emulate a smaller 1169 * write the old 32-bit data must be read, updated with the required new data 1170 * and written back as a 32-bit value. This function performs the 1171 * transformation from the old value to the new value. 1172 * 1173 * @value: Value to transform (32-bit value read from @offset & ~3) 1174 * @offset: Register offset that should be written 1175 * @size: Required size of the write 1176 * @return the value that should be written as a 32-bit access to @offset & ~3. 1177 */ 1178 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, 1179 enum pci_size_t size); 1180 1181 /** 1182 * pci_get_controller() - obtain the controller to use for a bus 1183 * 1184 * @dev: Device to check 1185 * @return pointer to the controller device for this bus 1186 */ 1187 struct udevice *pci_get_controller(struct udevice *dev); 1188 1189 /** 1190 * pci_get_regions() - obtain pointers to all the region types 1191 * 1192 * @dev: Device to check 1193 * @iop: Returns a pointer to the I/O region, or NULL if none 1194 * @memp: Returns a pointer to the memory region, or NULL if none 1195 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none 1196 * @return the number of non-NULL regions returned, normally 3 1197 */ 1198 int pci_get_regions(struct udevice *dev, struct pci_region **iop, 1199 struct pci_region **memp, struct pci_region **prefp); 1200 1201 /** 1202 * pci_aer_dump() - dump AER (Advanced Error Reporting) information for a PCIe device 1203 * 1204 * @udev: PCI device to dump AER information 1205 * @dev: PCI device and function address 1206 * @return: 0 if successful, negative error code on failure 1207 */ 1208 int pci_aer_dump(struct udevice *udev, pci_dev_t dev); 1209 1210 /** 1211 * dm_pci_write_bar32() - Write the address of a BAR 1212 * 1213 * This writes a raw address to a bar 1214 * 1215 * @dev: PCI device to update 1216 * @barnum: BAR number (0-5) 1217 * @addr: BAR address 1218 */ 1219 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); 1220 1221 /** 1222 * dm_pci_read_bar32() - read a base address register from a device 1223 * 1224 * @dev: Device to check 1225 * @barnum: Bar number to read (numbered from 0) 1226 * @return: value of BAR 1227 */ 1228 u32 dm_pci_read_bar32(struct udevice *dev, int barnum); 1229 1230 /** 1231 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address 1232 * 1233 * @dev: Device containing the PCI address 1234 * @addr: PCI address to convert 1235 * @flags: Flags for the region type (PCI_REGION_...) 1236 * @return physical address corresponding to that PCI bus address 1237 */ 1238 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, 1239 unsigned long flags); 1240 1241 /** 1242 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address 1243 * 1244 * @dev: Device containing the bus address 1245 * @addr: Physical address to convert 1246 * @flags: Flags for the region type (PCI_REGION_...) 1247 * @return PCI bus address corresponding to that physical address 1248 */ 1249 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, 1250 unsigned long flags); 1251 1252 /** 1253 * dm_pci_map_bar() - get a virtual address associated with a BAR region 1254 * 1255 * Looks up a base address register and finds the physical memory address 1256 * that corresponds to it 1257 * 1258 * @dev: Device to check 1259 * @bar: Bar number to read (numbered from 0) 1260 * @flags: Flags for the region type (PCI_REGION_...) 1261 * @return: pointer to the virtual address to use 1262 */ 1263 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); 1264 1265 /** 1266 * dm_pci_find_next_capability() - find a capability starting from an offset 1267 * 1268 * Tell if a device supports a given PCI capability. Returns the 1269 * address of the requested capability structure within the device's 1270 * PCI configuration space or 0 in case the device does not support it. 1271 * 1272 * Possible values for @cap: 1273 * 1274 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1275 * %PCI_CAP_ID_PCIX PCI-X 1276 * %PCI_CAP_ID_EXP PCI Express 1277 * %PCI_CAP_ID_MSIX MSI-X 1278 * 1279 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1280 * 1281 * @dev: PCI device to query 1282 * @start: offset to start from 1283 * @cap: capability code 1284 * @return: capability address or 0 if not supported 1285 */ 1286 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap); 1287 1288 /** 1289 * dm_pci_find_capability() - find a capability 1290 * 1291 * Tell if a device supports a given PCI capability. Returns the 1292 * address of the requested capability structure within the device's 1293 * PCI configuration space or 0 in case the device does not support it. 1294 * 1295 * Possible values for @cap: 1296 * 1297 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1298 * %PCI_CAP_ID_PCIX PCI-X 1299 * %PCI_CAP_ID_EXP PCI Express 1300 * %PCI_CAP_ID_MSIX MSI-X 1301 * 1302 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1303 * 1304 * @dev: PCI device to query 1305 * @cap: capability code 1306 * @return: capability address or 0 if not supported 1307 */ 1308 int dm_pci_find_capability(struct udevice *dev, int cap); 1309 1310 /** 1311 * dm_pci_find_next_ext_capability() - find an extended capability 1312 * starting from an offset 1313 * 1314 * Tell if a device supports a given PCI express extended capability. 1315 * Returns the address of the requested extended capability structure 1316 * within the device's PCI configuration space or 0 in case the device 1317 * does not support it. 1318 * 1319 * Possible values for @cap: 1320 * 1321 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1322 * %PCI_EXT_CAP_ID_VC Virtual Channel 1323 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1324 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1325 * 1326 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1327 * 1328 * @dev: PCI device to query 1329 * @start: offset to start from 1330 * @cap: extended capability code 1331 * @return: extended capability address or 0 if not supported 1332 */ 1333 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap); 1334 1335 /** 1336 * dm_pci_find_ext_capability() - find an extended capability 1337 * 1338 * Tell if a device supports a given PCI express extended capability. 1339 * Returns the address of the requested extended capability structure 1340 * within the device's PCI configuration space or 0 in case the device 1341 * does not support it. 1342 * 1343 * Possible values for @cap: 1344 * 1345 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1346 * %PCI_EXT_CAP_ID_VC Virtual Channel 1347 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1348 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1349 * 1350 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1351 * 1352 * @dev: PCI device to query 1353 * @cap: extended capability code 1354 * @return: extended capability address or 0 if not supported 1355 */ 1356 int dm_pci_find_ext_capability(struct udevice *dev, int cap); 1357 1358 #define dm_pci_virt_to_bus(dev, addr, flags) \ 1359 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) 1360 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 1361 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \ 1362 (len), (map_flags)) 1363 1364 #define dm_pci_phys_to_mem(dev, addr) \ 1365 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 1366 #define dm_pci_mem_to_phys(dev, addr) \ 1367 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 1368 #define dm_pci_phys_to_io(dev, addr) \ 1369 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 1370 #define dm_pci_io_to_phys(dev, addr) \ 1371 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 1372 1373 #define dm_pci_virt_to_mem(dev, addr) \ 1374 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 1375 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ 1376 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 1377 #define dm_pci_virt_to_io(dev, addr) \ 1378 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 1379 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \ 1380 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 1381 1382 /** 1383 * dm_pci_find_device() - find a device by vendor/device ID 1384 * 1385 * @vendor: Vendor ID 1386 * @device: Device ID 1387 * @index: 0 to find the first match, 1 for second, etc. 1388 * @devp: Returns pointer to the device, if found 1389 * @return 0 if found, -ve on error 1390 */ 1391 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, 1392 struct udevice **devp); 1393 1394 /** 1395 * dm_pci_find_class() - find a device by class 1396 * 1397 * @find_class: 3-byte (24-bit) class value to find 1398 * @index: 0 to find the first match, 1 for second, etc. 1399 * @devp: Returns pointer to the device, if found 1400 * @return 0 if found, -ve on error 1401 */ 1402 int dm_pci_find_class(uint find_class, int index, struct udevice **devp); 1403 1404 /** 1405 * struct dm_pci_emul_ops - PCI device emulator operations 1406 */ 1407 struct dm_pci_emul_ops { 1408 /** 1409 * get_devfn(): Check which device and function this emulators 1410 * 1411 * @dev: device to check 1412 * @return the device and function this emulates, or -ve on error 1413 */ 1414 int (*get_devfn)(struct udevice *dev); 1415 /** 1416 * read_config() - Read a PCI configuration value 1417 * 1418 * @dev: Emulated device to read from 1419 * @offset: Byte offset within the device's configuration space 1420 * @valuep: Place to put the returned value 1421 * @size: Access size 1422 * @return 0 if OK, -ve on error 1423 */ 1424 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep, 1425 enum pci_size_t size); 1426 /** 1427 * write_config() - Write a PCI configuration value 1428 * 1429 * @dev: Emulated device to write to 1430 * @offset: Byte offset within the device's configuration space 1431 * @value: Value to write 1432 * @size: Access size 1433 * @return 0 if OK, -ve on error 1434 */ 1435 int (*write_config)(struct udevice *dev, uint offset, ulong value, 1436 enum pci_size_t size); 1437 /** 1438 * read_io() - Read a PCI I/O value 1439 * 1440 * @dev: Emulated device to read from 1441 * @addr: I/O address to read 1442 * @valuep: Place to put the returned value 1443 * @size: Access size 1444 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1445 * other -ve value on error 1446 */ 1447 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, 1448 enum pci_size_t size); 1449 /** 1450 * write_io() - Write a PCI I/O value 1451 * 1452 * @dev: Emulated device to write from 1453 * @addr: I/O address to write 1454 * @value: Value to write 1455 * @size: Access size 1456 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1457 * other -ve value on error 1458 */ 1459 int (*write_io)(struct udevice *dev, unsigned int addr, 1460 ulong value, enum pci_size_t size); 1461 /** 1462 * map_physmem() - Map a device into sandbox memory 1463 * 1464 * @dev: Emulated device to map 1465 * @addr: Memory address, normally corresponding to a PCI BAR. 1466 * The device should have been configured to have a BAR 1467 * at this address. 1468 * @lenp: On entry, the size of the area to map, On exit it is 1469 * updated to the size actually mapped, which may be less 1470 * if the device has less space 1471 * @ptrp: Returns a pointer to the mapped address. The device's 1472 * space can be accessed as @lenp bytes starting here 1473 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1474 * other -ve value on error 1475 */ 1476 int (*map_physmem)(struct udevice *dev, phys_addr_t addr, 1477 unsigned long *lenp, void **ptrp); 1478 /** 1479 * unmap_physmem() - undo a memory mapping 1480 * 1481 * This must be called after map_physmem() to undo the mapping. 1482 * Some devices can use this to check what has been written into 1483 * their mapped memory and perform an operations they require on it. 1484 * In this way, map/unmap can be used as a sort of handshake between 1485 * the emulated device and its users. 1486 * 1487 * @dev: Emuated device to unmap 1488 * @vaddr: Mapped memory address, as passed to map_physmem() 1489 * @len: Size of area mapped, as returned by map_physmem() 1490 * @return 0 if OK, -ve on error 1491 */ 1492 int (*unmap_physmem)(struct udevice *dev, const void *vaddr, 1493 unsigned long len); 1494 }; 1495 1496 /* Get access to a PCI device emulator's operations */ 1497 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) 1498 1499 /** 1500 * sandbox_pci_get_emul() - Get the emulation device for a PCI device 1501 * 1502 * Searches for a suitable emulator for the given PCI bus device 1503 * 1504 * @bus: PCI bus to search 1505 * @find_devfn: PCI device and function address (PCI_DEVFN()) 1506 * @emulp: Returns emulated device if found 1507 * @return 0 if found, -ENODEV if not found 1508 */ 1509 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, 1510 struct udevice **emulp); 1511 1512 #endif /* CONFIG_DM_PCI */ 1513 1514 /** 1515 * PCI_DEVICE - macro used to describe a specific pci device 1516 * @vend: the 16 bit PCI Vendor ID 1517 * @dev: the 16 bit PCI Device ID 1518 * 1519 * This macro is used to create a struct pci_device_id that matches a 1520 * specific device. The subvendor and subdevice fields will be set to 1521 * PCI_ANY_ID. 1522 */ 1523 #define PCI_DEVICE(vend, dev) \ 1524 .vendor = (vend), .device = (dev), \ 1525 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1526 1527 /** 1528 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 1529 * @vend: the 16 bit PCI Vendor ID 1530 * @dev: the 16 bit PCI Device ID 1531 * @subvend: the 16 bit PCI Subvendor ID 1532 * @subdev: the 16 bit PCI Subdevice ID 1533 * 1534 * This macro is used to create a struct pci_device_id that matches a 1535 * specific device with subsystem information. 1536 */ 1537 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1538 .vendor = (vend), .device = (dev), \ 1539 .subvendor = (subvend), .subdevice = (subdev) 1540 1541 /** 1542 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 1543 * @dev_class: the class, subclass, prog-if triple for this device 1544 * @dev_class_mask: the class mask for this device 1545 * 1546 * This macro is used to create a struct pci_device_id that matches a 1547 * specific PCI class. The vendor, device, subvendor, and subdevice 1548 * fields will be set to PCI_ANY_ID. 1549 */ 1550 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ 1551 .class = (dev_class), .class_mask = (dev_class_mask), \ 1552 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1553 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1554 1555 /** 1556 * PCI_VDEVICE - macro used to describe a specific pci device in short form 1557 * @vend: the vendor name 1558 * @dev: the 16 bit PCI Device ID 1559 * 1560 * This macro is used to create a struct pci_device_id that matches a 1561 * specific PCI device. The subvendor, and subdevice fields will be set 1562 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1563 * private data. 1564 */ 1565 1566 #define PCI_VDEVICE(vend, dev) \ 1567 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1568 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1569 1570 /** 1571 * struct pci_driver_entry - Matches a driver to its pci_device_id list 1572 * @driver: Driver to use 1573 * @match: List of match records for this driver, terminated by {} 1574 */ 1575 struct pci_driver_entry { 1576 struct driver *driver; 1577 const struct pci_device_id *match; 1578 }; 1579 1580 #define U_BOOT_PCI_DEVICE(__name, __match) \ 1581 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\ 1582 .driver = llsym(struct driver, __name, driver), \ 1583 .match = __match, \ 1584 } 1585 1586 #endif /* __ASSEMBLY__ */ 1587 #endif /* _PCI_H */ 1588