1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _PCI_H 12 #define _PCI_H 13 14 #define PCI_CFG_SPACE_SIZE 256 15 #define PCI_CFG_SPACE_EXP_SIZE 4096 16 17 /* 18 * Under PCI, each device has 256 bytes of configuration address space, 19 * of which the first 64 bytes are standardized as follows: 20 */ 21 #define PCI_STD_HEADER_SIZEOF 64 22 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 23 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 24 #define PCI_COMMAND 0x04 /* 16 bits */ 25 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 26 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 27 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 28 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 29 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 30 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 31 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 32 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 33 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 34 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 35 36 #define PCI_STATUS 0x06 /* 16 bits */ 37 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 38 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 39 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 40 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 41 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 42 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 43 #define PCI_STATUS_DEVSEL_FAST 0x000 44 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 45 #define PCI_STATUS_DEVSEL_SLOW 0x400 46 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 47 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 48 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 49 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 50 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 51 52 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 53 revision */ 54 #define PCI_REVISION_ID 0x08 /* Revision ID */ 55 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 56 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 57 #define PCI_CLASS_CODE 0x0b /* Device class code */ 58 #define PCI_CLASS_CODE_TOO_OLD 0x00 59 #define PCI_CLASS_CODE_STORAGE 0x01 60 #define PCI_CLASS_CODE_NETWORK 0x02 61 #define PCI_CLASS_CODE_DISPLAY 0x03 62 #define PCI_CLASS_CODE_MULTIMEDIA 0x04 63 #define PCI_CLASS_CODE_MEMORY 0x05 64 #define PCI_CLASS_CODE_BRIDGE 0x06 65 #define PCI_CLASS_CODE_COMM 0x07 66 #define PCI_CLASS_CODE_PERIPHERAL 0x08 67 #define PCI_CLASS_CODE_INPUT 0x09 68 #define PCI_CLASS_CODE_DOCKING 0x0A 69 #define PCI_CLASS_CODE_PROCESSOR 0x0B 70 #define PCI_CLASS_CODE_SERIAL 0x0C 71 #define PCI_CLASS_CODE_WIRELESS 0x0D 72 #define PCI_CLASS_CODE_I2O 0x0E 73 #define PCI_CLASS_CODE_SATELLITE 0x0F 74 #define PCI_CLASS_CODE_CRYPTO 0x10 75 #define PCI_CLASS_CODE_DATA 0x11 76 /* Base Class 0x12 - 0xFE is reserved */ 77 #define PCI_CLASS_CODE_OTHER 0xFF 78 79 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 80 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 81 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 82 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 83 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 84 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 85 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 86 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 87 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 88 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 89 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 90 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 91 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 92 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 93 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 94 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 95 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 96 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 97 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 98 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 99 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 100 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 101 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 102 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 105 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 106 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 107 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 108 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 109 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 110 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 111 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 112 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 113 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 114 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 115 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 116 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 117 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 118 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 119 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 120 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A 121 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 122 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 123 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 124 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 125 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 126 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 127 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 128 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 134 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 135 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 136 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 137 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 138 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 139 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 140 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 141 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 142 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 143 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 144 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 145 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 146 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 147 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 148 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 149 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 150 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 151 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 152 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 153 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 154 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 155 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 156 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 157 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 158 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 159 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 160 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 161 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 162 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 163 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 164 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 165 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 166 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 167 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 168 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 169 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 170 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 171 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 172 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 173 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 174 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 175 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 176 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 177 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 178 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 179 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 180 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 181 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 182 183 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 184 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 185 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 186 #define PCI_HEADER_TYPE_NORMAL 0 187 #define PCI_HEADER_TYPE_BRIDGE 1 188 #define PCI_HEADER_TYPE_CARDBUS 2 189 190 #define PCI_BIST 0x0f /* 8 bits */ 191 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 192 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 193 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 194 195 /* 196 * Base addresses specify locations in memory or I/O space. 197 * Decoded size can be determined by writing a value of 198 * 0xffffffff to the register, and reading it back. Only 199 * 1 bits are decoded. 200 */ 201 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 202 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 203 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 204 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 205 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 206 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 207 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 208 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 209 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 210 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 211 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 212 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 213 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 214 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 215 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 216 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 217 /* bit 1 is reserved if address_space = 1 */ 218 219 /* Header type 0 (normal devices) */ 220 #define PCI_CARDBUS_CIS 0x28 221 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 222 #define PCI_SUBSYSTEM_ID 0x2e 223 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 224 #define PCI_ROM_ADDRESS_ENABLE 0x01 225 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 226 227 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 228 229 /* 0x35-0x3b are reserved */ 230 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 231 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 232 #define PCI_MIN_GNT 0x3e /* 8 bits */ 233 #define PCI_MAX_LAT 0x3f /* 8 bits */ 234 235 #define PCI_INTERRUPT_LINE_DISABLE 0xff 236 237 /* Header type 1 (PCI-to-PCI bridges) */ 238 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 239 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 240 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 241 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 242 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 243 #define PCI_IO_LIMIT 0x1d 244 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 245 #define PCI_IO_RANGE_TYPE_16 0x00 246 #define PCI_IO_RANGE_TYPE_32 0x01 247 #define PCI_IO_RANGE_MASK ~0x0f 248 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 249 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 250 #define PCI_MEMORY_LIMIT 0x22 251 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 252 #define PCI_MEMORY_RANGE_MASK ~0x0f 253 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 254 #define PCI_PREF_MEMORY_LIMIT 0x26 255 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 256 #define PCI_PREF_RANGE_TYPE_32 0x00 257 #define PCI_PREF_RANGE_TYPE_64 0x01 258 #define PCI_PREF_RANGE_MASK ~0x0f 259 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 260 #define PCI_PREF_LIMIT_UPPER32 0x2c 261 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 262 #define PCI_IO_LIMIT_UPPER16 0x32 263 /* 0x34 same as for htype 0 */ 264 /* 0x35-0x3b is reserved */ 265 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 266 /* 0x3c-0x3d are same as for htype 0 */ 267 #define PCI_BRIDGE_CONTROL 0x3e 268 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 269 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 270 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 271 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 272 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 273 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 274 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 275 276 /* From 440ep */ 277 #define PCI_ERREN 0x48 /* Error Enable */ 278 #define PCI_ERRSTS 0x49 /* Error Status */ 279 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ 280 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ 281 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ 282 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ 283 #define PCI_CAPID 0x58 /* Capability Identifier */ 284 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ 285 #define PCI_PMC 0x5A /* Power Management Capabilities */ 286 #define PCI_PMCSR 0x5C /* Power Management Control Status */ 287 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ 288 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ 289 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ 290 291 /* Header type 2 (CardBus bridges) */ 292 #define PCI_CB_CAPABILITY_LIST 0x14 293 /* 0x15 reserved */ 294 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 295 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 296 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 297 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 298 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 299 #define PCI_CB_MEMORY_BASE_0 0x1c 300 #define PCI_CB_MEMORY_LIMIT_0 0x20 301 #define PCI_CB_MEMORY_BASE_1 0x24 302 #define PCI_CB_MEMORY_LIMIT_1 0x28 303 #define PCI_CB_IO_BASE_0 0x2c 304 #define PCI_CB_IO_BASE_0_HI 0x2e 305 #define PCI_CB_IO_LIMIT_0 0x30 306 #define PCI_CB_IO_LIMIT_0_HI 0x32 307 #define PCI_CB_IO_BASE_1 0x34 308 #define PCI_CB_IO_BASE_1_HI 0x36 309 #define PCI_CB_IO_LIMIT_1 0x38 310 #define PCI_CB_IO_LIMIT_1_HI 0x3a 311 #define PCI_CB_IO_RANGE_MASK ~0x03 312 /* 0x3c-0x3d are same as for htype 0 */ 313 #define PCI_CB_BRIDGE_CONTROL 0x3e 314 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 315 #define PCI_CB_BRIDGE_CTL_SERR 0x02 316 #define PCI_CB_BRIDGE_CTL_ISA 0x04 317 #define PCI_CB_BRIDGE_CTL_VGA 0x08 318 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 319 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 320 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 321 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 322 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 323 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 324 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 325 #define PCI_CB_SUBSYSTEM_ID 0x42 326 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 327 /* 0x48-0x7f reserved */ 328 329 /* Capability lists */ 330 331 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 332 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 333 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 334 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 335 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 336 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 337 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 338 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 339 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 340 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 341 #define PCI_CAP_SIZEOF 4 342 343 /* Power Management Registers */ 344 345 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 346 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 347 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 348 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 349 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 350 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 351 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 352 #define PCI_PM_CTRL 4 /* PM control and status register */ 353 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 354 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 355 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 356 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 357 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 358 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 359 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 360 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 361 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 362 #define PCI_PM_SIZEOF 8 363 364 /* AGP registers */ 365 366 #define PCI_AGP_VERSION 2 /* BCD version number */ 367 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 368 #define PCI_AGP_STATUS 4 /* Status register */ 369 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 370 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 371 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 372 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 373 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 374 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 375 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 376 #define PCI_AGP_COMMAND 8 /* Control register */ 377 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 378 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 379 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 380 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 381 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 382 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 383 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 384 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 385 #define PCI_AGP_SIZEOF 12 386 387 /* PCI-X registers */ 388 389 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 390 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 391 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 392 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 393 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 394 395 396 /* Slot Identification */ 397 398 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 399 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 400 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 401 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 402 403 /* Message Signalled Interrupts registers */ 404 405 #define PCI_MSI_FLAGS 2 /* Various flags */ 406 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 407 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 408 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 409 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 410 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 411 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 412 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 413 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 414 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 415 416 #define PCI_MAX_PCI_DEVICES 32 417 #define PCI_MAX_PCI_FUNCTIONS 8 418 419 #define PCI_FIND_CAP_TTL 0x48 420 #define CAP_START_POS 0x40 421 422 /* Extended Capabilities (PCI-X 2.0 and Express) */ 423 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 424 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 425 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 426 427 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 428 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 429 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 430 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 431 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 432 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 433 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 434 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 435 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 436 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 437 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 438 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 439 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 440 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 441 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 442 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 443 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 444 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 445 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 446 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 447 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 448 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 449 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 450 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 451 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 452 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 453 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 454 455 /* Include the ID list */ 456 457 #include <pci_ids.h> 458 459 #ifndef __ASSEMBLY__ 460 461 #ifdef CONFIG_SYS_PCI_64BIT 462 typedef u64 pci_addr_t; 463 typedef u64 pci_size_t; 464 #else 465 typedef u32 pci_addr_t; 466 typedef u32 pci_size_t; 467 #endif 468 469 struct pci_region { 470 pci_addr_t bus_start; /* Start on the bus */ 471 phys_addr_t phys_start; /* Start in physical address space */ 472 pci_size_t size; /* Size */ 473 unsigned long flags; /* Resource flags */ 474 475 pci_addr_t bus_lower; 476 }; 477 478 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 479 #define PCI_REGION_IO 0x00000001 /* PCI IO space */ 480 #define PCI_REGION_TYPE 0x00000001 481 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 482 483 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 484 #define PCI_REGION_RO 0x00000200 /* Read-only memory */ 485 486 static inline void pci_set_region(struct pci_region *reg, 487 pci_addr_t bus_start, 488 phys_addr_t phys_start, 489 pci_size_t size, 490 unsigned long flags) { 491 reg->bus_start = bus_start; 492 reg->phys_start = phys_start; 493 reg->size = size; 494 reg->flags = flags; 495 } 496 497 typedef int pci_dev_t; 498 499 #define PCI_BUS(d) (((d) >> 16) & 0xff) 500 #define PCI_DEV(d) (((d) >> 11) & 0x1f) 501 #define PCI_FUNC(d) (((d) >> 8) & 0x7) 502 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) 503 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) 504 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) 505 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) 506 #define PCI_VENDEV(v, d) (((v) << 16) | (d)) 507 #define PCI_ANY_ID (~0) 508 509 struct pci_device_id { 510 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 511 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ 512 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ 513 unsigned long driver_data; /* Data private to the driver */ 514 }; 515 516 struct pci_controller; 517 518 struct pci_config_table { 519 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 520 unsigned int class; /* Class ID, or PCI_ANY_ID */ 521 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 522 unsigned int dev; /* Device number, or PCI_ANY_ID */ 523 unsigned int func; /* Function number, or PCI_ANY_ID */ 524 525 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 526 struct pci_config_table *); 527 unsigned long priv[3]; 528 }; 529 530 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 531 struct pci_config_table *); 532 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 533 struct pci_config_table *); 534 535 #define MAX_PCI_REGIONS 7 536 537 #define INDIRECT_TYPE_NO_PCIE_LINK 1 538 539 /* 540 * Structure of a PCI controller (host bridge) 541 * 542 * With driver model this is dev_get_uclass_priv(bus) 543 */ 544 struct pci_controller { 545 #ifdef CONFIG_DM_PCI 546 struct udevice *bus; 547 struct udevice *ctlr; 548 #else 549 struct pci_controller *next; 550 #endif 551 552 int first_busno; 553 int last_busno; 554 555 volatile unsigned int *cfg_addr; 556 volatile unsigned char *cfg_data; 557 558 int indirect_type; 559 560 /* 561 * TODO(sjg@chromium.org): With driver model we use struct 562 * pci_controller for both the controller and any bridge devices 563 * attached to it. But there is only one region list and it is in the 564 * top-level controller. 565 * 566 * This could be changed so that struct pci_controller is only used 567 * for PCI controllers and a separate UCLASS (or perhaps 568 * UCLASS_PCI_GENERIC) is used for bridges. 569 */ 570 struct pci_region regions[MAX_PCI_REGIONS]; 571 int region_count; 572 573 struct pci_config_table *config_table; 574 575 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 576 #ifndef CONFIG_DM_PCI 577 /* Low-level architecture-dependent routines */ 578 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); 579 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); 580 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); 581 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); 582 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); 583 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); 584 #endif 585 586 /* Used by auto config */ 587 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 588 589 /* Used by ppc405 autoconfig*/ 590 struct pci_region *pci_fb; 591 #ifndef CONFIG_DM_PCI 592 int current_busno; 593 594 void *priv_data; 595 #endif 596 }; 597 598 #ifndef CONFIG_DM_PCI 599 static inline void pci_set_ops(struct pci_controller *hose, 600 int (*read_byte)(struct pci_controller*, 601 pci_dev_t, int where, u8 *), 602 int (*read_word)(struct pci_controller*, 603 pci_dev_t, int where, u16 *), 604 int (*read_dword)(struct pci_controller*, 605 pci_dev_t, int where, u32 *), 606 int (*write_byte)(struct pci_controller*, 607 pci_dev_t, int where, u8), 608 int (*write_word)(struct pci_controller*, 609 pci_dev_t, int where, u16), 610 int (*write_dword)(struct pci_controller*, 611 pci_dev_t, int where, u32)) { 612 hose->read_byte = read_byte; 613 hose->read_word = read_word; 614 hose->read_dword = read_dword; 615 hose->write_byte = write_byte; 616 hose->write_word = write_word; 617 hose->write_dword = write_dword; 618 } 619 #endif 620 621 #ifdef CONFIG_PCI_INDIRECT_BRIDGE 622 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); 623 #endif 624 625 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 626 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 627 pci_addr_t addr, unsigned long flags); 628 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 629 phys_addr_t addr, unsigned long flags); 630 631 #define pci_phys_to_bus(dev, addr, flags) \ 632 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 633 #define pci_bus_to_phys(dev, addr, flags) \ 634 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 635 636 #define pci_virt_to_bus(dev, addr, flags) \ 637 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 638 (virt_to_phys(addr)), (flags)) 639 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 640 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 641 (addr), (flags)), \ 642 (len), (map_flags)) 643 644 #define pci_phys_to_mem(dev, addr) \ 645 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 646 #define pci_mem_to_phys(dev, addr) \ 647 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 648 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 649 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 650 651 #define pci_virt_to_mem(dev, addr) \ 652 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 653 #define pci_mem_to_virt(dev, addr, len, map_flags) \ 654 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 655 #define pci_virt_to_io(dev, addr) \ 656 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 657 #define pci_io_to_virt(dev, addr, len, map_flags) \ 658 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 659 660 /* For driver model these are defined in macros in pci_compat.c */ 661 extern int pci_hose_read_config_byte(struct pci_controller *hose, 662 pci_dev_t dev, int where, u8 *val); 663 extern int pci_hose_read_config_word(struct pci_controller *hose, 664 pci_dev_t dev, int where, u16 *val); 665 extern int pci_hose_read_config_dword(struct pci_controller *hose, 666 pci_dev_t dev, int where, u32 *val); 667 extern int pci_hose_write_config_byte(struct pci_controller *hose, 668 pci_dev_t dev, int where, u8 val); 669 extern int pci_hose_write_config_word(struct pci_controller *hose, 670 pci_dev_t dev, int where, u16 val); 671 extern int pci_hose_write_config_dword(struct pci_controller *hose, 672 pci_dev_t dev, int where, u32 val); 673 #endif 674 675 #ifndef CONFIG_DM_PCI 676 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); 677 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); 678 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); 679 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); 680 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); 681 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); 682 #endif 683 684 void pciauto_region_init(struct pci_region *res); 685 void pciauto_region_align(struct pci_region *res, pci_size_t size); 686 void pciauto_config_init(struct pci_controller *hose); 687 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 688 pci_addr_t *bar); 689 690 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 691 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 692 pci_dev_t dev, int where, u8 *val); 693 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 694 pci_dev_t dev, int where, u16 *val); 695 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 696 pci_dev_t dev, int where, u8 val); 697 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 698 pci_dev_t dev, int where, u16 val); 699 700 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 701 extern void pci_register_hose(struct pci_controller* hose); 702 extern struct pci_controller* pci_bus_to_hose(int bus); 703 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 704 extern struct pci_controller *pci_get_hose_head(void); 705 706 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); 707 extern int pci_hose_scan(struct pci_controller *hose); 708 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 709 710 extern void pciauto_setup_device(struct pci_controller *hose, 711 pci_dev_t dev, int bars_num, 712 struct pci_region *mem, 713 struct pci_region *prefetch, 714 struct pci_region *io); 715 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 716 pci_dev_t dev, int sub_bus); 717 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 718 pci_dev_t dev, int sub_bus); 719 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 720 721 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 722 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 723 pci_dev_t pci_find_class(unsigned int find_class, int index); 724 725 extern int pci_hose_config_device(struct pci_controller *hose, 726 pci_dev_t dev, 727 unsigned long io, 728 pci_addr_t mem, 729 unsigned long command); 730 731 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 732 int cap); 733 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 734 u8 hdr_type); 735 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 736 int cap); 737 738 int pci_find_next_ext_capability(struct pci_controller *hose, 739 pci_dev_t dev, int start, int cap); 740 int pci_hose_find_ext_capability(struct pci_controller *hose, 741 pci_dev_t dev, int cap); 742 743 #ifdef CONFIG_PCI_FIXUP_DEV 744 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 745 unsigned short vendor, 746 unsigned short device, 747 unsigned short class); 748 #endif 749 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ 750 751 const char * pci_class_str(u8 class); 752 int pci_last_busno(void); 753 754 #ifdef CONFIG_MPC85xx 755 extern void pci_mpc85xx_init (struct pci_controller *hose); 756 #endif 757 758 #ifdef CONFIG_PCIE_IMX 759 extern void imx_pcie_remove(void); 760 #endif 761 762 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 763 /** 764 * pci_write_bar32() - Write the address of a BAR including control bits 765 * 766 * This writes a raw address (with control bits) to a bar. This can be used 767 * with devices which require hard-coded addresses, not part of the normal 768 * PCI enumeration process. 769 * 770 * @hose: PCI hose to use 771 * @dev: PCI device to update 772 * @barnum: BAR number (0-5) 773 * @addr: BAR address with control bits 774 */ 775 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, 776 u32 addr); 777 778 /** 779 * pci_read_bar32() - read the address of a bar 780 * 781 * @hose: PCI hose to use 782 * @dev: PCI device to inspect 783 * @barnum: BAR number (0-5) 784 * @return address of the bar, masking out any control bits 785 * */ 786 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); 787 788 /** 789 * pci_hose_find_devices() - Find devices by vendor/device ID 790 * 791 * @hose: PCI hose to search 792 * @busnum: Bus number to search 793 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 794 * @indexp: Pointer to device index to find. To find the first matching 795 * device, pass 0; to find the second, pass 1, etc. This 796 * parameter is decremented for each non-matching device so 797 * can be called repeatedly. 798 */ 799 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, 800 struct pci_device_id *ids, int *indexp); 801 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ 802 803 /* Access sizes for PCI reads and writes */ 804 enum pci_size_t { 805 PCI_SIZE_8, 806 PCI_SIZE_16, 807 PCI_SIZE_32, 808 }; 809 810 struct udevice; 811 812 #ifdef CONFIG_DM_PCI 813 /** 814 * struct pci_child_platdata - information stored about each PCI device 815 * 816 * Every device on a PCI bus has this per-child data. 817 * 818 * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a 819 * PCI bus (i.e. UCLASS_PCI) 820 * 821 * @devfn: Encoded device and function index - see PCI_DEVFN() 822 * @vendor: PCI vendor ID (see pci_ids.h) 823 * @device: PCI device ID (see pci_ids.h) 824 * @class: PCI class, 3 bytes: (base, sub, prog-if) 825 */ 826 struct pci_child_platdata { 827 int devfn; 828 unsigned short vendor; 829 unsigned short device; 830 unsigned int class; 831 }; 832 833 /* PCI bus operations */ 834 struct dm_pci_ops { 835 /** 836 * read_config() - Read a PCI configuration value 837 * 838 * PCI buses must support reading and writing configuration values 839 * so that the bus can be scanned and its devices configured. 840 * 841 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. 842 * If bridges exist it is possible to use the top-level bus to 843 * access a sub-bus. In that case @bus will be the top-level bus 844 * and PCI_BUS(bdf) will be a different (higher) value 845 * 846 * @bus: Bus to read from 847 * @bdf: Bus, device and function to read 848 * @offset: Byte offset within the device's configuration space 849 * @valuep: Place to put the returned value 850 * @size: Access size 851 * @return 0 if OK, -ve on error 852 */ 853 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 854 ulong *valuep, enum pci_size_t size); 855 /** 856 * write_config() - Write a PCI configuration value 857 * 858 * @bus: Bus to write to 859 * @bdf: Bus, device and function to write 860 * @offset: Byte offset within the device's configuration space 861 * @value: Value to write 862 * @size: Access size 863 * @return 0 if OK, -ve on error 864 */ 865 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 866 ulong value, enum pci_size_t size); 867 }; 868 869 /* Get access to a PCI bus' operations */ 870 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) 871 872 /** 873 * dm_pci_get_bdf() - Get the BDF value for a device 874 * 875 * @dev: Device to check 876 * @return bus/device/function value (see PCI_BDF()) 877 */ 878 pci_dev_t dm_pci_get_bdf(struct udevice *dev); 879 880 /** 881 * pci_bind_bus_devices() - scan a PCI bus and bind devices 882 * 883 * Scan a PCI bus looking for devices. Bind each one that is found. If 884 * devices are already bound that match the scanned devices, just update the 885 * child data so that the device can be used correctly (this happens when 886 * the device tree describes devices we expect to see on the bus). 887 * 888 * Devices that are bound in this way will use a generic PCI driver which 889 * does nothing. The device can still be accessed but will not provide any 890 * driver interface. 891 * 892 * @bus: Bus containing devices to bind 893 * @return 0 if OK, -ve on error 894 */ 895 int pci_bind_bus_devices(struct udevice *bus); 896 897 /** 898 * pci_auto_config_devices() - configure bus devices ready for use 899 * 900 * This works through all devices on a bus by scanning the driver model 901 * data structures (normally these have been set up by pci_bind_bus_devices() 902 * earlier). 903 * 904 * Space is allocated for each PCI base address register (BAR) so that the 905 * devices are mapped into memory and I/O space ready for use. 906 * 907 * @bus: Bus containing devices to bind 908 * @return 0 if OK, -ve on error 909 */ 910 int pci_auto_config_devices(struct udevice *bus); 911 912 /** 913 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address 914 * 915 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 916 * @devp: Returns the device for this address, if found 917 * @return 0 if OK, -ENODEV if not found 918 */ 919 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); 920 921 /** 922 * pci_bus_find_devfn() - Find a device on a bus 923 * 924 * @find_devfn: PCI device address (device and function only) 925 * @devp: Returns the device for this address, if found 926 * @return 0 if OK, -ENODEV if not found 927 */ 928 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 929 struct udevice **devp); 930 931 /** 932 * pci_find_first_device() - return the first available PCI device 933 * 934 * This function and pci_find_first_device() allow iteration through all 935 * available PCI devices on all buses. Assuming there are any, this will 936 * return the first one. 937 * 938 * @devp: Set to the first available device, or NULL if no more are left 939 * or we got an error 940 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 941 */ 942 int pci_find_first_device(struct udevice **devp); 943 944 /** 945 * pci_find_next_device() - return the next available PCI device 946 * 947 * Finds the next available PCI device after the one supplied, or sets @devp 948 * to NULL if there are no more. 949 * 950 * @devp: On entry, the last device returned. Set to the next available 951 * device, or NULL if no more are left or we got an error 952 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 953 */ 954 int pci_find_next_device(struct udevice **devp); 955 956 /** 957 * pci_get_ff() - Returns a mask for the given access size 958 * 959 * @size: Access size 960 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for 961 * PCI_SIZE_32 962 */ 963 int pci_get_ff(enum pci_size_t size); 964 965 /** 966 * pci_bus_find_devices () - Find devices on a bus 967 * 968 * @bus: Bus to search 969 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 970 * @indexp: Pointer to device index to find. To find the first matching 971 * device, pass 0; to find the second, pass 1, etc. This 972 * parameter is decremented for each non-matching device so 973 * can be called repeatedly. 974 * @devp: Returns matching device if found 975 * @return 0 if found, -ENODEV if not 976 */ 977 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 978 int *indexp, struct udevice **devp); 979 980 /** 981 * pci_find_device_id() - Find a device on any bus 982 * 983 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 984 * @index: Index number of device to find, 0 for the first match, 1 for 985 * the second, etc. 986 * @devp: Returns matching device if found 987 * @return 0 if found, -ENODEV if not 988 */ 989 int pci_find_device_id(struct pci_device_id *ids, int index, 990 struct udevice **devp); 991 992 /** 993 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices 994 * 995 * This probes the given bus which causes it to be scanned for devices. The 996 * devices will be bound but not probed. 997 * 998 * @hose specifies the PCI hose that will be used for the scan. This is 999 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is 1000 * in @bdf, and is a subordinate bus reachable from @hose. 1001 * 1002 * @hose: PCI hose to scan 1003 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) 1004 * @return 0 if OK, -ve on error 1005 */ 1006 int dm_pci_hose_probe_bus(struct udevice *bus); 1007 1008 /** 1009 * pci_bus_read_config() - Read a configuration value from a device 1010 * 1011 * TODO(sjg@chromium.org): We should be able to pass just a device and have 1012 * it do the right thing. It would be good to have that function also. 1013 * 1014 * @bus: Bus to read from 1015 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1016 * @offset: Register offset to read 1017 * @valuep: Place to put the returned value 1018 * @size: Access size 1019 * @return 0 if OK, -ve on error 1020 */ 1021 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 1022 unsigned long *valuep, enum pci_size_t size); 1023 1024 /** 1025 * pci_bus_write_config() - Write a configuration value to a device 1026 * 1027 * @bus: Bus to write from 1028 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1029 * @offset: Register offset to write 1030 * @value: Value to write 1031 * @size: Access size 1032 * @return 0 if OK, -ve on error 1033 */ 1034 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 1035 unsigned long value, enum pci_size_t size); 1036 1037 /** 1038 * pci_bus_clrset_config32() - Update a configuration value for a device 1039 * 1040 * The register at @offset is updated to (oldvalue & ~clr) | set. 1041 * 1042 * @bus: Bus to access 1043 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1044 * @offset: Register offset to update 1045 * @clr: Bits to clear 1046 * @set: Bits to set 1047 * @return 0 if OK, -ve on error 1048 */ 1049 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, 1050 u32 clr, u32 set); 1051 1052 /** 1053 * Driver model PCI config access functions. Use these in preference to others 1054 * when you have a valid device 1055 */ 1056 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, 1057 enum pci_size_t size); 1058 1059 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep); 1060 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep); 1061 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep); 1062 1063 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, 1064 enum pci_size_t size); 1065 1066 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value); 1067 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value); 1068 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); 1069 1070 /** 1071 * These permit convenient read/modify/write on PCI configuration. The 1072 * register is updated to (oldvalue & ~clr) | set. 1073 */ 1074 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set); 1075 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set); 1076 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set); 1077 1078 /* 1079 * The following functions provide access to the above without needing the 1080 * size parameter. We are trying to encourage the use of the 8/16/32-style 1081 * functions, rather than byte/word/dword. But both are supported. 1082 */ 1083 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); 1084 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); 1085 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); 1086 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); 1087 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); 1088 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); 1089 1090 #ifdef CONFIG_DM_PCI_COMPAT 1091 /* Compatibility with old naming */ 1092 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, 1093 u32 value) 1094 { 1095 return pci_write_config32(pcidev, offset, value); 1096 } 1097 1098 /* Compatibility with old naming */ 1099 static inline int pci_write_config_word(pci_dev_t pcidev, int offset, 1100 u16 value) 1101 { 1102 return pci_write_config16(pcidev, offset, value); 1103 } 1104 1105 /* Compatibility with old naming */ 1106 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, 1107 u8 value) 1108 { 1109 return pci_write_config8(pcidev, offset, value); 1110 } 1111 1112 /* Compatibility with old naming */ 1113 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, 1114 u32 *valuep) 1115 { 1116 return pci_read_config32(pcidev, offset, valuep); 1117 } 1118 1119 /* Compatibility with old naming */ 1120 static inline int pci_read_config_word(pci_dev_t pcidev, int offset, 1121 u16 *valuep) 1122 { 1123 return pci_read_config16(pcidev, offset, valuep); 1124 } 1125 1126 /* Compatibility with old naming */ 1127 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, 1128 u8 *valuep) 1129 { 1130 return pci_read_config8(pcidev, offset, valuep); 1131 } 1132 #endif /* CONFIG_DM_PCI_COMPAT */ 1133 1134 /** 1135 * dm_pciauto_config_device() - configure a device ready for use 1136 * 1137 * Space is allocated for each PCI base address register (BAR) so that the 1138 * devices are mapped into memory and I/O space ready for use. 1139 * 1140 * @dev: Device to configure 1141 * @return 0 if OK, -ve on error 1142 */ 1143 int dm_pciauto_config_device(struct udevice *dev); 1144 1145 /** 1146 * pci_conv_32_to_size() - convert a 32-bit read value to the given size 1147 * 1148 * Some PCI buses must always perform 32-bit reads. The data must then be 1149 * shifted and masked to reflect the required access size and offset. This 1150 * function performs this transformation. 1151 * 1152 * @value: Value to transform (32-bit value read from @offset & ~3) 1153 * @offset: Register offset that was read 1154 * @size: Required size of the result 1155 * @return the value that would have been obtained if the read had been 1156 * performed at the given offset with the correct size 1157 */ 1158 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); 1159 1160 /** 1161 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write 1162 * 1163 * Some PCI buses must always perform 32-bit writes. To emulate a smaller 1164 * write the old 32-bit data must be read, updated with the required new data 1165 * and written back as a 32-bit value. This function performs the 1166 * transformation from the old value to the new value. 1167 * 1168 * @value: Value to transform (32-bit value read from @offset & ~3) 1169 * @offset: Register offset that should be written 1170 * @size: Required size of the write 1171 * @return the value that should be written as a 32-bit access to @offset & ~3. 1172 */ 1173 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, 1174 enum pci_size_t size); 1175 1176 /** 1177 * pci_get_controller() - obtain the controller to use for a bus 1178 * 1179 * @dev: Device to check 1180 * @return pointer to the controller device for this bus 1181 */ 1182 struct udevice *pci_get_controller(struct udevice *dev); 1183 1184 /** 1185 * pci_get_regions() - obtain pointers to all the region types 1186 * 1187 * @dev: Device to check 1188 * @iop: Returns a pointer to the I/O region, or NULL if none 1189 * @memp: Returns a pointer to the memory region, or NULL if none 1190 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none 1191 * @return the number of non-NULL regions returned, normally 3 1192 */ 1193 int pci_get_regions(struct udevice *dev, struct pci_region **iop, 1194 struct pci_region **memp, struct pci_region **prefp); 1195 1196 /** 1197 * dm_pci_write_bar32() - Write the address of a BAR 1198 * 1199 * This writes a raw address to a bar 1200 * 1201 * @dev: PCI device to update 1202 * @barnum: BAR number (0-5) 1203 * @addr: BAR address 1204 */ 1205 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); 1206 1207 /** 1208 * dm_pci_read_bar32() - read a base address register from a device 1209 * 1210 * @dev: Device to check 1211 * @barnum: Bar number to read (numbered from 0) 1212 * @return: value of BAR 1213 */ 1214 u32 dm_pci_read_bar32(struct udevice *dev, int barnum); 1215 1216 /** 1217 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address 1218 * 1219 * @dev: Device containing the PCI address 1220 * @addr: PCI address to convert 1221 * @flags: Flags for the region type (PCI_REGION_...) 1222 * @return physical address corresponding to that PCI bus address 1223 */ 1224 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, 1225 unsigned long flags); 1226 1227 /** 1228 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address 1229 * 1230 * @dev: Device containing the bus address 1231 * @addr: Physical address to convert 1232 * @flags: Flags for the region type (PCI_REGION_...) 1233 * @return PCI bus address corresponding to that physical address 1234 */ 1235 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, 1236 unsigned long flags); 1237 1238 /** 1239 * dm_pci_map_bar() - get a virtual address associated with a BAR region 1240 * 1241 * Looks up a base address register and finds the physical memory address 1242 * that corresponds to it 1243 * 1244 * @dev: Device to check 1245 * @bar: Bar number to read (numbered from 0) 1246 * @flags: Flags for the region type (PCI_REGION_...) 1247 * @return: pointer to the virtual address to use 1248 */ 1249 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); 1250 1251 /** 1252 * dm_pci_find_next_capability() - find a capability starting from an offset 1253 * 1254 * Tell if a device supports a given PCI capability. Returns the 1255 * address of the requested capability structure within the device's 1256 * PCI configuration space or 0 in case the device does not support it. 1257 * 1258 * Possible values for @cap: 1259 * 1260 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1261 * %PCI_CAP_ID_PCIX PCI-X 1262 * %PCI_CAP_ID_EXP PCI Express 1263 * %PCI_CAP_ID_MSIX MSI-X 1264 * 1265 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1266 * 1267 * @dev: PCI device to query 1268 * @start: offset to start from 1269 * @cap: capability code 1270 * @return: capability address or 0 if not supported 1271 */ 1272 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap); 1273 1274 /** 1275 * dm_pci_find_capability() - find a capability 1276 * 1277 * Tell if a device supports a given PCI capability. Returns the 1278 * address of the requested capability structure within the device's 1279 * PCI configuration space or 0 in case the device does not support it. 1280 * 1281 * Possible values for @cap: 1282 * 1283 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1284 * %PCI_CAP_ID_PCIX PCI-X 1285 * %PCI_CAP_ID_EXP PCI Express 1286 * %PCI_CAP_ID_MSIX MSI-X 1287 * 1288 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1289 * 1290 * @dev: PCI device to query 1291 * @cap: capability code 1292 * @return: capability address or 0 if not supported 1293 */ 1294 int dm_pci_find_capability(struct udevice *dev, int cap); 1295 1296 /** 1297 * dm_pci_find_next_ext_capability() - find an extended capability 1298 * starting from an offset 1299 * 1300 * Tell if a device supports a given PCI express extended capability. 1301 * Returns the address of the requested extended capability structure 1302 * within the device's PCI configuration space or 0 in case the device 1303 * does not support it. 1304 * 1305 * Possible values for @cap: 1306 * 1307 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1308 * %PCI_EXT_CAP_ID_VC Virtual Channel 1309 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1310 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1311 * 1312 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1313 * 1314 * @dev: PCI device to query 1315 * @start: offset to start from 1316 * @cap: extended capability code 1317 * @return: extended capability address or 0 if not supported 1318 */ 1319 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap); 1320 1321 /** 1322 * dm_pci_find_ext_capability() - find an extended capability 1323 * 1324 * Tell if a device supports a given PCI express extended capability. 1325 * Returns the address of the requested extended capability structure 1326 * within the device's PCI configuration space or 0 in case the device 1327 * does not support it. 1328 * 1329 * Possible values for @cap: 1330 * 1331 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1332 * %PCI_EXT_CAP_ID_VC Virtual Channel 1333 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1334 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1335 * 1336 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1337 * 1338 * @dev: PCI device to query 1339 * @cap: extended capability code 1340 * @return: extended capability address or 0 if not supported 1341 */ 1342 int dm_pci_find_ext_capability(struct udevice *dev, int cap); 1343 1344 #define dm_pci_virt_to_bus(dev, addr, flags) \ 1345 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) 1346 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 1347 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \ 1348 (len), (map_flags)) 1349 1350 #define dm_pci_phys_to_mem(dev, addr) \ 1351 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 1352 #define dm_pci_mem_to_phys(dev, addr) \ 1353 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 1354 #define dm_pci_phys_to_io(dev, addr) \ 1355 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 1356 #define dm_pci_io_to_phys(dev, addr) \ 1357 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 1358 1359 #define dm_pci_virt_to_mem(dev, addr) \ 1360 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 1361 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ 1362 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 1363 #define dm_pci_virt_to_io(dev, addr) \ 1364 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 1365 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \ 1366 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 1367 1368 /** 1369 * dm_pci_find_device() - find a device by vendor/device ID 1370 * 1371 * @vendor: Vendor ID 1372 * @device: Device ID 1373 * @index: 0 to find the first match, 1 for second, etc. 1374 * @devp: Returns pointer to the device, if found 1375 * @return 0 if found, -ve on error 1376 */ 1377 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, 1378 struct udevice **devp); 1379 1380 /** 1381 * dm_pci_find_class() - find a device by class 1382 * 1383 * @find_class: 3-byte (24-bit) class value to find 1384 * @index: 0 to find the first match, 1 for second, etc. 1385 * @devp: Returns pointer to the device, if found 1386 * @return 0 if found, -ve on error 1387 */ 1388 int dm_pci_find_class(uint find_class, int index, struct udevice **devp); 1389 1390 /** 1391 * struct dm_pci_emul_ops - PCI device emulator operations 1392 */ 1393 struct dm_pci_emul_ops { 1394 /** 1395 * get_devfn(): Check which device and function this emulators 1396 * 1397 * @dev: device to check 1398 * @return the device and function this emulates, or -ve on error 1399 */ 1400 int (*get_devfn)(struct udevice *dev); 1401 /** 1402 * read_config() - Read a PCI configuration value 1403 * 1404 * @dev: Emulated device to read from 1405 * @offset: Byte offset within the device's configuration space 1406 * @valuep: Place to put the returned value 1407 * @size: Access size 1408 * @return 0 if OK, -ve on error 1409 */ 1410 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep, 1411 enum pci_size_t size); 1412 /** 1413 * write_config() - Write a PCI configuration value 1414 * 1415 * @dev: Emulated device to write to 1416 * @offset: Byte offset within the device's configuration space 1417 * @value: Value to write 1418 * @size: Access size 1419 * @return 0 if OK, -ve on error 1420 */ 1421 int (*write_config)(struct udevice *dev, uint offset, ulong value, 1422 enum pci_size_t size); 1423 /** 1424 * read_io() - Read a PCI I/O value 1425 * 1426 * @dev: Emulated device to read from 1427 * @addr: I/O address to read 1428 * @valuep: Place to put the returned value 1429 * @size: Access size 1430 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1431 * other -ve value on error 1432 */ 1433 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, 1434 enum pci_size_t size); 1435 /** 1436 * write_io() - Write a PCI I/O value 1437 * 1438 * @dev: Emulated device to write from 1439 * @addr: I/O address to write 1440 * @value: Value to write 1441 * @size: Access size 1442 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1443 * other -ve value on error 1444 */ 1445 int (*write_io)(struct udevice *dev, unsigned int addr, 1446 ulong value, enum pci_size_t size); 1447 /** 1448 * map_physmem() - Map a device into sandbox memory 1449 * 1450 * @dev: Emulated device to map 1451 * @addr: Memory address, normally corresponding to a PCI BAR. 1452 * The device should have been configured to have a BAR 1453 * at this address. 1454 * @lenp: On entry, the size of the area to map, On exit it is 1455 * updated to the size actually mapped, which may be less 1456 * if the device has less space 1457 * @ptrp: Returns a pointer to the mapped address. The device's 1458 * space can be accessed as @lenp bytes starting here 1459 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1460 * other -ve value on error 1461 */ 1462 int (*map_physmem)(struct udevice *dev, phys_addr_t addr, 1463 unsigned long *lenp, void **ptrp); 1464 /** 1465 * unmap_physmem() - undo a memory mapping 1466 * 1467 * This must be called after map_physmem() to undo the mapping. 1468 * Some devices can use this to check what has been written into 1469 * their mapped memory and perform an operations they require on it. 1470 * In this way, map/unmap can be used as a sort of handshake between 1471 * the emulated device and its users. 1472 * 1473 * @dev: Emuated device to unmap 1474 * @vaddr: Mapped memory address, as passed to map_physmem() 1475 * @len: Size of area mapped, as returned by map_physmem() 1476 * @return 0 if OK, -ve on error 1477 */ 1478 int (*unmap_physmem)(struct udevice *dev, const void *vaddr, 1479 unsigned long len); 1480 }; 1481 1482 /* Get access to a PCI device emulator's operations */ 1483 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) 1484 1485 /** 1486 * sandbox_pci_get_emul() - Get the emulation device for a PCI device 1487 * 1488 * Searches for a suitable emulator for the given PCI bus device 1489 * 1490 * @bus: PCI bus to search 1491 * @find_devfn: PCI device and function address (PCI_DEVFN()) 1492 * @emulp: Returns emulated device if found 1493 * @return 0 if found, -ENODEV if not found 1494 */ 1495 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, 1496 struct udevice **emulp); 1497 1498 #endif /* CONFIG_DM_PCI */ 1499 1500 /** 1501 * PCI_DEVICE - macro used to describe a specific pci device 1502 * @vend: the 16 bit PCI Vendor ID 1503 * @dev: the 16 bit PCI Device ID 1504 * 1505 * This macro is used to create a struct pci_device_id that matches a 1506 * specific device. The subvendor and subdevice fields will be set to 1507 * PCI_ANY_ID. 1508 */ 1509 #define PCI_DEVICE(vend, dev) \ 1510 .vendor = (vend), .device = (dev), \ 1511 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1512 1513 /** 1514 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 1515 * @vend: the 16 bit PCI Vendor ID 1516 * @dev: the 16 bit PCI Device ID 1517 * @subvend: the 16 bit PCI Subvendor ID 1518 * @subdev: the 16 bit PCI Subdevice ID 1519 * 1520 * This macro is used to create a struct pci_device_id that matches a 1521 * specific device with subsystem information. 1522 */ 1523 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1524 .vendor = (vend), .device = (dev), \ 1525 .subvendor = (subvend), .subdevice = (subdev) 1526 1527 /** 1528 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 1529 * @dev_class: the class, subclass, prog-if triple for this device 1530 * @dev_class_mask: the class mask for this device 1531 * 1532 * This macro is used to create a struct pci_device_id that matches a 1533 * specific PCI class. The vendor, device, subvendor, and subdevice 1534 * fields will be set to PCI_ANY_ID. 1535 */ 1536 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ 1537 .class = (dev_class), .class_mask = (dev_class_mask), \ 1538 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1539 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1540 1541 /** 1542 * PCI_VDEVICE - macro used to describe a specific pci device in short form 1543 * @vend: the vendor name 1544 * @dev: the 16 bit PCI Device ID 1545 * 1546 * This macro is used to create a struct pci_device_id that matches a 1547 * specific PCI device. The subvendor, and subdevice fields will be set 1548 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1549 * private data. 1550 */ 1551 1552 #define PCI_VDEVICE(vend, dev) \ 1553 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1554 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1555 1556 /** 1557 * struct pci_driver_entry - Matches a driver to its pci_device_id list 1558 * @driver: Driver to use 1559 * @match: List of match records for this driver, terminated by {} 1560 */ 1561 struct pci_driver_entry { 1562 struct driver *driver; 1563 const struct pci_device_id *match; 1564 }; 1565 1566 #define U_BOOT_PCI_DEVICE(__name, __match) \ 1567 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\ 1568 .driver = llsym(struct driver, __name, driver), \ 1569 .match = __match, \ 1570 } 1571 1572 #endif /* __ASSEMBLY__ */ 1573 #endif /* _PCI_H */ 1574