1*fa36ae79SStefan Roese /* 2*fa36ae79SStefan Roese * (C) Copyright 2009 3*fa36ae79SStefan Roese * Stefan Roese, DENX Software Engineering, sr@denx.de. 4*fa36ae79SStefan Roese * 5*fa36ae79SStefan Roese * See file CREDITS for list of people who contributed to this 6*fa36ae79SStefan Roese * project. 7*fa36ae79SStefan Roese * 8*fa36ae79SStefan Roese * This program is free software; you can redistribute it and/or 9*fa36ae79SStefan Roese * modify it under the terms of the GNU General Public License as 10*fa36ae79SStefan Roese * published by the Free Software Foundation; either version 2 of 11*fa36ae79SStefan Roese * the License, or (at your option) any later version. 12*fa36ae79SStefan Roese * 13*fa36ae79SStefan Roese * This program is distributed in the hope that it will be useful, 14*fa36ae79SStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*fa36ae79SStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*fa36ae79SStefan Roese * GNU General Public License for more details. 17*fa36ae79SStefan Roese * 18*fa36ae79SStefan Roese * You should have received a copy of the GNU General Public License 19*fa36ae79SStefan Roese * along with this program; if not, write to the Free Software 20*fa36ae79SStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*fa36ae79SStefan Roese * MA 02111-1307 USA 22*fa36ae79SStefan Roese * 23*fa36ae79SStefan Roese */ 24*fa36ae79SStefan Roese 25*fa36ae79SStefan Roese #ifndef __CFI_FLASH_H__ 26*fa36ae79SStefan Roese #define __CFI_FLASH_H__ 27*fa36ae79SStefan Roese 28*fa36ae79SStefan Roese #define FLASH_CMD_CFI 0x98 29*fa36ae79SStefan Roese #define FLASH_CMD_READ_ID 0x90 30*fa36ae79SStefan Roese #define FLASH_CMD_RESET 0xff 31*fa36ae79SStefan Roese #define FLASH_CMD_BLOCK_ERASE 0x20 32*fa36ae79SStefan Roese #define FLASH_CMD_ERASE_CONFIRM 0xD0 33*fa36ae79SStefan Roese #define FLASH_CMD_WRITE 0x40 34*fa36ae79SStefan Roese #define FLASH_CMD_PROTECT 0x60 35*fa36ae79SStefan Roese #define FLASH_CMD_PROTECT_SET 0x01 36*fa36ae79SStefan Roese #define FLASH_CMD_PROTECT_CLEAR 0xD0 37*fa36ae79SStefan Roese #define FLASH_CMD_CLEAR_STATUS 0x50 38*fa36ae79SStefan Roese #define FLASH_CMD_READ_STATUS 0x70 39*fa36ae79SStefan Roese #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 40*fa36ae79SStefan Roese #define FLASH_CMD_WRITE_BUFFER_PROG 0xE9 41*fa36ae79SStefan Roese #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 42*fa36ae79SStefan Roese 43*fa36ae79SStefan Roese #define FLASH_STATUS_DONE 0x80 44*fa36ae79SStefan Roese #define FLASH_STATUS_ESS 0x40 45*fa36ae79SStefan Roese #define FLASH_STATUS_ECLBS 0x20 46*fa36ae79SStefan Roese #define FLASH_STATUS_PSLBS 0x10 47*fa36ae79SStefan Roese #define FLASH_STATUS_VPENS 0x08 48*fa36ae79SStefan Roese #define FLASH_STATUS_PSS 0x04 49*fa36ae79SStefan Roese #define FLASH_STATUS_DPS 0x02 50*fa36ae79SStefan Roese #define FLASH_STATUS_R 0x01 51*fa36ae79SStefan Roese #define FLASH_STATUS_PROTECT 0x01 52*fa36ae79SStefan Roese 53*fa36ae79SStefan Roese #define AMD_CMD_RESET 0xF0 54*fa36ae79SStefan Roese #define AMD_CMD_WRITE 0xA0 55*fa36ae79SStefan Roese #define AMD_CMD_ERASE_START 0x80 56*fa36ae79SStefan Roese #define AMD_CMD_ERASE_SECTOR 0x30 57*fa36ae79SStefan Roese #define AMD_CMD_UNLOCK_START 0xAA 58*fa36ae79SStefan Roese #define AMD_CMD_UNLOCK_ACK 0x55 59*fa36ae79SStefan Roese #define AMD_CMD_WRITE_TO_BUFFER 0x25 60*fa36ae79SStefan Roese #define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 61*fa36ae79SStefan Roese 62*fa36ae79SStefan Roese #define AMD_STATUS_TOGGLE 0x40 63*fa36ae79SStefan Roese #define AMD_STATUS_ERROR 0x20 64*fa36ae79SStefan Roese 65*fa36ae79SStefan Roese #define ATM_CMD_UNLOCK_SECT 0x70 66*fa36ae79SStefan Roese #define ATM_CMD_SOFTLOCK_START 0x80 67*fa36ae79SStefan Roese #define ATM_CMD_LOCK_SECT 0x40 68*fa36ae79SStefan Roese 69*fa36ae79SStefan Roese #define FLASH_CONTINUATION_CODE 0x7F 70*fa36ae79SStefan Roese 71*fa36ae79SStefan Roese #define FLASH_OFFSET_MANUFACTURER_ID 0x00 72*fa36ae79SStefan Roese #define FLASH_OFFSET_DEVICE_ID 0x01 73*fa36ae79SStefan Roese #define FLASH_OFFSET_DEVICE_ID2 0x0E 74*fa36ae79SStefan Roese #define FLASH_OFFSET_DEVICE_ID3 0x0F 75*fa36ae79SStefan Roese #define FLASH_OFFSET_CFI 0x55 76*fa36ae79SStefan Roese #define FLASH_OFFSET_CFI_ALT 0x555 77*fa36ae79SStefan Roese #define FLASH_OFFSET_CFI_RESP 0x10 78*fa36ae79SStefan Roese #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 79*fa36ae79SStefan Roese /* extended query table primary address */ 80*fa36ae79SStefan Roese #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 81*fa36ae79SStefan Roese #define FLASH_OFFSET_WTOUT 0x1F 82*fa36ae79SStefan Roese #define FLASH_OFFSET_WBTOUT 0x20 83*fa36ae79SStefan Roese #define FLASH_OFFSET_ETOUT 0x21 84*fa36ae79SStefan Roese #define FLASH_OFFSET_CETOUT 0x22 85*fa36ae79SStefan Roese #define FLASH_OFFSET_WMAX_TOUT 0x23 86*fa36ae79SStefan Roese #define FLASH_OFFSET_WBMAX_TOUT 0x24 87*fa36ae79SStefan Roese #define FLASH_OFFSET_EMAX_TOUT 0x25 88*fa36ae79SStefan Roese #define FLASH_OFFSET_CEMAX_TOUT 0x26 89*fa36ae79SStefan Roese #define FLASH_OFFSET_SIZE 0x27 90*fa36ae79SStefan Roese #define FLASH_OFFSET_INTERFACE 0x28 91*fa36ae79SStefan Roese #define FLASH_OFFSET_BUFFER_SIZE 0x2A 92*fa36ae79SStefan Roese #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C 93*fa36ae79SStefan Roese #define FLASH_OFFSET_ERASE_REGIONS 0x2D 94*fa36ae79SStefan Roese #define FLASH_OFFSET_PROTECT 0x02 95*fa36ae79SStefan Roese #define FLASH_OFFSET_USER_PROTECTION 0x85 96*fa36ae79SStefan Roese #define FLASH_OFFSET_INTEL_PROTECTION 0x81 97*fa36ae79SStefan Roese 98*fa36ae79SStefan Roese #define CFI_CMDSET_NONE 0 99*fa36ae79SStefan Roese #define CFI_CMDSET_INTEL_EXTENDED 1 100*fa36ae79SStefan Roese #define CFI_CMDSET_AMD_STANDARD 2 101*fa36ae79SStefan Roese #define CFI_CMDSET_INTEL_STANDARD 3 102*fa36ae79SStefan Roese #define CFI_CMDSET_AMD_EXTENDED 4 103*fa36ae79SStefan Roese #define CFI_CMDSET_MITSU_STANDARD 256 104*fa36ae79SStefan Roese #define CFI_CMDSET_MITSU_EXTENDED 257 105*fa36ae79SStefan Roese #define CFI_CMDSET_SST 258 106*fa36ae79SStefan Roese #define CFI_CMDSET_INTEL_PROG_REGIONS 512 107*fa36ae79SStefan Roese 108*fa36ae79SStefan Roese #ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ 109*fa36ae79SStefan Roese # undef FLASH_CMD_RESET 110*fa36ae79SStefan Roese # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ 111*fa36ae79SStefan Roese #endif 112*fa36ae79SStefan Roese 113*fa36ae79SStefan Roese #define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ 114*fa36ae79SStefan Roese 115*fa36ae79SStefan Roese typedef union { 116*fa36ae79SStefan Roese unsigned char c; 117*fa36ae79SStefan Roese unsigned short w; 118*fa36ae79SStefan Roese unsigned long l; 119*fa36ae79SStefan Roese unsigned long long ll; 120*fa36ae79SStefan Roese } cfiword_t; 121*fa36ae79SStefan Roese 122*fa36ae79SStefan Roese /* CFI standard query structure */ 123*fa36ae79SStefan Roese struct cfi_qry { 124*fa36ae79SStefan Roese u8 qry[3]; 125*fa36ae79SStefan Roese u16 p_id; 126*fa36ae79SStefan Roese u16 p_adr; 127*fa36ae79SStefan Roese u16 a_id; 128*fa36ae79SStefan Roese u16 a_adr; 129*fa36ae79SStefan Roese u8 vcc_min; 130*fa36ae79SStefan Roese u8 vcc_max; 131*fa36ae79SStefan Roese u8 vpp_min; 132*fa36ae79SStefan Roese u8 vpp_max; 133*fa36ae79SStefan Roese u8 word_write_timeout_typ; 134*fa36ae79SStefan Roese u8 buf_write_timeout_typ; 135*fa36ae79SStefan Roese u8 block_erase_timeout_typ; 136*fa36ae79SStefan Roese u8 chip_erase_timeout_typ; 137*fa36ae79SStefan Roese u8 word_write_timeout_max; 138*fa36ae79SStefan Roese u8 buf_write_timeout_max; 139*fa36ae79SStefan Roese u8 block_erase_timeout_max; 140*fa36ae79SStefan Roese u8 chip_erase_timeout_max; 141*fa36ae79SStefan Roese u8 dev_size; 142*fa36ae79SStefan Roese u16 interface_desc; 143*fa36ae79SStefan Roese u16 max_buf_write_size; 144*fa36ae79SStefan Roese u8 num_erase_regions; 145*fa36ae79SStefan Roese u32 erase_region_info[NUM_ERASE_REGIONS]; 146*fa36ae79SStefan Roese } __attribute__((packed)); 147*fa36ae79SStefan Roese 148*fa36ae79SStefan Roese struct cfi_pri_hdr { 149*fa36ae79SStefan Roese u8 pri[3]; 150*fa36ae79SStefan Roese u8 major_version; 151*fa36ae79SStefan Roese u8 minor_version; 152*fa36ae79SStefan Roese } __attribute__((packed)); 153*fa36ae79SStefan Roese 154*fa36ae79SStefan Roese void flash_write_cmd(flash_info_t * info, flash_sect_t sect, 155*fa36ae79SStefan Roese uint offset, u32 cmd); 156*fa36ae79SStefan Roese 157*fa36ae79SStefan Roese #endif /* __CFI_FLASH_H__ */ 158