1fa36ae79SStefan Roese /* 2fa36ae79SStefan Roese * (C) Copyright 2009 3fa36ae79SStefan Roese * Stefan Roese, DENX Software Engineering, sr@denx.de. 4fa36ae79SStefan Roese * 5fa36ae79SStefan Roese * See file CREDITS for list of people who contributed to this 6fa36ae79SStefan Roese * project. 7fa36ae79SStefan Roese * 8fa36ae79SStefan Roese * This program is free software; you can redistribute it and/or 9fa36ae79SStefan Roese * modify it under the terms of the GNU General Public License as 10fa36ae79SStefan Roese * published by the Free Software Foundation; either version 2 of 11fa36ae79SStefan Roese * the License, or (at your option) any later version. 12fa36ae79SStefan Roese * 13fa36ae79SStefan Roese * This program is distributed in the hope that it will be useful, 14fa36ae79SStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15fa36ae79SStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16fa36ae79SStefan Roese * GNU General Public License for more details. 17fa36ae79SStefan Roese * 18fa36ae79SStefan Roese * You should have received a copy of the GNU General Public License 19fa36ae79SStefan Roese * along with this program; if not, write to the Free Software 20fa36ae79SStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21fa36ae79SStefan Roese * MA 02111-1307 USA 22fa36ae79SStefan Roese * 23fa36ae79SStefan Roese */ 24fa36ae79SStefan Roese 25fa36ae79SStefan Roese #ifndef __CFI_FLASH_H__ 26fa36ae79SStefan Roese #define __CFI_FLASH_H__ 27fa36ae79SStefan Roese 28fa36ae79SStefan Roese #define FLASH_CMD_CFI 0x98 29fa36ae79SStefan Roese #define FLASH_CMD_READ_ID 0x90 30fa36ae79SStefan Roese #define FLASH_CMD_RESET 0xff 31fa36ae79SStefan Roese #define FLASH_CMD_BLOCK_ERASE 0x20 32fa36ae79SStefan Roese #define FLASH_CMD_ERASE_CONFIRM 0xD0 33fa36ae79SStefan Roese #define FLASH_CMD_WRITE 0x40 34fa36ae79SStefan Roese #define FLASH_CMD_PROTECT 0x60 35fa36ae79SStefan Roese #define FLASH_CMD_PROTECT_SET 0x01 36fa36ae79SStefan Roese #define FLASH_CMD_PROTECT_CLEAR 0xD0 37fa36ae79SStefan Roese #define FLASH_CMD_CLEAR_STATUS 0x50 38fa36ae79SStefan Roese #define FLASH_CMD_READ_STATUS 0x70 39fa36ae79SStefan Roese #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 40fa36ae79SStefan Roese #define FLASH_CMD_WRITE_BUFFER_PROG 0xE9 41fa36ae79SStefan Roese #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 42fa36ae79SStefan Roese 43fa36ae79SStefan Roese #define FLASH_STATUS_DONE 0x80 44fa36ae79SStefan Roese #define FLASH_STATUS_ESS 0x40 45fa36ae79SStefan Roese #define FLASH_STATUS_ECLBS 0x20 46fa36ae79SStefan Roese #define FLASH_STATUS_PSLBS 0x10 47fa36ae79SStefan Roese #define FLASH_STATUS_VPENS 0x08 48fa36ae79SStefan Roese #define FLASH_STATUS_PSS 0x04 49fa36ae79SStefan Roese #define FLASH_STATUS_DPS 0x02 50fa36ae79SStefan Roese #define FLASH_STATUS_R 0x01 51fa36ae79SStefan Roese #define FLASH_STATUS_PROTECT 0x01 52fa36ae79SStefan Roese 53fa36ae79SStefan Roese #define AMD_CMD_RESET 0xF0 54fa36ae79SStefan Roese #define AMD_CMD_WRITE 0xA0 55fa36ae79SStefan Roese #define AMD_CMD_ERASE_START 0x80 56fa36ae79SStefan Roese #define AMD_CMD_ERASE_SECTOR 0x30 57fa36ae79SStefan Roese #define AMD_CMD_UNLOCK_START 0xAA 58fa36ae79SStefan Roese #define AMD_CMD_UNLOCK_ACK 0x55 59fa36ae79SStefan Roese #define AMD_CMD_WRITE_TO_BUFFER 0x25 60fa36ae79SStefan Roese #define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 61fa36ae79SStefan Roese 62fa36ae79SStefan Roese #define AMD_STATUS_TOGGLE 0x40 63fa36ae79SStefan Roese #define AMD_STATUS_ERROR 0x20 64fa36ae79SStefan Roese 65fa36ae79SStefan Roese #define ATM_CMD_UNLOCK_SECT 0x70 66fa36ae79SStefan Roese #define ATM_CMD_SOFTLOCK_START 0x80 67fa36ae79SStefan Roese #define ATM_CMD_LOCK_SECT 0x40 68fa36ae79SStefan Roese 69fa36ae79SStefan Roese #define FLASH_CONTINUATION_CODE 0x7F 70fa36ae79SStefan Roese 71fa36ae79SStefan Roese #define FLASH_OFFSET_MANUFACTURER_ID 0x00 72fa36ae79SStefan Roese #define FLASH_OFFSET_DEVICE_ID 0x01 73fa36ae79SStefan Roese #define FLASH_OFFSET_DEVICE_ID2 0x0E 74fa36ae79SStefan Roese #define FLASH_OFFSET_DEVICE_ID3 0x0F 75fa36ae79SStefan Roese #define FLASH_OFFSET_CFI 0x55 76fa36ae79SStefan Roese #define FLASH_OFFSET_CFI_ALT 0x555 77fa36ae79SStefan Roese #define FLASH_OFFSET_CFI_RESP 0x10 78fa36ae79SStefan Roese #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 79fa36ae79SStefan Roese /* extended query table primary address */ 80fa36ae79SStefan Roese #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 81fa36ae79SStefan Roese #define FLASH_OFFSET_WTOUT 0x1F 82fa36ae79SStefan Roese #define FLASH_OFFSET_WBTOUT 0x20 83fa36ae79SStefan Roese #define FLASH_OFFSET_ETOUT 0x21 84fa36ae79SStefan Roese #define FLASH_OFFSET_CETOUT 0x22 85fa36ae79SStefan Roese #define FLASH_OFFSET_WMAX_TOUT 0x23 86fa36ae79SStefan Roese #define FLASH_OFFSET_WBMAX_TOUT 0x24 87fa36ae79SStefan Roese #define FLASH_OFFSET_EMAX_TOUT 0x25 88fa36ae79SStefan Roese #define FLASH_OFFSET_CEMAX_TOUT 0x26 89fa36ae79SStefan Roese #define FLASH_OFFSET_SIZE 0x27 90fa36ae79SStefan Roese #define FLASH_OFFSET_INTERFACE 0x28 91fa36ae79SStefan Roese #define FLASH_OFFSET_BUFFER_SIZE 0x2A 92fa36ae79SStefan Roese #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C 93fa36ae79SStefan Roese #define FLASH_OFFSET_ERASE_REGIONS 0x2D 94fa36ae79SStefan Roese #define FLASH_OFFSET_PROTECT 0x02 95fa36ae79SStefan Roese #define FLASH_OFFSET_USER_PROTECTION 0x85 96fa36ae79SStefan Roese #define FLASH_OFFSET_INTEL_PROTECTION 0x81 97fa36ae79SStefan Roese 98fa36ae79SStefan Roese #define CFI_CMDSET_NONE 0 99fa36ae79SStefan Roese #define CFI_CMDSET_INTEL_EXTENDED 1 100fa36ae79SStefan Roese #define CFI_CMDSET_AMD_STANDARD 2 101fa36ae79SStefan Roese #define CFI_CMDSET_INTEL_STANDARD 3 102fa36ae79SStefan Roese #define CFI_CMDSET_AMD_EXTENDED 4 103fa36ae79SStefan Roese #define CFI_CMDSET_MITSU_STANDARD 256 104fa36ae79SStefan Roese #define CFI_CMDSET_MITSU_EXTENDED 257 105fa36ae79SStefan Roese #define CFI_CMDSET_SST 258 106fa36ae79SStefan Roese #define CFI_CMDSET_INTEL_PROG_REGIONS 512 107fa36ae79SStefan Roese 108fa36ae79SStefan Roese #ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ 109fa36ae79SStefan Roese # undef FLASH_CMD_RESET 110fa36ae79SStefan Roese # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ 111fa36ae79SStefan Roese #endif 112fa36ae79SStefan Roese 113fa36ae79SStefan Roese #define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ 114fa36ae79SStefan Roese 115fa36ae79SStefan Roese typedef union { 116fa36ae79SStefan Roese unsigned char c; 117fa36ae79SStefan Roese unsigned short w; 118fa36ae79SStefan Roese unsigned long l; 119fa36ae79SStefan Roese unsigned long long ll; 120fa36ae79SStefan Roese } cfiword_t; 121fa36ae79SStefan Roese 122fa36ae79SStefan Roese /* CFI standard query structure */ 123fa36ae79SStefan Roese struct cfi_qry { 124fa36ae79SStefan Roese u8 qry[3]; 125fa36ae79SStefan Roese u16 p_id; 126fa36ae79SStefan Roese u16 p_adr; 127fa36ae79SStefan Roese u16 a_id; 128fa36ae79SStefan Roese u16 a_adr; 129fa36ae79SStefan Roese u8 vcc_min; 130fa36ae79SStefan Roese u8 vcc_max; 131fa36ae79SStefan Roese u8 vpp_min; 132fa36ae79SStefan Roese u8 vpp_max; 133fa36ae79SStefan Roese u8 word_write_timeout_typ; 134fa36ae79SStefan Roese u8 buf_write_timeout_typ; 135fa36ae79SStefan Roese u8 block_erase_timeout_typ; 136fa36ae79SStefan Roese u8 chip_erase_timeout_typ; 137fa36ae79SStefan Roese u8 word_write_timeout_max; 138fa36ae79SStefan Roese u8 buf_write_timeout_max; 139fa36ae79SStefan Roese u8 block_erase_timeout_max; 140fa36ae79SStefan Roese u8 chip_erase_timeout_max; 141fa36ae79SStefan Roese u8 dev_size; 142fa36ae79SStefan Roese u16 interface_desc; 143fa36ae79SStefan Roese u16 max_buf_write_size; 144fa36ae79SStefan Roese u8 num_erase_regions; 145fa36ae79SStefan Roese u32 erase_region_info[NUM_ERASE_REGIONS]; 146fa36ae79SStefan Roese } __attribute__((packed)); 147fa36ae79SStefan Roese 148fa36ae79SStefan Roese struct cfi_pri_hdr { 149fa36ae79SStefan Roese u8 pri[3]; 150fa36ae79SStefan Roese u8 major_version; 151fa36ae79SStefan Roese u8 minor_version; 152fa36ae79SStefan Roese } __attribute__((packed)); 153fa36ae79SStefan Roese 154*ca5def3fSStefan Roese #ifndef CONFIG_SYS_FLASH_BANKS_LIST 155*ca5def3fSStefan Roese #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 156*ca5def3fSStefan Roese #endif 157*ca5def3fSStefan Roese 158*ca5def3fSStefan Roese /* 159*ca5def3fSStefan Roese * CFI_MAX_FLASH_BANKS only used for flash_info struct declaration. 160*ca5def3fSStefan Roese * 161*ca5def3fSStefan Roese * Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined 162*ca5def3fSStefan Roese */ 163*ca5def3fSStefan Roese #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) 164*ca5def3fSStefan Roese #define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks) 165*ca5def3fSStefan Roese #define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT 166*ca5def3fSStefan Roese /* board code can update this variable before CFI detection */ 167*ca5def3fSStefan Roese extern int cfi_flash_num_flash_banks; 168*ca5def3fSStefan Roese #else 169*ca5def3fSStefan Roese #define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS 170*ca5def3fSStefan Roese #endif 171*ca5def3fSStefan Roese 172fa36ae79SStefan Roese void flash_write_cmd(flash_info_t * info, flash_sect_t sect, 173fa36ae79SStefan Roese uint offset, u32 cmd); 174fa36ae79SStefan Roese 175fa36ae79SStefan Roese #endif /* __CFI_FLASH_H__ */ 176