1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Inc, <www.ti.com> 4 * 5 * Author: Dan Murphy <dmurphy@ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _ASM_ARCH_XHCI_OMAP_H_ 11 #define _ASM_ARCH_XHCI_OMAP_H_ 12 13 #ifdef CONFIG_DRA7XX 14 #define OMAP_XHCI_BASE 0x488d0000 15 #define OMAP_OCP1_SCP_BASE 0x4A081000 16 #define OMAP_OTG_WRAPPER_BASE 0x488c0000 17 #else 18 /* Default to the OMAP5 XHCI defines */ 19 #define OMAP_XHCI_BASE 0x4a030000 20 #define OMAP_OCP1_SCP_BASE 0x4a084c00 21 #define OMAP_OTG_WRAPPER_BASE 0x4A020000 22 #endif 23 24 /* Phy register MACRO definitions */ 25 #define PLL_REGM_MASK 0x001FFE00 26 #define PLL_REGM_SHIFT 0x9 27 #define PLL_REGM_F_MASK 0x0003FFFF 28 #define PLL_REGM_F_SHIFT 0x0 29 #define PLL_REGN_MASK 0x000001FE 30 #define PLL_REGN_SHIFT 0x1 31 #define PLL_SELFREQDCO_MASK 0x0000000E 32 #define PLL_SELFREQDCO_SHIFT 0x1 33 #define PLL_SD_MASK 0x0003FC00 34 #define PLL_SD_SHIFT 0x9 35 #define SET_PLL_GO 0x1 36 #define PLL_TICOPWDN 0x10000 37 #define PLL_LOCK 0x2 38 #define PLL_IDLE 0x1 39 40 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 41 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 42 #define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) 43 #define USB3_PHY_RX_POWERON (1 << 14) 44 #define USB3_PHY_TX_POWERON (1 << 15) 45 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 46 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 47 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 48 49 /* USBOTGSS_WRAPPER definitions */ 50 #define USBOTGSS_WRAPRESET (1 << 17) 51 #define USBOTGSS_DMADISABLE (1 << 16) 52 #define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) 53 #define USBOTGSS_STANDBYMODE_SMRT (1 << 5) 54 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 55 #define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) 56 #define USBOTGSS_IDLEMODE_SMRT (1 << 3) 57 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 58 59 /* USBOTGSS_IRQENABLE_SET_0 bit */ 60 #define USBOTGSS_COREIRQ_EN (1 << 0) 61 62 /* USBOTGSS_IRQENABLE_SET_1 bits */ 63 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) 64 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) 65 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) 66 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) 67 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) 68 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) 69 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) 70 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) 71 #define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) 72 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) 73 74 /* 75 * USBOTGSS_WRAPPER registers 76 */ 77 struct omap_dwc_wrapper { 78 u32 revision; 79 80 u32 reserve_1[3]; 81 82 u32 sysconfig; /* offset of 0x10 */ 83 84 u32 reserve_2[3]; 85 u16 reserve_3; 86 87 u32 irqstatus_raw_0; /* offset of 0x24 */ 88 u32 irqstatus_0; 89 u32 irqenable_set_0; 90 u32 irqenable_clr_0; 91 92 u32 irqstatus_raw_1; /* offset of 0x34 */ 93 u32 irqstatus_1; 94 u32 irqenable_set_1; 95 u32 irqenable_clr_1; 96 97 u32 reserve_4[15]; 98 99 u32 utmi_otg_ctrl; /* offset of 0x80 */ 100 u32 utmi_otg_status; 101 102 u32 reserve_5[30]; 103 104 u32 mram_offset; /* offset of 0x100 */ 105 u32 fladj; 106 u32 dbg_config; 107 u32 dbg_data; 108 u32 dev_ebc_en; 109 }; 110 111 /* XHCI PHY register structure */ 112 struct omap_usb3_phy { 113 u32 reserve1; 114 u32 pll_status; 115 u32 pll_go; 116 u32 pll_config_1; 117 u32 pll_config_2; 118 u32 pll_config_3; 119 u32 pll_ssc_config_1; 120 u32 pll_ssc_config_2; 121 u32 pll_config_4; 122 }; 123 124 struct omap_xhci { 125 struct omap_dwc_wrapper *otg_wrapper; 126 struct omap_usb3_phy *usb3_phy; 127 struct xhci_hccr *hcd; 128 struct dwc3 *dwc3_reg; 129 }; 130 131 /* USB PHY functions */ 132 void omap_enable_phy(struct omap_xhci *omap); 133 void omap_reset_usb_phy(struct dwc3 *dwc3_reg); 134 void usb_phy_power(int on); 135 136 #endif /* _ASM_ARCH_XHCI_OMAP_H_ */ 137