1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Inc, <www.ti.com> 4 * 5 * Author: Dan Murphy <dmurphy@ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _ASM_ARCH_XHCI_OMAP_H_ 11 #define _ASM_ARCH_XHCI_OMAP_H_ 12 13 #define OMAP_XHCI_BASE 0x4a030000 14 #define OMAP_OCP1_SCP_BASE 0x4a084c00 15 #define OMAP_OTG_WRAPPER_BASE 0x4A020000 16 17 /* Phy register MACRO definitions */ 18 #define PLL_REGM_MASK 0x001FFE00 19 #define PLL_REGM_SHIFT 0x9 20 #define PLL_REGM_F_MASK 0x0003FFFF 21 #define PLL_REGM_F_SHIFT 0x0 22 #define PLL_REGN_MASK 0x000001FE 23 #define PLL_REGN_SHIFT 0x1 24 #define PLL_SELFREQDCO_MASK 0x0000000E 25 #define PLL_SELFREQDCO_SHIFT 0x1 26 #define PLL_SD_MASK 0x0003FC00 27 #define PLL_SD_SHIFT 0x9 28 #define SET_PLL_GO 0x1 29 #define PLL_TICOPWDN 0x10000 30 #define PLL_LOCK 0x2 31 #define PLL_IDLE 0x1 32 33 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 34 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 35 #define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) 36 #define USB3_PHY_RX_POWERON (1 << 14) 37 #define USB3_PHY_TX_POWERON (1 << 15) 38 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 39 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 40 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 41 42 /* USBOTGSS_WRAPPER definitions */ 43 #define USBOTGSS_WRAPRESET (1 << 17) 44 #define USBOTGSS_DMADISABLE (1 << 16) 45 #define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) 46 #define USBOTGSS_STANDBYMODE_SMRT (1 << 5) 47 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 48 #define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) 49 #define USBOTGSS_IDLEMODE_SMRT (1 << 3) 50 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 51 52 /* USBOTGSS_IRQENABLE_SET_0 bit */ 53 #define USBOTGSS_COREIRQ_EN (1 << 0) 54 55 /* USBOTGSS_IRQENABLE_SET_1 bits */ 56 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) 57 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) 58 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) 59 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) 60 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) 61 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) 62 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) 63 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) 64 #define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) 65 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) 66 67 /* 68 * USBOTGSS_WRAPPER registers 69 */ 70 struct omap_dwc_wrapper { 71 u32 revision; 72 73 u32 reserve_1[3]; 74 75 u32 sysconfig; /* offset of 0x10 */ 76 77 u32 reserve_2[3]; 78 u16 reserve_3; 79 80 u32 irqstatus_raw_0; /* offset of 0x24 */ 81 u32 irqstatus_0; 82 u32 irqenable_set_0; 83 u32 irqenable_clr_0; 84 85 u32 irqstatus_raw_1; /* offset of 0x34 */ 86 u32 irqstatus_1; 87 u32 irqenable_set_1; 88 u32 irqenable_clr_1; 89 90 u32 reserve_4[15]; 91 92 u32 utmi_otg_ctrl; /* offset of 0x80 */ 93 u32 utmi_otg_status; 94 95 u32 reserve_5[30]; 96 97 u32 mram_offset; /* offset of 0x100 */ 98 u32 fladj; 99 u32 dbg_config; 100 u32 dbg_data; 101 u32 dev_ebc_en; 102 }; 103 104 /* XHCI PHY register structure */ 105 struct omap_usb3_phy { 106 u32 reserve1; 107 u32 pll_status; 108 u32 pll_go; 109 u32 pll_config_1; 110 u32 pll_config_2; 111 u32 pll_config_3; 112 u32 pll_ssc_config_1; 113 u32 pll_ssc_config_2; 114 u32 pll_config_4; 115 }; 116 117 struct omap_xhci { 118 struct omap_dwc_wrapper *otg_wrapper; 119 struct omap_usb3_phy *usb3_phy; 120 struct xhci_hccr *hcd; 121 struct dwc3 *dwc3_reg; 122 }; 123 124 #endif /* _ASM_ARCH_XHCI_OMAP_H_ */ 125