1*41b667b8SDan Murphy /* 2*41b667b8SDan Murphy * (C) Copyright 2013 3*41b667b8SDan Murphy * Texas Instruments Inc, <www.ti.com> 4*41b667b8SDan Murphy * 5*41b667b8SDan Murphy * Author: Dan Murphy <dmurphy@ti.com> 6*41b667b8SDan Murphy * 7*41b667b8SDan Murphy * SPDX-License-Identifier: GPL-2.0+ 8*41b667b8SDan Murphy */ 9*41b667b8SDan Murphy 10*41b667b8SDan Murphy #ifndef _ASM_ARCH_XHCI_OMAP_H_ 11*41b667b8SDan Murphy #define _ASM_ARCH_XHCI_OMAP_H_ 12*41b667b8SDan Murphy 13*41b667b8SDan Murphy #define OMAP_XHCI_BASE 0x4a030000 14*41b667b8SDan Murphy #define OMAP_OCP1_SCP_BASE 0x4a084c00 15*41b667b8SDan Murphy #define OMAP_OTG_WRAPPER_BASE 0x4A020000 16*41b667b8SDan Murphy 17*41b667b8SDan Murphy /* Phy register MACRO definitions */ 18*41b667b8SDan Murphy #define PLL_REGM_MASK 0x001FFE00 19*41b667b8SDan Murphy #define PLL_REGM_SHIFT 0x9 20*41b667b8SDan Murphy #define PLL_REGM_F_MASK 0x0003FFFF 21*41b667b8SDan Murphy #define PLL_REGM_F_SHIFT 0x0 22*41b667b8SDan Murphy #define PLL_REGN_MASK 0x000001FE 23*41b667b8SDan Murphy #define PLL_REGN_SHIFT 0x1 24*41b667b8SDan Murphy #define PLL_SELFREQDCO_MASK 0x0000000E 25*41b667b8SDan Murphy #define PLL_SELFREQDCO_SHIFT 0x1 26*41b667b8SDan Murphy #define PLL_SD_MASK 0x0003FC00 27*41b667b8SDan Murphy #define PLL_SD_SHIFT 0x9 28*41b667b8SDan Murphy #define SET_PLL_GO 0x1 29*41b667b8SDan Murphy #define PLL_TICOPWDN 0x10000 30*41b667b8SDan Murphy #define PLL_LOCK 0x2 31*41b667b8SDan Murphy #define PLL_IDLE 0x1 32*41b667b8SDan Murphy 33*41b667b8SDan Murphy #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 34*41b667b8SDan Murphy #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 35*41b667b8SDan Murphy #define USB3_PHY_PARTIAL_RX_POWERON (1 << 6) 36*41b667b8SDan Murphy #define USB3_PHY_RX_POWERON (1 << 14) 37*41b667b8SDan Murphy #define USB3_PHY_TX_POWERON (1 << 15) 38*41b667b8SDan Murphy #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 39*41b667b8SDan Murphy #define USB3_PWRCTL_CLK_CMD_SHIFT 14 40*41b667b8SDan Murphy #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 41*41b667b8SDan Murphy 42*41b667b8SDan Murphy /* USBOTGSS_WRAPPER definitions */ 43*41b667b8SDan Murphy #define USBOTGSS_WRAPRESET (1 << 17) 44*41b667b8SDan Murphy #define USBOTGSS_DMADISABLE (1 << 16) 45*41b667b8SDan Murphy #define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4) 46*41b667b8SDan Murphy #define USBOTGSS_STANDBYMODE_SMRT (1 << 5) 47*41b667b8SDan Murphy #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 48*41b667b8SDan Murphy #define USBOTGSS_IDLEMODE_NOIDLE (1 << 2) 49*41b667b8SDan Murphy #define USBOTGSS_IDLEMODE_SMRT (1 << 3) 50*41b667b8SDan Murphy #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 51*41b667b8SDan Murphy 52*41b667b8SDan Murphy /* USBOTGSS_IRQENABLE_SET_0 bit */ 53*41b667b8SDan Murphy #define USBOTGSS_COREIRQ_EN (1 << 0) 54*41b667b8SDan Murphy 55*41b667b8SDan Murphy /* USBOTGSS_IRQENABLE_SET_1 bits */ 56*41b667b8SDan Murphy #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0) 57*41b667b8SDan Murphy #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3) 58*41b667b8SDan Murphy #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4) 59*41b667b8SDan Murphy #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5) 60*41b667b8SDan Murphy #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8) 61*41b667b8SDan Murphy #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11) 62*41b667b8SDan Murphy #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12) 63*41b667b8SDan Murphy #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13) 64*41b667b8SDan Murphy #define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16) 65*41b667b8SDan Murphy #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17) 66*41b667b8SDan Murphy 67*41b667b8SDan Murphy /* 68*41b667b8SDan Murphy * USBOTGSS_WRAPPER registers 69*41b667b8SDan Murphy */ 70*41b667b8SDan Murphy struct omap_dwc_wrapper { 71*41b667b8SDan Murphy u32 revision; 72*41b667b8SDan Murphy 73*41b667b8SDan Murphy u32 reserve_1[3]; 74*41b667b8SDan Murphy 75*41b667b8SDan Murphy u32 sysconfig; /* offset of 0x10 */ 76*41b667b8SDan Murphy 77*41b667b8SDan Murphy u32 reserve_2[3]; 78*41b667b8SDan Murphy u16 reserve_3; 79*41b667b8SDan Murphy 80*41b667b8SDan Murphy u32 irqstatus_raw_0; /* offset of 0x24 */ 81*41b667b8SDan Murphy u32 irqstatus_0; 82*41b667b8SDan Murphy u32 irqenable_set_0; 83*41b667b8SDan Murphy u32 irqenable_clr_0; 84*41b667b8SDan Murphy 85*41b667b8SDan Murphy u32 irqstatus_raw_1; /* offset of 0x34 */ 86*41b667b8SDan Murphy u32 irqstatus_1; 87*41b667b8SDan Murphy u32 irqenable_set_1; 88*41b667b8SDan Murphy u32 irqenable_clr_1; 89*41b667b8SDan Murphy 90*41b667b8SDan Murphy u32 reserve_4[15]; 91*41b667b8SDan Murphy 92*41b667b8SDan Murphy u32 utmi_otg_ctrl; /* offset of 0x80 */ 93*41b667b8SDan Murphy u32 utmi_otg_status; 94*41b667b8SDan Murphy 95*41b667b8SDan Murphy u32 reserve_5[30]; 96*41b667b8SDan Murphy 97*41b667b8SDan Murphy u32 mram_offset; /* offset of 0x100 */ 98*41b667b8SDan Murphy u32 fladj; 99*41b667b8SDan Murphy u32 dbg_config; 100*41b667b8SDan Murphy u32 dbg_data; 101*41b667b8SDan Murphy u32 dev_ebc_en; 102*41b667b8SDan Murphy }; 103*41b667b8SDan Murphy 104*41b667b8SDan Murphy /* XHCI PHY register structure */ 105*41b667b8SDan Murphy struct omap_usb3_phy { 106*41b667b8SDan Murphy u32 reserve1; 107*41b667b8SDan Murphy u32 pll_status; 108*41b667b8SDan Murphy u32 pll_go; 109*41b667b8SDan Murphy u32 pll_config_1; 110*41b667b8SDan Murphy u32 pll_config_2; 111*41b667b8SDan Murphy u32 pll_config_3; 112*41b667b8SDan Murphy u32 pll_ssc_config_1; 113*41b667b8SDan Murphy u32 pll_ssc_config_2; 114*41b667b8SDan Murphy u32 pll_config_4; 115*41b667b8SDan Murphy }; 116*41b667b8SDan Murphy 117*41b667b8SDan Murphy struct omap_xhci { 118*41b667b8SDan Murphy struct omap_dwc_wrapper *otg_wrapper; 119*41b667b8SDan Murphy struct omap_usb3_phy *usb3_phy; 120*41b667b8SDan Murphy struct xhci_hccr *hcd; 121*41b667b8SDan Murphy struct dwc3 *dwc3_reg; 122*41b667b8SDan Murphy }; 123*41b667b8SDan Murphy 124*41b667b8SDan Murphy #endif /* _ASM_ARCH_XHCI_OMAP_H_ */ 125