1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <peterpandong@micron.com> 7 */ 8 #ifndef __LINUX_MTD_SPINAND_H 9 #define __LINUX_MTD_SPINAND_H 10 11 #ifndef __UBOOT__ 12 #include <linux/mutex.h> 13 #include <linux/bitops.h> 14 #include <linux/device.h> 15 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/nand.h> 17 #include <linux/spi/spi.h> 18 #include <linux/spi/spi-mem.h> 19 #else 20 #include <common.h> 21 #include <spi.h> 22 #include <spi-mem.h> 23 #include <linux/mtd/nand.h> 24 #endif 25 26 /** 27 * Standard SPI NAND flash operations 28 */ 29 30 #define SPINAND_RESET_OP \ 31 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \ 32 SPI_MEM_OP_NO_ADDR, \ 33 SPI_MEM_OP_NO_DUMMY, \ 34 SPI_MEM_OP_NO_DATA) 35 36 #define SPINAND_WR_EN_DIS_OP(enable) \ 37 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ 38 SPI_MEM_OP_NO_ADDR, \ 39 SPI_MEM_OP_NO_DUMMY, \ 40 SPI_MEM_OP_NO_DATA) 41 42 #define SPINAND_READID_OP(naddr, ndummy, buf, len) \ 43 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ 44 SPI_MEM_OP_ADDR(naddr, 0, 1), \ 45 SPI_MEM_OP_DUMMY(ndummy, 1), \ 46 SPI_MEM_OP_DATA_IN(len, buf, 1)) 47 48 #define SPINAND_SET_FEATURE_OP(reg, valptr) \ 49 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ 50 SPI_MEM_OP_ADDR(1, reg, 1), \ 51 SPI_MEM_OP_NO_DUMMY, \ 52 SPI_MEM_OP_DATA_OUT(1, valptr, 1)) 53 54 #define SPINAND_GET_FEATURE_OP(reg, valptr) \ 55 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \ 56 SPI_MEM_OP_ADDR(1, reg, 1), \ 57 SPI_MEM_OP_NO_DUMMY, \ 58 SPI_MEM_OP_DATA_IN(1, valptr, 1)) 59 60 #define SPINAND_BLK_ERASE_OP(addr) \ 61 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \ 62 SPI_MEM_OP_ADDR(3, addr, 1), \ 63 SPI_MEM_OP_NO_DUMMY, \ 64 SPI_MEM_OP_NO_DATA) 65 66 #define SPINAND_PAGE_READ_OP(addr) \ 67 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \ 68 SPI_MEM_OP_ADDR(3, addr, 1), \ 69 SPI_MEM_OP_NO_DUMMY, \ 70 SPI_MEM_OP_NO_DATA) 71 72 #define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \ 73 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ 74 SPI_MEM_OP_ADDR(2, addr, 1), \ 75 SPI_MEM_OP_DUMMY(ndummy, 1), \ 76 SPI_MEM_OP_DATA_IN(len, buf, 1)) 77 78 #define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \ 79 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ 80 SPI_MEM_OP_ADDR(3, addr, 1), \ 81 SPI_MEM_OP_DUMMY(ndummy, 1), \ 82 SPI_MEM_OP_DATA_IN(len, buf, 1)) 83 84 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ 85 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 86 SPI_MEM_OP_ADDR(2, addr, 1), \ 87 SPI_MEM_OP_DUMMY(ndummy, 1), \ 88 SPI_MEM_OP_DATA_IN(len, buf, 2)) 89 90 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \ 91 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 92 SPI_MEM_OP_ADDR(3, addr, 1), \ 93 SPI_MEM_OP_DUMMY(ndummy, 1), \ 94 SPI_MEM_OP_DATA_IN(len, buf, 2)) 95 96 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ 97 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 98 SPI_MEM_OP_ADDR(2, addr, 1), \ 99 SPI_MEM_OP_DUMMY(ndummy, 1), \ 100 SPI_MEM_OP_DATA_IN(len, buf, 4)) 101 102 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \ 103 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 104 SPI_MEM_OP_ADDR(3, addr, 1), \ 105 SPI_MEM_OP_DUMMY(ndummy, 1), \ 106 SPI_MEM_OP_DATA_IN(len, buf, 4)) 107 108 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ 109 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 110 SPI_MEM_OP_ADDR(2, addr, 2), \ 111 SPI_MEM_OP_DUMMY(ndummy, 2), \ 112 SPI_MEM_OP_DATA_IN(len, buf, 2)) 113 114 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \ 115 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 116 SPI_MEM_OP_ADDR(3, addr, 2), \ 117 SPI_MEM_OP_DUMMY(ndummy, 2), \ 118 SPI_MEM_OP_DATA_IN(len, buf, 2)) 119 120 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \ 121 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 122 SPI_MEM_OP_ADDR(2, addr, 4), \ 123 SPI_MEM_OP_DUMMY(ndummy, 4), \ 124 SPI_MEM_OP_DATA_IN(len, buf, 4)) 125 126 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \ 127 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 128 SPI_MEM_OP_ADDR(3, addr, 4), \ 129 SPI_MEM_OP_DUMMY(ndummy, 4), \ 130 SPI_MEM_OP_DATA_IN(len, buf, 4)) 131 132 #define SPINAND_PROG_EXEC_OP(addr) \ 133 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ 134 SPI_MEM_OP_ADDR(3, addr, 1), \ 135 SPI_MEM_OP_NO_DUMMY, \ 136 SPI_MEM_OP_NO_DATA) 137 138 #define SPINAND_PROG_LOAD(reset, addr, buf, len) \ 139 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \ 140 SPI_MEM_OP_ADDR(2, addr, 1), \ 141 SPI_MEM_OP_NO_DUMMY, \ 142 SPI_MEM_OP_DATA_OUT(len, buf, 1)) 143 144 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \ 145 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \ 146 SPI_MEM_OP_ADDR(2, addr, 1), \ 147 SPI_MEM_OP_NO_DUMMY, \ 148 SPI_MEM_OP_DATA_OUT(len, buf, 4)) 149 150 /** 151 * Standard SPI NAND flash commands 152 */ 153 #define SPINAND_CMD_PROG_LOAD_X4 0x32 154 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34 155 156 /* feature register */ 157 #define REG_BLOCK_LOCK 0xa0 158 #define BL_ALL_UNLOCKED 0x00 159 160 /* configuration register */ 161 #define REG_CFG 0xb0 162 #define CFG_OTP_ENABLE BIT(6) 163 #define CFG_ECC_ENABLE BIT(4) 164 #define CFG_QUAD_ENABLE BIT(0) 165 166 /* status register */ 167 #define REG_STATUS 0xc0 168 #define STATUS_BUSY BIT(0) 169 #define STATUS_ERASE_FAILED BIT(2) 170 #define STATUS_PROG_FAILED BIT(3) 171 #define STATUS_ECC_MASK GENMASK(5, 4) 172 #define STATUS_ECC_NO_BITFLIPS (0 << 4) 173 #define STATUS_ECC_HAS_BITFLIPS (1 << 4) 174 #define STATUS_ECC_UNCOR_ERROR (2 << 4) 175 176 struct spinand_op; 177 struct spinand_device; 178 179 #define SPINAND_MAX_ID_LEN 4 180 181 /** 182 * struct spinand_id - SPI NAND id structure 183 * @data: buffer containing the id bytes. Currently 4 bytes large, but can 184 * be extended if required 185 * @len: ID length 186 */ 187 struct spinand_id { 188 u8 data[SPINAND_MAX_ID_LEN]; 189 int len; 190 }; 191 192 enum spinand_readid_method { 193 SPINAND_READID_METHOD_OPCODE, 194 SPINAND_READID_METHOD_OPCODE_ADDR, 195 SPINAND_READID_METHOD_OPCODE_DUMMY, 196 }; 197 198 /** 199 * struct spinand_devid - SPI NAND device id structure 200 * @id: device id of current chip 201 * @len: number of bytes in device id 202 * @method: method to read chip id 203 * There are 3 possible variants: 204 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately 205 * after read_id opcode. 206 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after 207 * read_id opcode + 1-byte address. 208 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after 209 * read_id opcode + 1 dummy byte. 210 */ 211 struct spinand_devid { 212 const u8 *id; 213 const u8 len; 214 const enum spinand_readid_method method; 215 }; 216 217 /** 218 * struct manufacurer_ops - SPI NAND manufacturer specific operations 219 * @init: initialize a SPI NAND device 220 * @cleanup: cleanup a SPI NAND device 221 * 222 * Each SPI NAND manufacturer driver should implement this interface so that 223 * NAND chips coming from this vendor can be initialized properly. 224 */ 225 struct spinand_manufacturer_ops { 226 int (*init)(struct spinand_device *spinand); 227 void (*cleanup)(struct spinand_device *spinand); 228 }; 229 230 /** 231 * struct spinand_manufacturer - SPI NAND manufacturer instance 232 * @id: manufacturer ID 233 * @name: manufacturer name 234 * @devid_len: number of bytes in device ID 235 * @chips: supported SPI NANDs under current manufacturer 236 * @nchips: number of SPI NANDs available in chips array 237 * @ops: manufacturer operations 238 */ 239 struct spinand_manufacturer { 240 u8 id; 241 char *name; 242 const struct spinand_info *chips; 243 const size_t nchips; 244 const struct spinand_manufacturer_ops *ops; 245 }; 246 247 /* SPI NAND manufacturers */ 248 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; 249 extern const struct spinand_manufacturer macronix_spinand_manufacturer; 250 extern const struct spinand_manufacturer micron_spinand_manufacturer; 251 extern const struct spinand_manufacturer toshiba_spinand_manufacturer; 252 extern const struct spinand_manufacturer winbond_spinand_manufacturer; 253 extern const struct spinand_manufacturer dosilicon_spinand_manufacturer; 254 extern const struct spinand_manufacturer esmt_spinand_manufacturer; 255 extern const struct spinand_manufacturer xtx_spinand_manufacturer; 256 extern const struct spinand_manufacturer hyf_spinand_manufacturer; 257 extern const struct spinand_manufacturer fmsh_spinand_manufacturer; 258 extern const struct spinand_manufacturer foresee_spinand_manufacturer; 259 extern const struct spinand_manufacturer biwin_spinand_manufacturer; 260 extern const struct spinand_manufacturer etron_spinand_manufacturer; 261 extern const struct spinand_manufacturer jsc_spinand_manufacturer; 262 extern const struct spinand_manufacturer silicongo_spinand_manufacturer; 263 extern const struct spinand_manufacturer unim_spinand_manufacturer; 264 extern const struct spinand_manufacturer skyhigh_spinand_manufacturer; 265 266 /** 267 * struct spinand_op_variants - SPI NAND operation variants 268 * @ops: the list of variants for a given operation 269 * @nops: the number of variants 270 * 271 * Some operations like read-from-cache/write-to-cache have several variants 272 * depending on the number of IO lines you use to transfer data or address 273 * cycles. This structure is a way to describe the different variants supported 274 * by a chip and let the core pick the best one based on the SPI mem controller 275 * capabilities. 276 */ 277 struct spinand_op_variants { 278 const struct spi_mem_op *ops; 279 unsigned int nops; 280 }; 281 282 #define SPINAND_OP_VARIANTS(name, ...) \ 283 const struct spinand_op_variants name = { \ 284 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \ 285 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \ 286 sizeof(struct spi_mem_op), \ 287 } 288 289 /** 290 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND 291 * chip 292 * @get_status: get the ECC status. Should return a positive number encoding 293 * the number of corrected bitflips if correction was possible or 294 * -EBADMSG if there are uncorrectable errors. I can also return 295 * other negative error codes if the error is not caused by 296 * uncorrectable bitflips 297 * @ooblayout: the OOB layout used by the on-die ECC implementation 298 */ 299 struct spinand_ecc_info { 300 int (*get_status)(struct spinand_device *spinand, u8 status); 301 const struct mtd_ooblayout_ops *ooblayout; 302 }; 303 304 #define SPINAND_HAS_QE_BIT BIT(0) 305 306 /** 307 * struct spinand_info - Structure used to describe SPI NAND chips 308 * @model: model name 309 * @devid: device ID 310 * @flags: OR-ing of the SPINAND_XXX flags 311 * @memorg: memory organization 312 * @eccreq: ECC requirements 313 * @eccinfo: on-die ECC info 314 * @op_variants: operations variants 315 * @op_variants.read_cache: variants of the read-cache operation 316 * @op_variants.write_cache: variants of the write-cache operation 317 * @op_variants.update_cache: variants of the update-cache operation 318 * @select_target: function used to select a target/die. Required only for 319 * multi-die chips 320 * 321 * Each SPI NAND manufacturer driver should have a spinand_info table 322 * describing all the chips supported by the driver. 323 */ 324 struct spinand_info { 325 const char *model; 326 struct spinand_devid devid; 327 u32 flags; 328 struct nand_memory_organization memorg; 329 struct nand_ecc_req eccreq; 330 struct spinand_ecc_info eccinfo; 331 struct { 332 const struct spinand_op_variants *read_cache; 333 const struct spinand_op_variants *write_cache; 334 const struct spinand_op_variants *update_cache; 335 } op_variants; 336 int (*select_target)(struct spinand_device *spinand, 337 unsigned int target); 338 }; 339 340 #define SPINAND_ID(__method, ...) \ 341 { \ 342 .id = (const u8[]){ __VA_ARGS__ }, \ 343 .len = sizeof((u8[]){ __VA_ARGS__ }), \ 344 .method = __method, \ 345 } 346 347 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ 348 { \ 349 .read_cache = __read, \ 350 .write_cache = __write, \ 351 .update_cache = __update, \ 352 } 353 354 #define SPINAND_ECCINFO(__ooblayout, __get_status) \ 355 .eccinfo = { \ 356 .ooblayout = __ooblayout, \ 357 .get_status = __get_status, \ 358 } 359 360 #define SPINAND_SELECT_TARGET(__func) \ 361 .select_target = __func, 362 363 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ 364 __flags, ...) \ 365 { \ 366 .model = __model, \ 367 .devid = __id, \ 368 .memorg = __memorg, \ 369 .eccreq = __eccreq, \ 370 .op_variants = __op_variants, \ 371 .flags = __flags, \ 372 __VA_ARGS__ \ 373 } 374 375 /** 376 * struct spinand_device - SPI NAND device instance 377 * @base: NAND device instance 378 * @slave: pointer to the SPI slave object 379 * @lock: lock used to serialize accesses to the NAND 380 * @id: NAND ID as returned by READ_ID 381 * @flags: NAND flags 382 * @op_templates: various SPI mem op templates 383 * @op_templates.read_cache: read cache op template 384 * @op_templates.write_cache: write cache op template 385 * @op_templates.update_cache: update cache op template 386 * @select_target: select a specific target/die. Usually called before sending 387 * a command addressing a page or an eraseblock embedded in 388 * this die. Only required if your chip exposes several dies 389 * @cur_target: currently selected target/die 390 * @eccinfo: on-die ECC information 391 * @cfg_cache: config register cache. One entry per die 392 * @databuf: bounce buffer for data 393 * @oobbuf: bounce buffer for OOB data 394 * @scratchbuf: buffer used for everything but page accesses. This is needed 395 * because the spi-mem interface explicitly requests that buffers 396 * passed in spi_mem_op be DMA-able, so we can't based the bufs on 397 * the stack 398 * @manufacturer: SPI NAND manufacturer information 399 * @priv: manufacturer private data 400 */ 401 struct spinand_device { 402 struct nand_device base; 403 #ifndef __UBOOT__ 404 struct spi_mem *spimem; 405 struct mutex lock; 406 #else 407 struct spi_slave *slave; 408 #endif 409 struct spinand_id id; 410 u32 flags; 411 412 struct { 413 const struct spi_mem_op *read_cache; 414 const struct spi_mem_op *write_cache; 415 const struct spi_mem_op *update_cache; 416 } op_templates; 417 418 int (*select_target)(struct spinand_device *spinand, 419 unsigned int target); 420 unsigned int cur_target; 421 422 struct spinand_ecc_info eccinfo; 423 424 u8 *cfg_cache; 425 u8 *databuf; 426 u8 *oobbuf; 427 u8 *scratchbuf; 428 const struct spinand_manufacturer *manufacturer; 429 void *priv; 430 }; 431 432 /** 433 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance 434 * @mtd: MTD instance 435 * 436 * Return: the SPI NAND device attached to @mtd. 437 */ 438 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd) 439 { 440 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base); 441 } 442 443 /** 444 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device 445 * @spinand: SPI NAND device 446 * 447 * Return: the MTD device embedded in @spinand. 448 */ 449 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand) 450 { 451 return nanddev_to_mtd(&spinand->base); 452 } 453 454 /** 455 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object 456 * @nand: NAND object 457 * 458 * Return: the SPI NAND device embedding @nand. 459 */ 460 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand) 461 { 462 return container_of(nand, struct spinand_device, base); 463 } 464 465 /** 466 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object 467 * @spinand: SPI NAND device 468 * 469 * Return: the NAND device embedded in @spinand. 470 */ 471 static inline struct nand_device * 472 spinand_to_nand(struct spinand_device *spinand) 473 { 474 return &spinand->base; 475 } 476 477 /** 478 * spinand_set_of_node - Attach a DT node to a SPI NAND device 479 * @spinand: SPI NAND device 480 * @np: DT node 481 * 482 * Attach a DT node to a SPI NAND device. 483 */ 484 static inline void spinand_set_of_node(struct spinand_device *spinand, 485 const struct device_node *np) 486 { 487 nanddev_set_of_node(&spinand->base, np); 488 } 489 490 int spinand_match_and_init(struct spinand_device *spinand, 491 const struct spinand_info *table, 492 unsigned int table_size, 493 enum spinand_readid_method rdid_method); 494 495 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); 496 int spinand_select_target(struct spinand_device *spinand, unsigned int target); 497 498 #endif /* __LINUX_MTD_SPINAND_H */ 499