1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <peterpandong@micron.com> 7 */ 8 #ifndef __LINUX_MTD_SPINAND_H 9 #define __LINUX_MTD_SPINAND_H 10 11 #ifndef __UBOOT__ 12 #include <linux/mutex.h> 13 #include <linux/bitops.h> 14 #include <linux/device.h> 15 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/nand.h> 17 #include <linux/spi/spi.h> 18 #include <linux/spi/spi-mem.h> 19 #else 20 #include <common.h> 21 #include <spi.h> 22 #include <spi-mem.h> 23 #include <linux/mtd/nand.h> 24 #endif 25 26 /** 27 * Standard SPI NAND flash operations 28 */ 29 30 #define SPINAND_RESET_OP \ 31 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \ 32 SPI_MEM_OP_NO_ADDR, \ 33 SPI_MEM_OP_NO_DUMMY, \ 34 SPI_MEM_OP_NO_DATA) 35 36 #define SPINAND_WR_EN_DIS_OP(enable) \ 37 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ 38 SPI_MEM_OP_NO_ADDR, \ 39 SPI_MEM_OP_NO_DUMMY, \ 40 SPI_MEM_OP_NO_DATA) 41 42 #define SPINAND_READID_OP(naddr, ndummy, buf, len) \ 43 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ 44 SPI_MEM_OP_ADDR(naddr, 0, 1), \ 45 SPI_MEM_OP_DUMMY(ndummy, 1), \ 46 SPI_MEM_OP_DATA_IN(len, buf, 1)) 47 48 #define SPINAND_SET_FEATURE_OP(reg, valptr) \ 49 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ 50 SPI_MEM_OP_ADDR(1, reg, 1), \ 51 SPI_MEM_OP_NO_DUMMY, \ 52 SPI_MEM_OP_DATA_OUT(1, valptr, 1)) 53 54 #define SPINAND_GET_FEATURE_OP(reg, valptr) \ 55 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \ 56 SPI_MEM_OP_ADDR(1, reg, 1), \ 57 SPI_MEM_OP_NO_DUMMY, \ 58 SPI_MEM_OP_DATA_IN(1, valptr, 1)) 59 60 #define SPINAND_BLK_ERASE_OP(addr) \ 61 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \ 62 SPI_MEM_OP_ADDR(3, addr, 1), \ 63 SPI_MEM_OP_NO_DUMMY, \ 64 SPI_MEM_OP_NO_DATA) 65 66 #define SPINAND_PAGE_READ_OP(addr) \ 67 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \ 68 SPI_MEM_OP_ADDR(3, addr, 1), \ 69 SPI_MEM_OP_NO_DUMMY, \ 70 SPI_MEM_OP_NO_DATA) 71 72 #define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \ 73 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ 74 SPI_MEM_OP_ADDR(2, addr, 1), \ 75 SPI_MEM_OP_DUMMY(ndummy, 1), \ 76 SPI_MEM_OP_DATA_IN(len, buf, 1)) 77 78 #define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \ 79 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ 80 SPI_MEM_OP_ADDR(3, addr, 1), \ 81 SPI_MEM_OP_DUMMY(ndummy, 1), \ 82 SPI_MEM_OP_DATA_IN(len, buf, 1)) 83 84 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ 85 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 86 SPI_MEM_OP_ADDR(2, addr, 1), \ 87 SPI_MEM_OP_DUMMY(ndummy, 1), \ 88 SPI_MEM_OP_DATA_IN(len, buf, 2)) 89 90 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \ 91 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 92 SPI_MEM_OP_ADDR(3, addr, 1), \ 93 SPI_MEM_OP_DUMMY(ndummy, 1), \ 94 SPI_MEM_OP_DATA_IN(len, buf, 2)) 95 96 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ 97 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 98 SPI_MEM_OP_ADDR(2, addr, 1), \ 99 SPI_MEM_OP_DUMMY(ndummy, 1), \ 100 SPI_MEM_OP_DATA_IN(len, buf, 4)) 101 102 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \ 103 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 104 SPI_MEM_OP_ADDR(3, addr, 1), \ 105 SPI_MEM_OP_DUMMY(ndummy, 1), \ 106 SPI_MEM_OP_DATA_IN(len, buf, 4)) 107 108 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ 109 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 110 SPI_MEM_OP_ADDR(2, addr, 2), \ 111 SPI_MEM_OP_DUMMY(ndummy, 2), \ 112 SPI_MEM_OP_DATA_IN(len, buf, 2)) 113 114 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \ 115 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 116 SPI_MEM_OP_ADDR(3, addr, 2), \ 117 SPI_MEM_OP_DUMMY(ndummy, 2), \ 118 SPI_MEM_OP_DATA_IN(len, buf, 2)) 119 120 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \ 121 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 122 SPI_MEM_OP_ADDR(2, addr, 4), \ 123 SPI_MEM_OP_DUMMY(ndummy, 4), \ 124 SPI_MEM_OP_DATA_IN(len, buf, 4)) 125 126 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \ 127 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 128 SPI_MEM_OP_ADDR(3, addr, 4), \ 129 SPI_MEM_OP_DUMMY(ndummy, 4), \ 130 SPI_MEM_OP_DATA_IN(len, buf, 4)) 131 132 #define SPINAND_PROG_EXEC_OP(addr) \ 133 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ 134 SPI_MEM_OP_ADDR(3, addr, 1), \ 135 SPI_MEM_OP_NO_DUMMY, \ 136 SPI_MEM_OP_NO_DATA) 137 138 #define SPINAND_PROG_LOAD(reset, addr, buf, len) \ 139 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \ 140 SPI_MEM_OP_ADDR(2, addr, 1), \ 141 SPI_MEM_OP_NO_DUMMY, \ 142 SPI_MEM_OP_DATA_OUT(len, buf, 1)) 143 144 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \ 145 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \ 146 SPI_MEM_OP_ADDR(2, addr, 1), \ 147 SPI_MEM_OP_NO_DUMMY, \ 148 SPI_MEM_OP_DATA_OUT(len, buf, 4)) 149 150 /** 151 * Standard SPI NAND flash commands 152 */ 153 #define SPINAND_CMD_PROG_LOAD_X4 0x32 154 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34 155 156 /* feature register */ 157 #define REG_BLOCK_LOCK 0xa0 158 #define BL_ALL_UNLOCKED 0x00 159 #define HWP_EN 0x02 /* Skyhigh feature, Hardware write protection */ 160 161 /* configuration register */ 162 #define REG_CFG 0xb0 163 #define CFG_OTP_ENABLE BIT(6) 164 #define CFG_ECC_ENABLE BIT(4) 165 #define CFG_QUAD_ENABLE BIT(0) 166 167 /* status register */ 168 #define REG_STATUS 0xc0 169 #define STATUS_BUSY BIT(0) 170 #define STATUS_ERASE_FAILED BIT(2) 171 #define STATUS_PROG_FAILED BIT(3) 172 #define STATUS_ECC_MASK GENMASK(5, 4) 173 #define STATUS_ECC_NO_BITFLIPS (0 << 4) 174 #define STATUS_ECC_HAS_BITFLIPS (1 << 4) 175 #define STATUS_ECC_UNCOR_ERROR (2 << 4) 176 177 struct spinand_op; 178 struct spinand_device; 179 180 #define SPINAND_MAX_ID_LEN 4 181 182 /** 183 * struct spinand_id - SPI NAND id structure 184 * @data: buffer containing the id bytes. Currently 4 bytes large, but can 185 * be extended if required 186 * @len: ID length 187 */ 188 struct spinand_id { 189 u8 data[SPINAND_MAX_ID_LEN]; 190 int len; 191 }; 192 193 enum spinand_readid_method { 194 SPINAND_READID_METHOD_OPCODE, 195 SPINAND_READID_METHOD_OPCODE_ADDR, 196 SPINAND_READID_METHOD_OPCODE_DUMMY, 197 }; 198 199 /** 200 * struct spinand_devid - SPI NAND device id structure 201 * @id: device id of current chip 202 * @len: number of bytes in device id 203 * @method: method to read chip id 204 * There are 3 possible variants: 205 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately 206 * after read_id opcode. 207 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after 208 * read_id opcode + 1-byte address. 209 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after 210 * read_id opcode + 1 dummy byte. 211 */ 212 struct spinand_devid { 213 const u8 *id; 214 const u8 len; 215 const enum spinand_readid_method method; 216 }; 217 218 /** 219 * struct manufacurer_ops - SPI NAND manufacturer specific operations 220 * @init: initialize a SPI NAND device 221 * @cleanup: cleanup a SPI NAND device 222 * 223 * Each SPI NAND manufacturer driver should implement this interface so that 224 * NAND chips coming from this vendor can be initialized properly. 225 */ 226 struct spinand_manufacturer_ops { 227 int (*init)(struct spinand_device *spinand); 228 void (*cleanup)(struct spinand_device *spinand); 229 }; 230 231 /** 232 * struct spinand_manufacturer - SPI NAND manufacturer instance 233 * @id: manufacturer ID 234 * @name: manufacturer name 235 * @devid_len: number of bytes in device ID 236 * @chips: supported SPI NANDs under current manufacturer 237 * @nchips: number of SPI NANDs available in chips array 238 * @ops: manufacturer operations 239 */ 240 struct spinand_manufacturer { 241 u8 id; 242 char *name; 243 const struct spinand_info *chips; 244 const size_t nchips; 245 const struct spinand_manufacturer_ops *ops; 246 }; 247 248 /* SPI NAND manufacturers */ 249 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; 250 extern const struct spinand_manufacturer macronix_spinand_manufacturer; 251 extern const struct spinand_manufacturer micron_spinand_manufacturer; 252 extern const struct spinand_manufacturer toshiba_spinand_manufacturer; 253 extern const struct spinand_manufacturer winbond_spinand_manufacturer; 254 extern const struct spinand_manufacturer dosilicon_spinand_manufacturer; 255 extern const struct spinand_manufacturer esmt_spinand_manufacturer; 256 extern const struct spinand_manufacturer xincun_spinand_manufacturer; 257 extern const struct spinand_manufacturer xtx_spinand_manufacturer; 258 extern const struct spinand_manufacturer hyf_spinand_manufacturer; 259 extern const struct spinand_manufacturer fmsh_spinand_manufacturer; 260 extern const struct spinand_manufacturer foresee_spinand_manufacturer; 261 extern const struct spinand_manufacturer biwin_spinand_manufacturer; 262 extern const struct spinand_manufacturer etron_spinand_manufacturer; 263 extern const struct spinand_manufacturer jsc_spinand_manufacturer; 264 extern const struct spinand_manufacturer silicongo_spinand_manufacturer; 265 extern const struct spinand_manufacturer unim_spinand_manufacturer; 266 extern const struct spinand_manufacturer unim_zl_spinand_manufacturer; 267 extern const struct spinand_manufacturer skyhigh_spinand_manufacturer; 268 extern const struct spinand_manufacturer gsto_spinand_manufacturer; 269 extern const struct spinand_manufacturer zbit_spinand_manufacturer; 270 271 /** 272 * struct spinand_op_variants - SPI NAND operation variants 273 * @ops: the list of variants for a given operation 274 * @nops: the number of variants 275 * 276 * Some operations like read-from-cache/write-to-cache have several variants 277 * depending on the number of IO lines you use to transfer data or address 278 * cycles. This structure is a way to describe the different variants supported 279 * by a chip and let the core pick the best one based on the SPI mem controller 280 * capabilities. 281 */ 282 struct spinand_op_variants { 283 const struct spi_mem_op *ops; 284 unsigned int nops; 285 }; 286 287 #define SPINAND_OP_VARIANTS(name, ...) \ 288 const struct spinand_op_variants name = { \ 289 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \ 290 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \ 291 sizeof(struct spi_mem_op), \ 292 } 293 294 /** 295 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND 296 * chip 297 * @get_status: get the ECC status. Should return a positive number encoding 298 * the number of corrected bitflips if correction was possible or 299 * -EBADMSG if there are uncorrectable errors. I can also return 300 * other negative error codes if the error is not caused by 301 * uncorrectable bitflips 302 * @ooblayout: the OOB layout used by the on-die ECC implementation 303 */ 304 struct spinand_ecc_info { 305 int (*get_status)(struct spinand_device *spinand, u8 status); 306 const struct mtd_ooblayout_ops *ooblayout; 307 }; 308 309 #define SPINAND_HAS_QE_BIT BIT(0) 310 311 /** 312 * struct spinand_info - Structure used to describe SPI NAND chips 313 * @model: model name 314 * @devid: device ID 315 * @flags: OR-ing of the SPINAND_XXX flags 316 * @memorg: memory organization 317 * @eccreq: ECC requirements 318 * @eccinfo: on-die ECC info 319 * @op_variants: operations variants 320 * @op_variants.read_cache: variants of the read-cache operation 321 * @op_variants.write_cache: variants of the write-cache operation 322 * @op_variants.update_cache: variants of the update-cache operation 323 * @select_target: function used to select a target/die. Required only for 324 * multi-die chips 325 * 326 * Each SPI NAND manufacturer driver should have a spinand_info table 327 * describing all the chips supported by the driver. 328 */ 329 struct spinand_info { 330 const char *model; 331 struct spinand_devid devid; 332 u32 flags; 333 struct nand_memory_organization memorg; 334 struct nand_ecc_req eccreq; 335 struct spinand_ecc_info eccinfo; 336 struct { 337 const struct spinand_op_variants *read_cache; 338 const struct spinand_op_variants *write_cache; 339 const struct spinand_op_variants *update_cache; 340 } op_variants; 341 int (*select_target)(struct spinand_device *spinand, 342 unsigned int target); 343 }; 344 345 #define SPINAND_ID(__method, ...) \ 346 { \ 347 .id = (const u8[]){ __VA_ARGS__ }, \ 348 .len = sizeof((u8[]){ __VA_ARGS__ }), \ 349 .method = __method, \ 350 } 351 352 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ 353 { \ 354 .read_cache = __read, \ 355 .write_cache = __write, \ 356 .update_cache = __update, \ 357 } 358 359 #define SPINAND_ECCINFO(__ooblayout, __get_status) \ 360 .eccinfo = { \ 361 .ooblayout = __ooblayout, \ 362 .get_status = __get_status, \ 363 } 364 365 #define SPINAND_SELECT_TARGET(__func) \ 366 .select_target = __func, 367 368 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ 369 __flags, ...) \ 370 { \ 371 .model = __model, \ 372 .devid = __id, \ 373 .memorg = __memorg, \ 374 .eccreq = __eccreq, \ 375 .op_variants = __op_variants, \ 376 .flags = __flags, \ 377 __VA_ARGS__ \ 378 } 379 380 /** 381 * struct spinand_device - SPI NAND device instance 382 * @base: NAND device instance 383 * @slave: pointer to the SPI slave object 384 * @lock: lock used to serialize accesses to the NAND 385 * @id: NAND ID as returned by READ_ID 386 * @flags: NAND flags 387 * @op_templates: various SPI mem op templates 388 * @op_templates.read_cache: read cache op template 389 * @op_templates.write_cache: write cache op template 390 * @op_templates.update_cache: update cache op template 391 * @select_target: select a specific target/die. Usually called before sending 392 * a command addressing a page or an eraseblock embedded in 393 * this die. Only required if your chip exposes several dies 394 * @cur_target: currently selected target/die 395 * @eccinfo: on-die ECC information 396 * @cfg_cache: config register cache. One entry per die 397 * @databuf: bounce buffer for data 398 * @oobbuf: bounce buffer for OOB data 399 * @scratchbuf: buffer used for everything but page accesses. This is needed 400 * because the spi-mem interface explicitly requests that buffers 401 * passed in spi_mem_op be DMA-able, so we can't based the bufs on 402 * the stack 403 * @manufacturer: SPI NAND manufacturer information 404 * @priv: manufacturer private data 405 */ 406 struct spinand_device { 407 struct nand_device base; 408 #ifndef __UBOOT__ 409 struct spi_mem *spimem; 410 struct mutex lock; 411 #else 412 struct spi_slave *slave; 413 #endif 414 struct spinand_id id; 415 u32 flags; 416 417 struct { 418 const struct spi_mem_op *read_cache; 419 const struct spi_mem_op *write_cache; 420 const struct spi_mem_op *update_cache; 421 } op_templates; 422 423 int (*select_target)(struct spinand_device *spinand, 424 unsigned int target); 425 unsigned int cur_target; 426 427 struct spinand_ecc_info eccinfo; 428 429 u8 *cfg_cache; 430 u8 *databuf; 431 u8 *oobbuf; 432 u8 *scratchbuf; 433 const struct spinand_manufacturer *manufacturer; 434 void *priv; 435 }; 436 437 /** 438 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance 439 * @mtd: MTD instance 440 * 441 * Return: the SPI NAND device attached to @mtd. 442 */ 443 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd) 444 { 445 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base); 446 } 447 448 /** 449 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device 450 * @spinand: SPI NAND device 451 * 452 * Return: the MTD device embedded in @spinand. 453 */ 454 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand) 455 { 456 return nanddev_to_mtd(&spinand->base); 457 } 458 459 /** 460 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object 461 * @nand: NAND object 462 * 463 * Return: the SPI NAND device embedding @nand. 464 */ 465 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand) 466 { 467 return container_of(nand, struct spinand_device, base); 468 } 469 470 /** 471 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object 472 * @spinand: SPI NAND device 473 * 474 * Return: the NAND device embedded in @spinand. 475 */ 476 static inline struct nand_device * 477 spinand_to_nand(struct spinand_device *spinand) 478 { 479 return &spinand->base; 480 } 481 482 /** 483 * spinand_set_of_node - Attach a DT node to a SPI NAND device 484 * @spinand: SPI NAND device 485 * @np: DT node 486 * 487 * Attach a DT node to a SPI NAND device. 488 */ 489 static inline void spinand_set_of_node(struct spinand_device *spinand, 490 const struct device_node *np) 491 { 492 nanddev_set_of_node(&spinand->base, np); 493 } 494 495 int spinand_match_and_init(struct spinand_device *spinand, 496 const struct spinand_info *table, 497 unsigned int table_size, 498 enum spinand_readid_method rdid_method); 499 500 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); 501 int spinand_select_target(struct spinand_device *spinand, unsigned int target); 502 503 #endif /* __LINUX_MTD_SPINAND_H */ 504