1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <peterpandong@micron.com> 7 */ 8 #ifndef __LINUX_MTD_SPINAND_H 9 #define __LINUX_MTD_SPINAND_H 10 11 #ifndef __UBOOT__ 12 #include <linux/mutex.h> 13 #include <linux/bitops.h> 14 #include <linux/device.h> 15 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/nand.h> 17 #include <linux/spi/spi.h> 18 #include <linux/spi/spi-mem.h> 19 #else 20 #include <common.h> 21 #include <spi.h> 22 #include <spi-mem.h> 23 #include <linux/mtd/nand.h> 24 #endif 25 26 /** 27 * Standard SPI NAND flash operations 28 */ 29 30 #define SPINAND_RESET_OP \ 31 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \ 32 SPI_MEM_OP_NO_ADDR, \ 33 SPI_MEM_OP_NO_DUMMY, \ 34 SPI_MEM_OP_NO_DATA) 35 36 #define SPINAND_WR_EN_DIS_OP(enable) \ 37 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ 38 SPI_MEM_OP_NO_ADDR, \ 39 SPI_MEM_OP_NO_DUMMY, \ 40 SPI_MEM_OP_NO_DATA) 41 42 #define SPINAND_READID_OP(naddr, ndummy, buf, len) \ 43 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ 44 SPI_MEM_OP_ADDR(naddr, 0, 1), \ 45 SPI_MEM_OP_DUMMY(ndummy, 1), \ 46 SPI_MEM_OP_DATA_IN(len, buf, 1)) 47 48 #define SPINAND_SET_FEATURE_OP(reg, valptr) \ 49 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ 50 SPI_MEM_OP_ADDR(1, reg, 1), \ 51 SPI_MEM_OP_NO_DUMMY, \ 52 SPI_MEM_OP_DATA_OUT(1, valptr, 1)) 53 54 #define SPINAND_GET_FEATURE_OP(reg, valptr) \ 55 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \ 56 SPI_MEM_OP_ADDR(1, reg, 1), \ 57 SPI_MEM_OP_NO_DUMMY, \ 58 SPI_MEM_OP_DATA_IN(1, valptr, 1)) 59 60 #define SPINAND_BLK_ERASE_OP(addr) \ 61 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \ 62 SPI_MEM_OP_ADDR(3, addr, 1), \ 63 SPI_MEM_OP_NO_DUMMY, \ 64 SPI_MEM_OP_NO_DATA) 65 66 #define SPINAND_PAGE_READ_OP(addr) \ 67 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \ 68 SPI_MEM_OP_ADDR(3, addr, 1), \ 69 SPI_MEM_OP_NO_DUMMY, \ 70 SPI_MEM_OP_NO_DATA) 71 72 #define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \ 73 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ 74 SPI_MEM_OP_ADDR(2, addr, 1), \ 75 SPI_MEM_OP_DUMMY(ndummy, 1), \ 76 SPI_MEM_OP_DATA_IN(len, buf, 1)) 77 78 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ 79 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 80 SPI_MEM_OP_ADDR(2, addr, 1), \ 81 SPI_MEM_OP_DUMMY(ndummy, 1), \ 82 SPI_MEM_OP_DATA_IN(len, buf, 2)) 83 84 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ 85 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 86 SPI_MEM_OP_ADDR(2, addr, 1), \ 87 SPI_MEM_OP_DUMMY(ndummy, 1), \ 88 SPI_MEM_OP_DATA_IN(len, buf, 4)) 89 90 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ 91 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 92 SPI_MEM_OP_ADDR(2, addr, 2), \ 93 SPI_MEM_OP_DUMMY(ndummy, 2), \ 94 SPI_MEM_OP_DATA_IN(len, buf, 2)) 95 96 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \ 97 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 98 SPI_MEM_OP_ADDR(2, addr, 4), \ 99 SPI_MEM_OP_DUMMY(ndummy, 4), \ 100 SPI_MEM_OP_DATA_IN(len, buf, 4)) 101 102 #define SPINAND_PROG_EXEC_OP(addr) \ 103 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ 104 SPI_MEM_OP_ADDR(3, addr, 1), \ 105 SPI_MEM_OP_NO_DUMMY, \ 106 SPI_MEM_OP_NO_DATA) 107 108 #define SPINAND_PROG_LOAD(reset, addr, buf, len) \ 109 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \ 110 SPI_MEM_OP_ADDR(2, addr, 1), \ 111 SPI_MEM_OP_NO_DUMMY, \ 112 SPI_MEM_OP_DATA_OUT(len, buf, 1)) 113 114 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \ 115 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \ 116 SPI_MEM_OP_ADDR(2, addr, 1), \ 117 SPI_MEM_OP_NO_DUMMY, \ 118 SPI_MEM_OP_DATA_OUT(len, buf, 4)) 119 120 /** 121 * Standard SPI NAND flash commands 122 */ 123 #define SPINAND_CMD_PROG_LOAD_X4 0x32 124 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34 125 126 /* feature register */ 127 #define REG_BLOCK_LOCK 0xa0 128 #define BL_ALL_UNLOCKED 0x00 129 130 /* configuration register */ 131 #define REG_CFG 0xb0 132 #define CFG_OTP_ENABLE BIT(6) 133 #define CFG_ECC_ENABLE BIT(4) 134 #define CFG_QUAD_ENABLE BIT(0) 135 136 /* status register */ 137 #define REG_STATUS 0xc0 138 #define STATUS_BUSY BIT(0) 139 #define STATUS_ERASE_FAILED BIT(2) 140 #define STATUS_PROG_FAILED BIT(3) 141 #define STATUS_ECC_MASK GENMASK(5, 4) 142 #define STATUS_ECC_NO_BITFLIPS (0 << 4) 143 #define STATUS_ECC_HAS_BITFLIPS (1 << 4) 144 #define STATUS_ECC_UNCOR_ERROR (2 << 4) 145 146 struct spinand_op; 147 struct spinand_device; 148 149 #define SPINAND_MAX_ID_LEN 4 150 151 /** 152 * struct spinand_id - SPI NAND id structure 153 * @data: buffer containing the id bytes. Currently 4 bytes large, but can 154 * be extended if required 155 * @len: ID length 156 */ 157 struct spinand_id { 158 u8 data[SPINAND_MAX_ID_LEN]; 159 int len; 160 }; 161 162 enum spinand_readid_method { 163 SPINAND_READID_METHOD_OPCODE, 164 SPINAND_READID_METHOD_OPCODE_ADDR, 165 SPINAND_READID_METHOD_OPCODE_DUMMY, 166 }; 167 168 /** 169 * struct spinand_devid - SPI NAND device id structure 170 * @id: device id of current chip 171 * @len: number of bytes in device id 172 * @method: method to read chip id 173 * There are 3 possible variants: 174 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately 175 * after read_id opcode. 176 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after 177 * read_id opcode + 1-byte address. 178 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after 179 * read_id opcode + 1 dummy byte. 180 */ 181 struct spinand_devid { 182 const u8 *id; 183 const u8 len; 184 const enum spinand_readid_method method; 185 }; 186 187 /** 188 * struct manufacurer_ops - SPI NAND manufacturer specific operations 189 * @init: initialize a SPI NAND device 190 * @cleanup: cleanup a SPI NAND device 191 * 192 * Each SPI NAND manufacturer driver should implement this interface so that 193 * NAND chips coming from this vendor can be initialized properly. 194 */ 195 struct spinand_manufacturer_ops { 196 int (*init)(struct spinand_device *spinand); 197 void (*cleanup)(struct spinand_device *spinand); 198 }; 199 200 /** 201 * struct spinand_manufacturer - SPI NAND manufacturer instance 202 * @id: manufacturer ID 203 * @name: manufacturer name 204 * @devid_len: number of bytes in device ID 205 * @chips: supported SPI NANDs under current manufacturer 206 * @nchips: number of SPI NANDs available in chips array 207 * @ops: manufacturer operations 208 */ 209 struct spinand_manufacturer { 210 u8 id; 211 char *name; 212 const struct spinand_info *chips; 213 const size_t nchips; 214 const struct spinand_manufacturer_ops *ops; 215 }; 216 217 /* SPI NAND manufacturers */ 218 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; 219 extern const struct spinand_manufacturer macronix_spinand_manufacturer; 220 extern const struct spinand_manufacturer micron_spinand_manufacturer; 221 extern const struct spinand_manufacturer toshiba_spinand_manufacturer; 222 extern const struct spinand_manufacturer winbond_spinand_manufacturer; 223 extern const struct spinand_manufacturer dosilicon_spinand_manufacturer; 224 extern const struct spinand_manufacturer esmt_spinand_manufacturer; 225 extern const struct spinand_manufacturer xtx_spinand_manufacturer; 226 extern const struct spinand_manufacturer hyf_spinand_manufacturer; 227 extern const struct spinand_manufacturer fmsh_spinand_manufacturer; 228 extern const struct spinand_manufacturer foresee_spinand_manufacturer; 229 extern const struct spinand_manufacturer biwin_spinand_manufacturer; 230 extern const struct spinand_manufacturer etron_spinand_manufacturer; 231 extern const struct spinand_manufacturer jsc_spinand_manufacturer; 232 extern const struct spinand_manufacturer silicongo_spinand_manufacturer; 233 extern const struct spinand_manufacturer unim_spinand_manufacturer; 234 235 /** 236 * struct spinand_op_variants - SPI NAND operation variants 237 * @ops: the list of variants for a given operation 238 * @nops: the number of variants 239 * 240 * Some operations like read-from-cache/write-to-cache have several variants 241 * depending on the number of IO lines you use to transfer data or address 242 * cycles. This structure is a way to describe the different variants supported 243 * by a chip and let the core pick the best one based on the SPI mem controller 244 * capabilities. 245 */ 246 struct spinand_op_variants { 247 const struct spi_mem_op *ops; 248 unsigned int nops; 249 }; 250 251 #define SPINAND_OP_VARIANTS(name, ...) \ 252 const struct spinand_op_variants name = { \ 253 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \ 254 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \ 255 sizeof(struct spi_mem_op), \ 256 } 257 258 /** 259 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND 260 * chip 261 * @get_status: get the ECC status. Should return a positive number encoding 262 * the number of corrected bitflips if correction was possible or 263 * -EBADMSG if there are uncorrectable errors. I can also return 264 * other negative error codes if the error is not caused by 265 * uncorrectable bitflips 266 * @ooblayout: the OOB layout used by the on-die ECC implementation 267 */ 268 struct spinand_ecc_info { 269 int (*get_status)(struct spinand_device *spinand, u8 status); 270 const struct mtd_ooblayout_ops *ooblayout; 271 }; 272 273 #define SPINAND_HAS_QE_BIT BIT(0) 274 275 /** 276 * struct spinand_info - Structure used to describe SPI NAND chips 277 * @model: model name 278 * @devid: device ID 279 * @flags: OR-ing of the SPINAND_XXX flags 280 * @memorg: memory organization 281 * @eccreq: ECC requirements 282 * @eccinfo: on-die ECC info 283 * @op_variants: operations variants 284 * @op_variants.read_cache: variants of the read-cache operation 285 * @op_variants.write_cache: variants of the write-cache operation 286 * @op_variants.update_cache: variants of the update-cache operation 287 * @select_target: function used to select a target/die. Required only for 288 * multi-die chips 289 * 290 * Each SPI NAND manufacturer driver should have a spinand_info table 291 * describing all the chips supported by the driver. 292 */ 293 struct spinand_info { 294 const char *model; 295 struct spinand_devid devid; 296 u32 flags; 297 struct nand_memory_organization memorg; 298 struct nand_ecc_req eccreq; 299 struct spinand_ecc_info eccinfo; 300 struct { 301 const struct spinand_op_variants *read_cache; 302 const struct spinand_op_variants *write_cache; 303 const struct spinand_op_variants *update_cache; 304 } op_variants; 305 int (*select_target)(struct spinand_device *spinand, 306 unsigned int target); 307 }; 308 309 #define SPINAND_ID(__method, ...) \ 310 { \ 311 .id = (const u8[]){ __VA_ARGS__ }, \ 312 .len = sizeof((u8[]){ __VA_ARGS__ }), \ 313 .method = __method, \ 314 } 315 316 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ 317 { \ 318 .read_cache = __read, \ 319 .write_cache = __write, \ 320 .update_cache = __update, \ 321 } 322 323 #define SPINAND_ECCINFO(__ooblayout, __get_status) \ 324 .eccinfo = { \ 325 .ooblayout = __ooblayout, \ 326 .get_status = __get_status, \ 327 } 328 329 #define SPINAND_SELECT_TARGET(__func) \ 330 .select_target = __func, 331 332 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ 333 __flags, ...) \ 334 { \ 335 .model = __model, \ 336 .devid = __id, \ 337 .memorg = __memorg, \ 338 .eccreq = __eccreq, \ 339 .op_variants = __op_variants, \ 340 .flags = __flags, \ 341 __VA_ARGS__ \ 342 } 343 344 /** 345 * struct spinand_device - SPI NAND device instance 346 * @base: NAND device instance 347 * @slave: pointer to the SPI slave object 348 * @lock: lock used to serialize accesses to the NAND 349 * @id: NAND ID as returned by READ_ID 350 * @flags: NAND flags 351 * @op_templates: various SPI mem op templates 352 * @op_templates.read_cache: read cache op template 353 * @op_templates.write_cache: write cache op template 354 * @op_templates.update_cache: update cache op template 355 * @select_target: select a specific target/die. Usually called before sending 356 * a command addressing a page or an eraseblock embedded in 357 * this die. Only required if your chip exposes several dies 358 * @cur_target: currently selected target/die 359 * @eccinfo: on-die ECC information 360 * @cfg_cache: config register cache. One entry per die 361 * @databuf: bounce buffer for data 362 * @oobbuf: bounce buffer for OOB data 363 * @scratchbuf: buffer used for everything but page accesses. This is needed 364 * because the spi-mem interface explicitly requests that buffers 365 * passed in spi_mem_op be DMA-able, so we can't based the bufs on 366 * the stack 367 * @manufacturer: SPI NAND manufacturer information 368 * @priv: manufacturer private data 369 */ 370 struct spinand_device { 371 struct nand_device base; 372 #ifndef __UBOOT__ 373 struct spi_mem *spimem; 374 struct mutex lock; 375 #else 376 struct spi_slave *slave; 377 #endif 378 struct spinand_id id; 379 u32 flags; 380 381 struct { 382 const struct spi_mem_op *read_cache; 383 const struct spi_mem_op *write_cache; 384 const struct spi_mem_op *update_cache; 385 } op_templates; 386 387 int (*select_target)(struct spinand_device *spinand, 388 unsigned int target); 389 unsigned int cur_target; 390 391 struct spinand_ecc_info eccinfo; 392 393 u8 *cfg_cache; 394 u8 *databuf; 395 u8 *oobbuf; 396 u8 *scratchbuf; 397 const struct spinand_manufacturer *manufacturer; 398 void *priv; 399 }; 400 401 /** 402 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance 403 * @mtd: MTD instance 404 * 405 * Return: the SPI NAND device attached to @mtd. 406 */ 407 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd) 408 { 409 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base); 410 } 411 412 /** 413 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device 414 * @spinand: SPI NAND device 415 * 416 * Return: the MTD device embedded in @spinand. 417 */ 418 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand) 419 { 420 return nanddev_to_mtd(&spinand->base); 421 } 422 423 /** 424 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object 425 * @nand: NAND object 426 * 427 * Return: the SPI NAND device embedding @nand. 428 */ 429 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand) 430 { 431 return container_of(nand, struct spinand_device, base); 432 } 433 434 /** 435 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object 436 * @spinand: SPI NAND device 437 * 438 * Return: the NAND device embedded in @spinand. 439 */ 440 static inline struct nand_device * 441 spinand_to_nand(struct spinand_device *spinand) 442 { 443 return &spinand->base; 444 } 445 446 /** 447 * spinand_set_of_node - Attach a DT node to a SPI NAND device 448 * @spinand: SPI NAND device 449 * @np: DT node 450 * 451 * Attach a DT node to a SPI NAND device. 452 */ 453 static inline void spinand_set_of_node(struct spinand_device *spinand, 454 const struct device_node *np) 455 { 456 nanddev_set_of_node(&spinand->base, np); 457 } 458 459 int spinand_match_and_init(struct spinand_device *spinand, 460 const struct spinand_info *table, 461 unsigned int table_size, 462 enum spinand_readid_method rdid_method); 463 464 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); 465 int spinand_select_target(struct spinand_device *spinand, unsigned int target); 466 467 #endif /* __LINUX_MTD_SPINAND_H */ 468