1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2014 Freescale Semiconductor, Inc. 4 * Synced from Linux v4.19 5 */ 6 7 #ifndef __LINUX_MTD_SPI_NOR_H 8 #define __LINUX_MTD_SPI_NOR_H 9 10 #include <linux/bitops.h> 11 #include <linux/mtd/cfi.h> 12 #include <linux/mtd/mtd.h> 13 14 /* 15 * Manufacturer IDs 16 * 17 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID. 18 * Sometimes these are the same as CFI IDs, but sometimes they aren't. 19 */ 20 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL 21 #define SNOR_MFR_GIGADEVICE 0xc8 22 #define SNOR_MFR_INTEL CFI_MFR_INTEL 23 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */ 24 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */ 25 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX 26 #define SNOR_MFR_SPANSION CFI_MFR_AMD 27 #define SNOR_MFR_SST CFI_MFR_SST 28 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ 29 30 /* 31 * Note on opcode nomenclature: some opcodes have a format like 32 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number 33 * of I/O lines used for the opcode, address, and data (respectively). The 34 * FUNCTION has an optional suffix of '4', to represent an opcode which 35 * requires a 4-byte (32-bit) address. 36 */ 37 38 /* Flash opcodes. */ 39 #define SPINOR_OP_WREN 0x06 /* Write enable */ 40 #define SPINOR_OP_RDSR 0x05 /* Read status register */ 41 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ 42 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */ 43 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */ 44 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ 45 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ 46 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ 47 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ 48 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ 49 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ 50 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ 51 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */ 52 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */ 53 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ 54 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ 55 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ 56 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ 57 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ 58 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ 59 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ 60 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ 61 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ 62 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ 63 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ 64 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ 65 66 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ 67 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ 68 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */ 69 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */ 70 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ 71 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ 72 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ 73 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ 74 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ 75 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ 76 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */ 77 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */ 78 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ 79 80 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ 81 #define SPINOR_OP_READ_1_1_1_DTR 0x0d 82 #define SPINOR_OP_READ_1_2_2_DTR 0xbd 83 #define SPINOR_OP_READ_1_4_4_DTR 0xed 84 85 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e 86 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe 87 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee 88 89 /* Used for SST flashes only. */ 90 #define SPINOR_OP_BP 0x02 /* Byte program */ 91 #define SPINOR_OP_WRDI 0x04 /* Write disable */ 92 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ 93 94 /* Used for S3AN flashes only */ 95 #define SPINOR_OP_XSE 0x50 /* Sector erase */ 96 #define SPINOR_OP_XPP 0x82 /* Page program */ 97 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */ 98 99 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ 100 #define XSR_RDY BIT(7) /* Ready */ 101 102 /* Used for Macronix and Winbond flashes. */ 103 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ 104 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ 105 106 /* Used for Spansion flashes only. */ 107 #define SPINOR_OP_BRWR 0x17 /* Bank register write */ 108 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ 109 110 /* Used for Micron flashes only. */ 111 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ 112 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ 113 114 /* Status Register bits. */ 115 #define SR_WIP BIT(0) /* Write in progress */ 116 #define SR_WEL BIT(1) /* Write enable latch */ 117 /* meaning of other SR_* bits may differ between vendors */ 118 #define SR_BP0 BIT(2) /* Block protect 0 */ 119 #define SR_BP1 BIT(3) /* Block protect 1 */ 120 #define SR_BP2 BIT(4) /* Block protect 2 */ 121 #define SR_TB BIT(5) /* Top/Bottom protect */ 122 #define SR_SRWD BIT(7) /* SR write protect */ 123 /* Spansion/Cypress specific status bits */ 124 #define SR_E_ERR BIT(5) 125 #define SR_P_ERR BIT(6) 126 127 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ 128 129 /* Enhanced Volatile Configuration Register bits */ 130 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ 131 132 /* Flag Status Register bits */ 133 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ 134 #define FSR_E_ERR BIT(5) /* Erase operation status */ 135 #define FSR_P_ERR BIT(4) /* Program operation status */ 136 #define FSR_PT_ERR BIT(1) /* Protection error bit */ 137 138 /* Configuration Register bits. */ 139 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ 140 141 /* Status Register 2 bits. */ 142 #define SR2_QUAD_EN_BIT7 BIT(7) 143 144 /* Supported SPI protocols */ 145 #define SNOR_PROTO_INST_MASK GENMASK(23, 16) 146 #define SNOR_PROTO_INST_SHIFT 16 147 #define SNOR_PROTO_INST(_nbits) \ 148 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \ 149 SNOR_PROTO_INST_MASK) 150 151 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8) 152 #define SNOR_PROTO_ADDR_SHIFT 8 153 #define SNOR_PROTO_ADDR(_nbits) \ 154 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \ 155 SNOR_PROTO_ADDR_MASK) 156 157 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0) 158 #define SNOR_PROTO_DATA_SHIFT 0 159 #define SNOR_PROTO_DATA(_nbits) \ 160 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \ 161 SNOR_PROTO_DATA_MASK) 162 163 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ 164 165 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ 166 (SNOR_PROTO_INST(_inst_nbits) | \ 167 SNOR_PROTO_ADDR(_addr_nbits) | \ 168 SNOR_PROTO_DATA(_data_nbits)) 169 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \ 170 (SNOR_PROTO_IS_DTR | \ 171 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)) 172 173 enum spi_nor_protocol { 174 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1), 175 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2), 176 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4), 177 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8), 178 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2), 179 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4), 180 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8), 181 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2), 182 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4), 183 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8), 184 185 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1), 186 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2), 187 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4), 188 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8), 189 }; 190 191 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) 192 { 193 return !!(proto & SNOR_PROTO_IS_DTR); 194 } 195 196 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto) 197 { 198 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >> 199 SNOR_PROTO_INST_SHIFT; 200 } 201 202 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto) 203 { 204 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >> 205 SNOR_PROTO_ADDR_SHIFT; 206 } 207 208 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto) 209 { 210 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >> 211 SNOR_PROTO_DATA_SHIFT; 212 } 213 214 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto) 215 { 216 return spi_nor_get_protocol_data_nbits(proto); 217 } 218 219 #define SPI_NOR_MAX_CMD_SIZE 8 220 enum spi_nor_ops { 221 SPI_NOR_OPS_READ = 0, 222 SPI_NOR_OPS_WRITE, 223 SPI_NOR_OPS_ERASE, 224 SPI_NOR_OPS_LOCK, 225 SPI_NOR_OPS_UNLOCK, 226 }; 227 228 enum spi_nor_option_flags { 229 SNOR_F_USE_FSR = BIT(0), 230 SNOR_F_HAS_SR_TB = BIT(1), 231 SNOR_F_NO_OP_CHIP_ERASE = BIT(2), 232 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3), 233 SNOR_F_READY_XSR_RDY = BIT(4), 234 SNOR_F_USE_CLSR = BIT(5), 235 SNOR_F_BROKEN_RESET = BIT(6), 236 }; 237 238 /** 239 * struct flash_info - Forward declaration of a structure used internally by 240 * spi_nor_scan() 241 */ 242 struct flash_info; 243 244 /* TODO: Remove, once all users of spi_flash interface are moved to MTD */ 245 #define spi_flash spi_nor 246 247 /** 248 * struct spi_nor - Structure for defining a the SPI NOR layer 249 * @mtd: point to a mtd_info structure 250 * @lock: the lock for the read/write/erase/lock/unlock operations 251 * @dev: point to a spi device, or a spi nor controller device. 252 * @info: spi-nor part JDEC MFR id and other info 253 * @page_size: the page size of the SPI NOR 254 * @addr_width: number of address bytes 255 * @erase_opcode: the opcode for erasing a sector 256 * @read_opcode: the read opcode 257 * @read_dummy: the dummy needed by the read operation 258 * @program_opcode: the program opcode 259 * @sst_write_second: used by the SST write operation 260 * @flags: flag options for the current SPI-NOR (SNOR_F_*) 261 * @read_proto: the SPI protocol for read operations 262 * @write_proto: the SPI protocol for write operations 263 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations 264 * @cmd_buf: used by the write_reg 265 * @prepare: [OPTIONAL] do some preparations for the 266 * read/write/erase/lock/unlock operations 267 * @unprepare: [OPTIONAL] do some post work after the 268 * read/write/erase/lock/unlock operations 269 * @read_reg: [DRIVER-SPECIFIC] read out the register 270 * @write_reg: [DRIVER-SPECIFIC] write data to the register 271 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR 272 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR 273 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR 274 * at the offset @offs; if not provided by the driver, 275 * spi-nor will send the erase opcode via write_reg() 276 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR 277 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR 278 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is 279 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode 280 * completely locked 281 * @priv: the private data 282 */ 283 struct spi_nor { 284 struct mtd_info mtd; 285 struct udevice *dev; 286 struct spi_slave *spi; 287 const struct flash_info *info; 288 u32 page_size; 289 u8 addr_width; 290 u8 erase_opcode; 291 u8 read_opcode; 292 u8 read_dummy; 293 u8 program_opcode; 294 enum spi_nor_protocol read_proto; 295 enum spi_nor_protocol write_proto; 296 enum spi_nor_protocol reg_proto; 297 bool sst_write_second; 298 u32 flags; 299 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; 300 301 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); 302 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); 303 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 304 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 305 306 ssize_t (*read)(struct spi_nor *nor, loff_t from, 307 size_t len, u_char *read_buf); 308 ssize_t (*write)(struct spi_nor *nor, loff_t to, 309 size_t len, const u_char *write_buf); 310 int (*erase)(struct spi_nor *nor, loff_t offs); 311 312 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 313 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 314 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); 315 int (*quad_enable)(struct spi_nor *nor); 316 317 void *priv; 318 /* Compatibility for spi_flash, remove once sf layer is merged with mtd */ 319 const char *name; 320 u32 size; 321 u32 sector_size; 322 u32 erase_size; 323 }; 324 325 static inline void spi_nor_set_flash_node(struct spi_nor *nor, 326 const struct device_node *np) 327 { 328 mtd_set_of_node(&nor->mtd, np); 329 } 330 331 static inline const struct 332 device_node *spi_nor_get_flash_node(struct spi_nor *nor) 333 { 334 return mtd_get_of_node(&nor->mtd); 335 } 336 337 /** 338 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies 339 * supported by the SPI controller (bus master). 340 * @mask: the bitmask listing all the supported hw capabilies 341 */ 342 struct spi_nor_hwcaps { 343 u32 mask; 344 }; 345 346 /* 347 *(Fast) Read capabilities. 348 * MUST be ordered by priority: the higher bit position, the higher priority. 349 * As a matter of performances, it is relevant to use Octo SPI protocols first, 350 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly 351 * (Slow) Read. 352 */ 353 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) 354 #define SNOR_HWCAPS_READ BIT(0) 355 #define SNOR_HWCAPS_READ_FAST BIT(1) 356 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) 357 358 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3) 359 #define SNOR_HWCAPS_READ_1_1_2 BIT(3) 360 #define SNOR_HWCAPS_READ_1_2_2 BIT(4) 361 #define SNOR_HWCAPS_READ_2_2_2 BIT(5) 362 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) 363 364 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7) 365 #define SNOR_HWCAPS_READ_1_1_4 BIT(7) 366 #define SNOR_HWCAPS_READ_1_4_4 BIT(8) 367 #define SNOR_HWCAPS_READ_4_4_4 BIT(9) 368 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) 369 370 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11) 371 #define SNOR_HWCAPS_READ_1_1_8 BIT(11) 372 #define SNOR_HWCAPS_READ_1_8_8 BIT(12) 373 #define SNOR_HWCAPS_READ_8_8_8 BIT(13) 374 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) 375 376 /* 377 * Page Program capabilities. 378 * MUST be ordered by priority: the higher bit position, the higher priority. 379 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the 380 * legacy SPI 1-1-1 protocol. 381 * Note that Dual Page Programs are not supported because there is no existing 382 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory 383 * implements such commands. 384 */ 385 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) 386 #define SNOR_HWCAPS_PP BIT(16) 387 388 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) 389 #define SNOR_HWCAPS_PP_1_1_4 BIT(17) 390 #define SNOR_HWCAPS_PP_1_4_4 BIT(18) 391 #define SNOR_HWCAPS_PP_4_4_4 BIT(19) 392 393 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20) 394 #define SNOR_HWCAPS_PP_1_1_8 BIT(20) 395 #define SNOR_HWCAPS_PP_1_8_8 BIT(21) 396 #define SNOR_HWCAPS_PP_8_8_8 BIT(22) 397 398 /** 399 * spi_nor_scan() - scan the SPI NOR 400 * @nor: the spi_nor structure 401 * 402 * The drivers can use this function to scan the SPI NOR. 403 * In the scanning, it will try to get all the necessary information to 404 * fill the mtd_info{} and the spi_nor{}. 405 * 406 * Return: 0 for success, others for failure. 407 */ 408 int spi_nor_scan(struct spi_nor *nor); 409 410 #endif 411