1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_NAND_H 17 #define __LINUX_MTD_NAND_H 18 19 #include <config.h> 20 21 #include <linux/compat.h> 22 #include <linux/mtd/mtd.h> 23 #include <linux/mtd/flashchip.h> 24 #include <linux/mtd/bbm.h> 25 26 struct mtd_info; 27 struct nand_flash_dev; 28 struct device_node; 29 30 /* Scan and identify a NAND device */ 31 extern int nand_scan(struct mtd_info *mtd, int max_chips); 32 /* 33 * Separate phases of nand_scan(), allowing board driver to intervene 34 * and override command or ECC setup according to flash type. 35 */ 36 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 37 struct nand_flash_dev *table); 38 extern int nand_scan_tail(struct mtd_info *mtd); 39 40 /* Free resources held by the NAND device */ 41 extern void nand_release(struct mtd_info *mtd); 42 43 /* Internal helper for board drivers which need to override command function */ 44 extern void nand_wait_ready(struct mtd_info *mtd); 45 46 /* 47 * This constant declares the max. oobsize / page, which 48 * is supported now. If you add a chip with bigger oobsize/page 49 * adjust this accordingly. 50 */ 51 #define NAND_MAX_OOBSIZE 1664 52 #define NAND_MAX_PAGESIZE 16384 53 54 /* 55 * Constants for hardware specific CLE/ALE/NCE function 56 * 57 * These are bits which can be or'ed to set/clear multiple 58 * bits in one go. 59 */ 60 /* Select the chip by setting nCE to low */ 61 #define NAND_NCE 0x01 62 /* Select the command latch by setting CLE to high */ 63 #define NAND_CLE 0x02 64 /* Select the address latch by setting ALE to high */ 65 #define NAND_ALE 0x04 66 67 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 68 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 69 #define NAND_CTRL_CHANGE 0x80 70 71 /* 72 * Standard NAND flash commands 73 */ 74 #define NAND_CMD_READ0 0 75 #define NAND_CMD_READ1 1 76 #define NAND_CMD_RNDOUT 5 77 #define NAND_CMD_PAGEPROG 0x10 78 #define NAND_CMD_READOOB 0x50 79 #define NAND_CMD_ERASE1 0x60 80 #define NAND_CMD_STATUS 0x70 81 #define NAND_CMD_SEQIN 0x80 82 #define NAND_CMD_RNDIN 0x85 83 #define NAND_CMD_READID 0x90 84 #define NAND_CMD_ERASE2 0xd0 85 #define NAND_CMD_PARAM 0xec 86 #define NAND_CMD_GET_FEATURES 0xee 87 #define NAND_CMD_SET_FEATURES 0xef 88 #define NAND_CMD_RESET 0xff 89 90 #define NAND_CMD_LOCK 0x2a 91 #define NAND_CMD_UNLOCK1 0x23 92 #define NAND_CMD_UNLOCK2 0x24 93 94 /* Extended commands for large page devices */ 95 #define NAND_CMD_READSTART 0x30 96 #define NAND_CMD_RNDOUTSTART 0xE0 97 #define NAND_CMD_CACHEDPROG 0x15 98 99 /* Extended commands for AG-AND device */ 100 /* 101 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 102 * there is no way to distinguish that from NAND_CMD_READ0 103 * until the remaining sequence of commands has been completed 104 * so add a high order bit and mask it off in the command. 105 */ 106 #define NAND_CMD_DEPLETE1 0x100 107 #define NAND_CMD_DEPLETE2 0x38 108 #define NAND_CMD_STATUS_MULTI 0x71 109 #define NAND_CMD_STATUS_ERROR 0x72 110 /* multi-bank error status (banks 0-3) */ 111 #define NAND_CMD_STATUS_ERROR0 0x73 112 #define NAND_CMD_STATUS_ERROR1 0x74 113 #define NAND_CMD_STATUS_ERROR2 0x75 114 #define NAND_CMD_STATUS_ERROR3 0x76 115 #define NAND_CMD_STATUS_RESET 0x7f 116 #define NAND_CMD_STATUS_CLEAR 0xff 117 118 #define NAND_CMD_NONE -1 119 120 /* Status bits */ 121 #define NAND_STATUS_FAIL 0x01 122 #define NAND_STATUS_FAIL_N1 0x02 123 #define NAND_STATUS_TRUE_READY 0x20 124 #define NAND_STATUS_READY 0x40 125 #define NAND_STATUS_WP 0x80 126 127 #define NAND_DATA_IFACE_CHECK_ONLY -1 128 129 /* 130 * Constants for ECC_MODES 131 */ 132 typedef enum { 133 NAND_ECC_NONE, 134 NAND_ECC_SOFT, 135 NAND_ECC_HW, 136 NAND_ECC_HW_SYNDROME, 137 NAND_ECC_HW_OOB_FIRST, 138 NAND_ECC_SOFT_BCH, 139 } nand_ecc_modes_t; 140 141 /* 142 * Constants for Hardware ECC 143 */ 144 /* Reset Hardware ECC for read */ 145 #define NAND_ECC_READ 0 146 /* Reset Hardware ECC for write */ 147 #define NAND_ECC_WRITE 1 148 /* Enable Hardware ECC before syndrome is read back from flash */ 149 #define NAND_ECC_READSYN 2 150 151 /* 152 * Enable generic NAND 'page erased' check. This check is only done when 153 * ecc.correct() returns -EBADMSG. 154 * Set this flag if your implementation does not fix bitflips in erased 155 * pages and you want to rely on the default implementation. 156 */ 157 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 158 #define NAND_ECC_MAXIMIZE BIT(1) 159 /* 160 * If your controller already sends the required NAND commands when 161 * reading or writing a page, then the framework is not supposed to 162 * send READ0 and SEQIN/PAGEPROG respectively. 163 */ 164 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) 165 166 /* Bit mask for flags passed to do_nand_read_ecc */ 167 #define NAND_GET_DEVICE 0x80 168 169 170 /* 171 * Option constants for bizarre disfunctionality and real 172 * features. 173 */ 174 /* Buswidth is 16 bit */ 175 #define NAND_BUSWIDTH_16 0x00000002 176 /* Device supports partial programming without padding */ 177 #define NAND_NO_PADDING 0x00000004 178 /* Chip has cache program function */ 179 #define NAND_CACHEPRG 0x00000008 180 /* Chip has copy back function */ 181 #define NAND_COPYBACK 0x00000010 182 /* 183 * Chip requires ready check on read (for auto-incremented sequential read). 184 * True only for small page devices; large page devices do not support 185 * autoincrement. 186 */ 187 #define NAND_NEED_READRDY 0x00000100 188 189 /* Chip does not allow subpage writes */ 190 #define NAND_NO_SUBPAGE_WRITE 0x00000200 191 192 /* Device is one of 'new' xD cards that expose fake nand command set */ 193 #define NAND_BROKEN_XD 0x00000400 194 195 /* Device behaves just like nand, but is readonly */ 196 #define NAND_ROM 0x00000800 197 198 /* Device supports subpage reads */ 199 #define NAND_SUBPAGE_READ 0x00001000 200 201 /* 202 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 203 * patterns. 204 */ 205 #define NAND_NEED_SCRAMBLING 0x00002000 206 207 /* Device needs 3rd row address cycle */ 208 #define NAND_ROW_ADDR_3 0x00004000 209 210 /* Options valid for Samsung large page devices */ 211 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 212 213 /* Macros to identify the above */ 214 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 215 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 216 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 217 218 /* Non chip related options */ 219 /* This option skips the bbt scan during initialization. */ 220 #define NAND_SKIP_BBTSCAN 0x00010000 221 /* 222 * This option is defined if the board driver allocates its own buffers 223 * (e.g. because it needs them DMA-coherent). 224 */ 225 #define NAND_OWN_BUFFERS 0x00020000 226 /* Chip may not exist, so silence any errors in scan */ 227 #define NAND_SCAN_SILENT_NODEV 0x00040000 228 /* 229 * Autodetect nand buswidth with readid/onfi. 230 * This suppose the driver will configure the hardware in 8 bits mode 231 * when calling nand_scan_ident, and update its configuration 232 * before calling nand_scan_tail. 233 */ 234 #define NAND_BUSWIDTH_AUTO 0x00080000 235 /* 236 * This option could be defined by controller drivers to protect against 237 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 238 */ 239 #define NAND_USE_BOUNCE_BUFFER 0x00100000 240 241 /* Options set by nand scan */ 242 /* bbt has already been read */ 243 #define NAND_BBT_SCANNED 0x40000000 244 /* Nand scan has allocated controller struct */ 245 #define NAND_CONTROLLER_ALLOC 0x80000000 246 247 /* Cell info constants */ 248 #define NAND_CI_CHIPNR_MSK 0x03 249 #define NAND_CI_CELLTYPE_MSK 0x0C 250 #define NAND_CI_CELLTYPE_SHIFT 2 251 252 /* Keep gcc happy */ 253 struct nand_chip; 254 255 /* ONFI features */ 256 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 257 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 258 259 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 260 #define ONFI_TIMING_MODE_0 (1 << 0) 261 #define ONFI_TIMING_MODE_1 (1 << 1) 262 #define ONFI_TIMING_MODE_2 (1 << 2) 263 #define ONFI_TIMING_MODE_3 (1 << 3) 264 #define ONFI_TIMING_MODE_4 (1 << 4) 265 #define ONFI_TIMING_MODE_5 (1 << 5) 266 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 267 268 /* ONFI feature address */ 269 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 270 271 /* Vendor-specific feature address (Micron) */ 272 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 273 274 /* ONFI subfeature parameters length */ 275 #define ONFI_SUBFEATURE_PARAM_LEN 4 276 277 /* ONFI optional commands SET/GET FEATURES supported? */ 278 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 279 280 struct nand_onfi_params { 281 /* rev info and features block */ 282 /* 'O' 'N' 'F' 'I' */ 283 u8 sig[4]; 284 __le16 revision; 285 __le16 features; 286 __le16 opt_cmd; 287 u8 reserved0[2]; 288 __le16 ext_param_page_length; /* since ONFI 2.1 */ 289 u8 num_of_param_pages; /* since ONFI 2.1 */ 290 u8 reserved1[17]; 291 292 /* manufacturer information block */ 293 char manufacturer[12]; 294 char model[20]; 295 u8 jedec_id; 296 __le16 date_code; 297 u8 reserved2[13]; 298 299 /* memory organization block */ 300 __le32 byte_per_page; 301 __le16 spare_bytes_per_page; 302 __le32 data_bytes_per_ppage; 303 __le16 spare_bytes_per_ppage; 304 __le32 pages_per_block; 305 __le32 blocks_per_lun; 306 u8 lun_count; 307 u8 addr_cycles; 308 u8 bits_per_cell; 309 __le16 bb_per_lun; 310 __le16 block_endurance; 311 u8 guaranteed_good_blocks; 312 __le16 guaranteed_block_endurance; 313 u8 programs_per_page; 314 u8 ppage_attr; 315 u8 ecc_bits; 316 u8 interleaved_bits; 317 u8 interleaved_ops; 318 u8 reserved3[13]; 319 320 /* electrical parameter block */ 321 u8 io_pin_capacitance_max; 322 __le16 async_timing_mode; 323 __le16 program_cache_timing_mode; 324 __le16 t_prog; 325 __le16 t_bers; 326 __le16 t_r; 327 __le16 t_ccs; 328 __le16 src_sync_timing_mode; 329 u8 src_ssync_features; 330 __le16 clk_pin_capacitance_typ; 331 __le16 io_pin_capacitance_typ; 332 __le16 input_pin_capacitance_typ; 333 u8 input_pin_capacitance_max; 334 u8 driver_strength_support; 335 __le16 t_int_r; 336 __le16 t_adl; 337 u8 reserved4[8]; 338 339 /* vendor */ 340 __le16 vendor_revision; 341 u8 vendor[88]; 342 343 __le16 crc; 344 } __packed; 345 346 #define ONFI_CRC_BASE 0x4F4E 347 348 /* Extended ECC information Block Definition (since ONFI 2.1) */ 349 struct onfi_ext_ecc_info { 350 u8 ecc_bits; 351 u8 codeword_size; 352 __le16 bb_per_lun; 353 __le16 block_endurance; 354 u8 reserved[2]; 355 } __packed; 356 357 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 358 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 359 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 360 struct onfi_ext_section { 361 u8 type; 362 u8 length; 363 } __packed; 364 365 #define ONFI_EXT_SECTION_MAX 8 366 367 /* Extended Parameter Page Definition (since ONFI 2.1) */ 368 struct onfi_ext_param_page { 369 __le16 crc; 370 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 371 u8 reserved0[10]; 372 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 373 374 /* 375 * The actual size of the Extended Parameter Page is in 376 * @ext_param_page_length of nand_onfi_params{}. 377 * The following are the variable length sections. 378 * So we do not add any fields below. Please see the ONFI spec. 379 */ 380 } __packed; 381 382 struct nand_onfi_vendor_micron { 383 u8 two_plane_read; 384 u8 read_cache; 385 u8 read_unique_id; 386 u8 dq_imped; 387 u8 dq_imped_num_settings; 388 u8 dq_imped_feat_addr; 389 u8 rb_pulldown_strength; 390 u8 rb_pulldown_strength_feat_addr; 391 u8 rb_pulldown_strength_num_settings; 392 u8 otp_mode; 393 u8 otp_page_start; 394 u8 otp_data_prot_addr; 395 u8 otp_num_pages; 396 u8 otp_feat_addr; 397 u8 read_retry_options; 398 u8 reserved[72]; 399 u8 param_revision; 400 } __packed; 401 402 struct jedec_ecc_info { 403 u8 ecc_bits; 404 u8 codeword_size; 405 __le16 bb_per_lun; 406 __le16 block_endurance; 407 u8 reserved[2]; 408 } __packed; 409 410 /* JEDEC features */ 411 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 412 413 struct nand_jedec_params { 414 /* rev info and features block */ 415 /* 'J' 'E' 'S' 'D' */ 416 u8 sig[4]; 417 __le16 revision; 418 __le16 features; 419 u8 opt_cmd[3]; 420 __le16 sec_cmd; 421 u8 num_of_param_pages; 422 u8 reserved0[18]; 423 424 /* manufacturer information block */ 425 char manufacturer[12]; 426 char model[20]; 427 u8 jedec_id[6]; 428 u8 reserved1[10]; 429 430 /* memory organization block */ 431 __le32 byte_per_page; 432 __le16 spare_bytes_per_page; 433 u8 reserved2[6]; 434 __le32 pages_per_block; 435 __le32 blocks_per_lun; 436 u8 lun_count; 437 u8 addr_cycles; 438 u8 bits_per_cell; 439 u8 programs_per_page; 440 u8 multi_plane_addr; 441 u8 multi_plane_op_attr; 442 u8 reserved3[38]; 443 444 /* electrical parameter block */ 445 __le16 async_sdr_speed_grade; 446 __le16 toggle_ddr_speed_grade; 447 __le16 sync_ddr_speed_grade; 448 u8 async_sdr_features; 449 u8 toggle_ddr_features; 450 u8 sync_ddr_features; 451 __le16 t_prog; 452 __le16 t_bers; 453 __le16 t_r; 454 __le16 t_r_multi_plane; 455 __le16 t_ccs; 456 __le16 io_pin_capacitance_typ; 457 __le16 input_pin_capacitance_typ; 458 __le16 clk_pin_capacitance_typ; 459 u8 driver_strength_support; 460 __le16 t_adl; 461 u8 reserved4[36]; 462 463 /* ECC and endurance block */ 464 u8 guaranteed_good_blocks; 465 __le16 guaranteed_block_endurance; 466 struct jedec_ecc_info ecc_info[4]; 467 u8 reserved5[29]; 468 469 /* reserved */ 470 u8 reserved6[148]; 471 472 /* vendor */ 473 __le16 vendor_rev_num; 474 u8 reserved7[88]; 475 476 /* CRC for Parameter Page */ 477 __le16 crc; 478 } __packed; 479 480 /** 481 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 482 * @lock: protection lock 483 * @active: the mtd device which holds the controller currently 484 * @wq: wait queue to sleep on if a NAND operation is in 485 * progress used instead of the per chip wait queue 486 * when a hw controller is available. 487 */ 488 struct nand_hw_control { 489 spinlock_t lock; 490 struct nand_chip *active; 491 }; 492 493 /** 494 * struct nand_ecc_step_info - ECC step information of ECC engine 495 * @stepsize: data bytes per ECC step 496 * @strengths: array of supported strengths 497 * @nstrengths: number of supported strengths 498 */ 499 struct nand_ecc_step_info { 500 int stepsize; 501 const int *strengths; 502 int nstrengths; 503 }; 504 505 /** 506 * struct nand_ecc_caps - capability of ECC engine 507 * @stepinfos: array of ECC step information 508 * @nstepinfos: number of ECC step information 509 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 510 */ 511 struct nand_ecc_caps { 512 const struct nand_ecc_step_info *stepinfos; 513 int nstepinfos; 514 int (*calc_ecc_bytes)(int step_size, int strength); 515 }; 516 517 /** 518 * struct nand_ecc_ctrl - Control structure for ECC 519 * @mode: ECC mode 520 * @steps: number of ECC steps per page 521 * @size: data bytes per ECC step 522 * @bytes: ECC bytes per step 523 * @strength: max number of correctible bits per ECC step 524 * @total: total number of ECC bytes per page 525 * @prepad: padding information for syndrome based ECC generators 526 * @postpad: padding information for syndrome based ECC generators 527 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 528 * @layout: ECC layout control struct pointer 529 * @priv: pointer to private ECC control data 530 * @hwctl: function to control hardware ECC generator. Must only 531 * be provided if an hardware ECC is available 532 * @calculate: function for ECC calculation or readback from ECC hardware 533 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 534 * Should return a positive number representing the number of 535 * corrected bitflips, -EBADMSG if the number of bitflips exceed 536 * ECC strength, or any other error code if the error is not 537 * directly related to correction. 538 * If -EBADMSG is returned the input buffers should be left 539 * untouched. 540 * @read_page_raw: function to read a raw page without ECC. This function 541 * should hide the specific layout used by the ECC 542 * controller and always return contiguous in-band and 543 * out-of-band data even if they're not stored 544 * contiguously on the NAND chip (e.g. 545 * NAND_ECC_HW_SYNDROME interleaves in-band and 546 * out-of-band data). 547 * @write_page_raw: function to write a raw page without ECC. This function 548 * should hide the specific layout used by the ECC 549 * controller and consider the passed data as contiguous 550 * in-band and out-of-band data. ECC controller is 551 * responsible for doing the appropriate transformations 552 * to adapt to its specific layout (e.g. 553 * NAND_ECC_HW_SYNDROME interleaves in-band and 554 * out-of-band data). 555 * @read_page: function to read a page according to the ECC generator 556 * requirements; returns maximum number of bitflips corrected in 557 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 558 * @read_subpage: function to read parts of the page covered by ECC; 559 * returns same as read_page() 560 * @write_subpage: function to write parts of the page covered by ECC. 561 * @write_page: function to write a page according to the ECC generator 562 * requirements. 563 * @write_oob_raw: function to write chip OOB data without ECC 564 * @read_oob_raw: function to read chip OOB data without ECC 565 * @read_oob: function to read chip OOB data 566 * @write_oob: function to write chip OOB data 567 */ 568 struct nand_ecc_ctrl { 569 nand_ecc_modes_t mode; 570 int steps; 571 int size; 572 int bytes; 573 int total; 574 int strength; 575 int prepad; 576 int postpad; 577 unsigned int options; 578 struct nand_ecclayout *layout; 579 void *priv; 580 void (*hwctl)(struct mtd_info *mtd, int mode); 581 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 582 uint8_t *ecc_code); 583 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 584 uint8_t *calc_ecc); 585 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 586 uint8_t *buf, int oob_required, int page); 587 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 588 const uint8_t *buf, int oob_required, int page); 589 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 590 uint8_t *buf, int oob_required, int page); 591 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 592 uint32_t offs, uint32_t len, uint8_t *buf, int page); 593 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 594 uint32_t offset, uint32_t data_len, 595 const uint8_t *data_buf, int oob_required, int page); 596 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 597 const uint8_t *buf, int oob_required, int page); 598 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 599 int page); 600 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 601 int page); 602 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 603 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 604 int page); 605 }; 606 607 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) 608 { 609 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); 610 } 611 612 /** 613 * struct nand_buffers - buffer structure for read/write 614 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 615 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 616 * @databuf: buffer pointer for data, size is (page size + oobsize). 617 * 618 * Do not change the order of buffers. databuf and oobrbuf must be in 619 * consecutive order. 620 */ 621 struct nand_buffers { 622 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 623 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 624 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 625 ARCH_DMA_MINALIGN)]; 626 }; 627 628 /** 629 * struct nand_sdr_timings - SDR NAND chip timings 630 * 631 * This struct defines the timing requirements of a SDR NAND chip. 632 * These information can be found in every NAND datasheets and the timings 633 * meaning are described in the ONFI specifications: 634 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 635 * Parameters) 636 * 637 * All these timings are expressed in picoseconds. 638 * 639 * @tBERS_max: Block erase time 640 * @tCCS_min: Change column setup time 641 * @tPROG_max: Page program time 642 * @tR_max: Page read time 643 * @tALH_min: ALE hold time 644 * @tADL_min: ALE to data loading time 645 * @tALS_min: ALE setup time 646 * @tAR_min: ALE to RE# delay 647 * @tCEA_max: CE# access time 648 * @tCEH_min: CE# high hold time 649 * @tCH_min: CE# hold time 650 * @tCHZ_max: CE# high to output hi-Z 651 * @tCLH_min: CLE hold time 652 * @tCLR_min: CLE to RE# delay 653 * @tCLS_min: CLE setup time 654 * @tCOH_min: CE# high to output hold 655 * @tCS_min: CE# setup time 656 * @tDH_min: Data hold time 657 * @tDS_min: Data setup time 658 * @tFEAT_max: Busy time for Set Features and Get Features 659 * @tIR_min: Output hi-Z to RE# low 660 * @tITC_max: Interface and Timing Mode Change time 661 * @tRC_min: RE# cycle time 662 * @tREA_max: RE# access time 663 * @tREH_min: RE# high hold time 664 * @tRHOH_min: RE# high to output hold 665 * @tRHW_min: RE# high to WE# low 666 * @tRHZ_max: RE# high to output hi-Z 667 * @tRLOH_min: RE# low to output hold 668 * @tRP_min: RE# pulse width 669 * @tRR_min: Ready to RE# low (data only) 670 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 671 * rising edge of R/B#. 672 * @tWB_max: WE# high to SR[6] low 673 * @tWC_min: WE# cycle time 674 * @tWH_min: WE# high hold time 675 * @tWHR_min: WE# high to RE# low 676 * @tWP_min: WE# pulse width 677 * @tWW_min: WP# transition to WE# low 678 */ 679 struct nand_sdr_timings { 680 u64 tBERS_max; 681 u32 tCCS_min; 682 u64 tPROG_max; 683 u64 tR_max; 684 u32 tALH_min; 685 u32 tADL_min; 686 u32 tALS_min; 687 u32 tAR_min; 688 u32 tCEA_max; 689 u32 tCEH_min; 690 u32 tCH_min; 691 u32 tCHZ_max; 692 u32 tCLH_min; 693 u32 tCLR_min; 694 u32 tCLS_min; 695 u32 tCOH_min; 696 u32 tCS_min; 697 u32 tDH_min; 698 u32 tDS_min; 699 u32 tFEAT_max; 700 u32 tIR_min; 701 u32 tITC_max; 702 u32 tRC_min; 703 u32 tREA_max; 704 u32 tREH_min; 705 u32 tRHOH_min; 706 u32 tRHW_min; 707 u32 tRHZ_max; 708 u32 tRLOH_min; 709 u32 tRP_min; 710 u32 tRR_min; 711 u64 tRST_max; 712 u32 tWB_max; 713 u32 tWC_min; 714 u32 tWH_min; 715 u32 tWHR_min; 716 u32 tWP_min; 717 u32 tWW_min; 718 }; 719 720 /** 721 * enum nand_data_interface_type - NAND interface timing type 722 * @NAND_SDR_IFACE: Single Data Rate interface 723 */ 724 enum nand_data_interface_type { 725 NAND_SDR_IFACE, 726 }; 727 728 /** 729 * struct nand_data_interface - NAND interface timing 730 * @type: type of the timing 731 * @timings: The timing, type according to @type 732 */ 733 struct nand_data_interface { 734 enum nand_data_interface_type type; 735 union { 736 struct nand_sdr_timings sdr; 737 } timings; 738 }; 739 740 /** 741 * nand_get_sdr_timings - get SDR timing from data interface 742 * @conf: The data interface 743 */ 744 static inline const struct nand_sdr_timings * 745 nand_get_sdr_timings(const struct nand_data_interface *conf) 746 { 747 if (conf->type != NAND_SDR_IFACE) 748 return ERR_PTR(-EINVAL); 749 750 return &conf->timings.sdr; 751 } 752 753 /** 754 * struct nand_chip - NAND Private Flash Chip Data 755 * @mtd: MTD device registered to the MTD framework 756 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 757 * flash device 758 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 759 * flash device. 760 * @flash_node: [BOARDSPECIFIC] device node describing this instance 761 * @read_byte: [REPLACEABLE] read one byte from the chip 762 * @read_word: [REPLACEABLE] read one word from the chip 763 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 764 * low 8 I/O lines 765 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 766 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 767 * @select_chip: [REPLACEABLE] select chip nr 768 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 769 * @block_markbad: [REPLACEABLE] mark a block bad 770 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 771 * ALE/CLE/nCE. Also used to write command and address 772 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 773 * device ready/busy line. If set to NULL no access to 774 * ready/busy is available and the ready/busy information 775 * is read from the chip status register. 776 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 777 * commands to the chip. 778 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 779 * ready. 780 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 781 * setting the read-retry mode. Mostly needed for MLC NAND. 782 * @ecc: [BOARDSPECIFIC] ECC control structure 783 * @buffers: buffer structure for read/write 784 * @buf_align: minimum buffer alignment required by a platform 785 * @hwcontrol: platform-specific hardware control structure 786 * @erase: [REPLACEABLE] erase function 787 * @scan_bbt: [REPLACEABLE] function to scan bad block table 788 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 789 * data from array to read regs (tR). 790 * @state: [INTERN] the current state of the NAND device 791 * @oob_poi: "poison value buffer," used for laying out OOB data 792 * before writing 793 * @page_shift: [INTERN] number of address bits in a page (column 794 * address bits). 795 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 796 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 797 * @chip_shift: [INTERN] number of address bits in one chip 798 * @options: [BOARDSPECIFIC] various chip options. They can partly 799 * be set to inform nand_scan about special functionality. 800 * See the defines for further explanation. 801 * @bbt_options: [INTERN] bad block specific options. All options used 802 * here must come from bbm.h. By default, these options 803 * will be copied to the appropriate nand_bbt_descr's. 804 * @badblockpos: [INTERN] position of the bad block marker in the oob 805 * area. 806 * @badblockbits: [INTERN] minimum number of set bits in a good block's 807 * bad block marker position; i.e., BBM == 11110111b is 808 * not bad when badblockbits == 7 809 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 810 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 811 * Minimum amount of bit errors per @ecc_step_ds guaranteed 812 * to be correctable. If unknown, set to zero. 813 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 814 * also from the datasheet. It is the recommended ECC step 815 * size, if known; if unknown, set to zero. 816 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 817 * set to the actually used ONFI mode if the chip is 818 * ONFI compliant or deduced from the datasheet if 819 * the NAND chip is not ONFI compliant. 820 * @numchips: [INTERN] number of physical chips 821 * @chipsize: [INTERN] the size of one chip for multichip arrays 822 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 823 * @pagebuf: [INTERN] holds the pagenumber which is currently in 824 * data_buf. 825 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 826 * currently in data_buf. 827 * @subpagesize: [INTERN] holds the subpagesize 828 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 829 * non 0 if ONFI supported. 830 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 831 * non 0 if JEDEC supported. 832 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 833 * supported, 0 otherwise. 834 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 835 * supported, 0 otherwise. 836 * @read_retries: [INTERN] the number of read retry modes supported 837 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 838 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 839 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 840 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 841 * means the configuration should not be applied but 842 * only checked. 843 * @bbt: [INTERN] bad block table pointer 844 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 845 * lookup. 846 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 847 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 848 * bad block scan. 849 * @controller: [REPLACEABLE] a pointer to a hardware controller 850 * structure which is shared among multiple independent 851 * devices. 852 * @priv: [OPTIONAL] pointer to private chip data 853 * @write_page: [REPLACEABLE] High-level page write function 854 */ 855 856 struct nand_chip { 857 struct mtd_info mtd; 858 void __iomem *IO_ADDR_R; 859 void __iomem *IO_ADDR_W; 860 861 int flash_node; 862 863 uint8_t (*read_byte)(struct mtd_info *mtd); 864 u16 (*read_word)(struct mtd_info *mtd); 865 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 866 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 867 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 868 void (*select_chip)(struct mtd_info *mtd, int chip); 869 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 870 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 871 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 872 int (*dev_ready)(struct mtd_info *mtd); 873 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 874 int page_addr); 875 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 876 int (*erase)(struct mtd_info *mtd, int page); 877 int (*scan_bbt)(struct mtd_info *mtd); 878 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 879 uint32_t offset, int data_len, const uint8_t *buf, 880 int oob_required, int page, int raw); 881 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 882 int feature_addr, uint8_t *subfeature_para); 883 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 884 int feature_addr, uint8_t *subfeature_para); 885 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 886 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 887 const struct nand_data_interface *conf); 888 889 890 int chip_delay; 891 unsigned int options; 892 unsigned int bbt_options; 893 894 int page_shift; 895 int phys_erase_shift; 896 int bbt_erase_shift; 897 int chip_shift; 898 int numchips; 899 uint64_t chipsize; 900 int pagemask; 901 int pagebuf; 902 unsigned int pagebuf_bitflips; 903 int subpagesize; 904 uint8_t bits_per_cell; 905 uint16_t ecc_strength_ds; 906 uint16_t ecc_step_ds; 907 int onfi_timing_mode_default; 908 int badblockpos; 909 int badblockbits; 910 911 int onfi_version; 912 int jedec_version; 913 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 914 struct nand_onfi_params onfi_params; 915 #endif 916 struct nand_jedec_params jedec_params; 917 918 struct nand_data_interface *data_interface; 919 920 int read_retries; 921 922 flstate_t state; 923 924 uint8_t *oob_poi; 925 struct nand_hw_control *controller; 926 struct nand_ecclayout *ecclayout; 927 928 struct nand_ecc_ctrl ecc; 929 struct nand_buffers *buffers; 930 unsigned long buf_align; 931 struct nand_hw_control hwcontrol; 932 933 uint8_t *bbt; 934 struct nand_bbt_descr *bbt_td; 935 struct nand_bbt_descr *bbt_md; 936 937 struct nand_bbt_descr *badblock_pattern; 938 939 void *priv; 940 }; 941 942 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 943 { 944 return container_of(mtd, struct nand_chip, mtd); 945 } 946 947 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 948 { 949 return &chip->mtd; 950 } 951 952 static inline void *nand_get_controller_data(struct nand_chip *chip) 953 { 954 return chip->priv; 955 } 956 957 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 958 { 959 chip->priv = priv; 960 } 961 962 /* 963 * NAND Flash Manufacturer ID Codes 964 */ 965 #define NAND_MFR_TOSHIBA 0x98 966 #define NAND_MFR_SAMSUNG 0xec 967 #define NAND_MFR_FUJITSU 0x04 968 #define NAND_MFR_NATIONAL 0x8f 969 #define NAND_MFR_RENESAS 0x07 970 #define NAND_MFR_STMICRO 0x20 971 #define NAND_MFR_HYNIX 0xad 972 #define NAND_MFR_MICRON 0x2c 973 #define NAND_MFR_AMD 0x01 974 #define NAND_MFR_MACRONIX 0xc2 975 #define NAND_MFR_EON 0x92 976 #define NAND_MFR_SANDISK 0x45 977 #define NAND_MFR_INTEL 0x89 978 #define NAND_MFR_ATO 0x9b 979 980 /* The maximum expected count of bytes in the NAND ID sequence */ 981 #define NAND_MAX_ID_LEN 8 982 983 /* 984 * A helper for defining older NAND chips where the second ID byte fully 985 * defined the chip, including the geometry (chip size, eraseblock size, page 986 * size). All these chips have 512 bytes NAND page size. 987 */ 988 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 989 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 990 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 991 992 /* 993 * A helper for defining newer chips which report their page size and 994 * eraseblock size via the extended ID bytes. 995 * 996 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 997 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 998 * device ID now only represented a particular total chip size (and voltage, 999 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1000 * using the same device ID. 1001 */ 1002 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1003 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1004 .options = (opts) } 1005 1006 #define NAND_ECC_INFO(_strength, _step) \ 1007 { .strength_ds = (_strength), .step_ds = (_step) } 1008 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1009 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1010 1011 /** 1012 * struct nand_flash_dev - NAND Flash Device ID Structure 1013 * @name: a human-readable name of the NAND chip 1014 * @dev_id: the device ID (the second byte of the full chip ID array) 1015 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1016 * memory address as @id[0]) 1017 * @dev_id: device ID part of the full chip ID array (refers the same memory 1018 * address as @id[1]) 1019 * @id: full device ID array 1020 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1021 * well as the eraseblock size) is determined from the extended NAND 1022 * chip ID array) 1023 * @chipsize: total chip size in MiB 1024 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1025 * @options: stores various chip bit options 1026 * @id_len: The valid length of the @id. 1027 * @oobsize: OOB size 1028 * @ecc: ECC correctability and step information from the datasheet. 1029 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1030 * @ecc_strength_ds in nand_chip{}. 1031 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1032 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1033 * For example, the "4bit ECC for each 512Byte" can be set with 1034 * NAND_ECC_INFO(4, 512). 1035 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1036 * reset. Should be deduced from timings described 1037 * in the datasheet. 1038 * 1039 */ 1040 struct nand_flash_dev { 1041 char *name; 1042 union { 1043 struct { 1044 uint8_t mfr_id; 1045 uint8_t dev_id; 1046 }; 1047 uint8_t id[NAND_MAX_ID_LEN]; 1048 }; 1049 unsigned int pagesize; 1050 unsigned int chipsize; 1051 unsigned int erasesize; 1052 unsigned int options; 1053 uint16_t id_len; 1054 uint16_t oobsize; 1055 struct { 1056 uint16_t strength_ds; 1057 uint16_t step_ds; 1058 } ecc; 1059 int onfi_timing_mode_default; 1060 }; 1061 1062 /** 1063 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 1064 * @name: Manufacturer name 1065 * @id: manufacturer ID code of device. 1066 */ 1067 struct nand_manufacturers { 1068 int id; 1069 char *name; 1070 }; 1071 1072 extern struct nand_flash_dev nand_flash_ids[]; 1073 extern struct nand_manufacturers nand_manuf_ids[]; 1074 1075 extern int nand_default_bbt(struct mtd_info *mtd); 1076 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1077 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1078 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1079 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1080 int allowbbt); 1081 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1082 size_t *retlen, uint8_t *buf); 1083 1084 /* 1085 * Constants for oob configuration 1086 */ 1087 #define NAND_SMALL_BADBLOCK_POS 5 1088 #define NAND_LARGE_BADBLOCK_POS 0 1089 1090 /** 1091 * struct platform_nand_chip - chip level device structure 1092 * @nr_chips: max. number of chips to scan for 1093 * @chip_offset: chip number offset 1094 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1095 * @partitions: mtd partition list 1096 * @chip_delay: R/B delay value in us 1097 * @options: Option flags, e.g. 16bit buswidth 1098 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1099 * @part_probe_types: NULL-terminated array of probe types 1100 */ 1101 struct platform_nand_chip { 1102 int nr_chips; 1103 int chip_offset; 1104 int nr_partitions; 1105 struct mtd_partition *partitions; 1106 int chip_delay; 1107 unsigned int options; 1108 unsigned int bbt_options; 1109 const char **part_probe_types; 1110 }; 1111 1112 /* Keep gcc happy */ 1113 struct platform_device; 1114 1115 /** 1116 * struct platform_nand_ctrl - controller level device structure 1117 * @probe: platform specific function to probe/setup hardware 1118 * @remove: platform specific function to remove/teardown hardware 1119 * @hwcontrol: platform specific hardware control structure 1120 * @dev_ready: platform specific function to read ready/busy pin 1121 * @select_chip: platform specific chip select function 1122 * @cmd_ctrl: platform specific function for controlling 1123 * ALE/CLE/nCE. Also used to write command and address 1124 * @write_buf: platform specific function for write buffer 1125 * @read_buf: platform specific function for read buffer 1126 * @read_byte: platform specific function to read one byte from chip 1127 * @priv: private data to transport driver specific settings 1128 * 1129 * All fields are optional and depend on the hardware driver requirements 1130 */ 1131 struct platform_nand_ctrl { 1132 int (*probe)(struct platform_device *pdev); 1133 void (*remove)(struct platform_device *pdev); 1134 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1135 int (*dev_ready)(struct mtd_info *mtd); 1136 void (*select_chip)(struct mtd_info *mtd, int chip); 1137 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1138 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1139 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1140 unsigned char (*read_byte)(struct mtd_info *mtd); 1141 void *priv; 1142 }; 1143 1144 /** 1145 * struct platform_nand_data - container structure for platform-specific data 1146 * @chip: chip level chip structure 1147 * @ctrl: controller level device structure 1148 */ 1149 struct platform_nand_data { 1150 struct platform_nand_chip chip; 1151 struct platform_nand_ctrl ctrl; 1152 }; 1153 1154 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 1155 /* return the supported features. */ 1156 static inline int onfi_feature(struct nand_chip *chip) 1157 { 1158 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1159 } 1160 1161 /* return the supported asynchronous timing mode. */ 1162 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1163 { 1164 if (!chip->onfi_version) 1165 return ONFI_TIMING_MODE_UNKNOWN; 1166 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1167 } 1168 1169 /* return the supported synchronous timing mode. */ 1170 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1171 { 1172 if (!chip->onfi_version) 1173 return ONFI_TIMING_MODE_UNKNOWN; 1174 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1175 } 1176 #endif 1177 1178 int onfi_init_data_interface(struct nand_chip *chip, 1179 struct nand_data_interface *iface, 1180 enum nand_data_interface_type type, 1181 int timing_mode); 1182 1183 /* 1184 * Check if it is a SLC nand. 1185 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1186 * We do not distinguish the MLC and TLC now. 1187 */ 1188 static inline bool nand_is_slc(struct nand_chip *chip) 1189 { 1190 return chip->bits_per_cell == 1; 1191 } 1192 1193 /** 1194 * Check if the opcode's address should be sent only on the lower 8 bits 1195 * @command: opcode to check 1196 */ 1197 static inline int nand_opcode_8bits(unsigned int command) 1198 { 1199 switch (command) { 1200 case NAND_CMD_READID: 1201 case NAND_CMD_PARAM: 1202 case NAND_CMD_GET_FEATURES: 1203 case NAND_CMD_SET_FEATURES: 1204 return 1; 1205 default: 1206 break; 1207 } 1208 return 0; 1209 } 1210 1211 /* return the supported JEDEC features. */ 1212 static inline int jedec_feature(struct nand_chip *chip) 1213 { 1214 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1215 : 0; 1216 } 1217 1218 /* Standard NAND functions from nand_base.c */ 1219 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1220 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1221 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1222 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1223 uint8_t nand_read_byte(struct mtd_info *mtd); 1224 1225 /* get timing characteristics from ONFI timing mode. */ 1226 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1227 /* get data interface from ONFI timing mode 0, used after reset. */ 1228 const struct nand_data_interface *nand_get_default_data_interface(void); 1229 1230 int nand_check_erased_ecc_chunk(void *data, int datalen, 1231 void *ecc, int ecclen, 1232 void *extraoob, int extraooblen, 1233 int threshold); 1234 1235 int nand_check_ecc_caps(struct nand_chip *chip, 1236 const struct nand_ecc_caps *caps, int oobavail); 1237 1238 int nand_match_ecc_req(struct nand_chip *chip, 1239 const struct nand_ecc_caps *caps, int oobavail); 1240 1241 int nand_maximize_ecc(struct nand_chip *chip, 1242 const struct nand_ecc_caps *caps, int oobavail); 1243 1244 /* Reset and initialize a NAND device */ 1245 int nand_reset(struct nand_chip *chip, int chipnr); 1246 1247 #endif /* __LINUX_MTD_NAND_H */ 1248