1 /* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 * 10 * Info: 11 * Contains standard defines and IDs for NAND flash devices 12 * 13 * Changelog: 14 * See git changelog. 15 */ 16 #ifndef __LINUX_MTD_NAND_H 17 #define __LINUX_MTD_NAND_H 18 19 #include <config.h> 20 21 #include <linux/compat.h> 22 #include <linux/mtd/mtd.h> 23 #include <linux/mtd/flashchip.h> 24 #include <linux/mtd/bbm.h> 25 26 struct mtd_info; 27 struct nand_flash_dev; 28 struct device_node; 29 30 /* Scan and identify a NAND device */ 31 extern int nand_scan(struct mtd_info *mtd, int max_chips); 32 /* 33 * Separate phases of nand_scan(), allowing board driver to intervene 34 * and override command or ECC setup according to flash type. 35 */ 36 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 37 struct nand_flash_dev *table); 38 extern int nand_scan_tail(struct mtd_info *mtd); 39 40 /* Free resources held by the NAND device */ 41 extern void nand_release(struct mtd_info *mtd); 42 43 /* Internal helper for board drivers which need to override command function */ 44 extern void nand_wait_ready(struct mtd_info *mtd); 45 46 /* 47 * This constant declares the max. oobsize / page, which 48 * is supported now. If you add a chip with bigger oobsize/page 49 * adjust this accordingly. 50 */ 51 #define NAND_MAX_OOBSIZE 1664 52 #define NAND_MAX_PAGESIZE 16384 53 54 /* 55 * Constants for hardware specific CLE/ALE/NCE function 56 * 57 * These are bits which can be or'ed to set/clear multiple 58 * bits in one go. 59 */ 60 /* Select the chip by setting nCE to low */ 61 #define NAND_NCE 0x01 62 /* Select the command latch by setting CLE to high */ 63 #define NAND_CLE 0x02 64 /* Select the address latch by setting ALE to high */ 65 #define NAND_ALE 0x04 66 67 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 68 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 69 #define NAND_CTRL_CHANGE 0x80 70 71 /* 72 * Standard NAND flash commands 73 */ 74 #define NAND_CMD_READ0 0 75 #define NAND_CMD_READ1 1 76 #define NAND_CMD_RNDOUT 5 77 #define NAND_CMD_PAGEPROG 0x10 78 #define NAND_CMD_READOOB 0x50 79 #define NAND_CMD_ERASE1 0x60 80 #define NAND_CMD_STATUS 0x70 81 #define NAND_CMD_SEQIN 0x80 82 #define NAND_CMD_RNDIN 0x85 83 #define NAND_CMD_READID 0x90 84 #define NAND_CMD_ERASE2 0xd0 85 #define NAND_CMD_PARAM 0xec 86 #define NAND_CMD_GET_FEATURES 0xee 87 #define NAND_CMD_SET_FEATURES 0xef 88 #define NAND_CMD_RESET 0xff 89 90 #define NAND_CMD_LOCK 0x2a 91 #define NAND_CMD_UNLOCK1 0x23 92 #define NAND_CMD_UNLOCK2 0x24 93 94 /* Extended commands for large page devices */ 95 #define NAND_CMD_READSTART 0x30 96 #define NAND_CMD_RNDOUTSTART 0xE0 97 #define NAND_CMD_CACHEDPROG 0x15 98 99 /* Extended commands for AG-AND device */ 100 /* 101 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 102 * there is no way to distinguish that from NAND_CMD_READ0 103 * until the remaining sequence of commands has been completed 104 * so add a high order bit and mask it off in the command. 105 */ 106 #define NAND_CMD_DEPLETE1 0x100 107 #define NAND_CMD_DEPLETE2 0x38 108 #define NAND_CMD_STATUS_MULTI 0x71 109 #define NAND_CMD_STATUS_ERROR 0x72 110 /* multi-bank error status (banks 0-3) */ 111 #define NAND_CMD_STATUS_ERROR0 0x73 112 #define NAND_CMD_STATUS_ERROR1 0x74 113 #define NAND_CMD_STATUS_ERROR2 0x75 114 #define NAND_CMD_STATUS_ERROR3 0x76 115 #define NAND_CMD_STATUS_RESET 0x7f 116 #define NAND_CMD_STATUS_CLEAR 0xff 117 118 #define NAND_CMD_NONE -1 119 120 /* Status bits */ 121 #define NAND_STATUS_FAIL 0x01 122 #define NAND_STATUS_FAIL_N1 0x02 123 #define NAND_STATUS_TRUE_READY 0x20 124 #define NAND_STATUS_READY 0x40 125 #define NAND_STATUS_WP 0x80 126 127 #define NAND_DATA_IFACE_CHECK_ONLY -1 128 129 /* 130 * Constants for ECC_MODES 131 */ 132 typedef enum { 133 NAND_ECC_NONE, 134 NAND_ECC_SOFT, 135 NAND_ECC_HW, 136 NAND_ECC_HW_SYNDROME, 137 NAND_ECC_HW_OOB_FIRST, 138 NAND_ECC_SOFT_BCH, 139 } nand_ecc_modes_t; 140 141 /* 142 * Constants for Hardware ECC 143 */ 144 /* Reset Hardware ECC for read */ 145 #define NAND_ECC_READ 0 146 /* Reset Hardware ECC for write */ 147 #define NAND_ECC_WRITE 1 148 /* Enable Hardware ECC before syndrome is read back from flash */ 149 #define NAND_ECC_READSYN 2 150 151 /* 152 * Enable generic NAND 'page erased' check. This check is only done when 153 * ecc.correct() returns -EBADMSG. 154 * Set this flag if your implementation does not fix bitflips in erased 155 * pages and you want to rely on the default implementation. 156 */ 157 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 158 #define NAND_ECC_MAXIMIZE BIT(1) 159 /* 160 * If your controller already sends the required NAND commands when 161 * reading or writing a page, then the framework is not supposed to 162 * send READ0 and SEQIN/PAGEPROG respectively. 163 */ 164 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) 165 166 /* Bit mask for flags passed to do_nand_read_ecc */ 167 #define NAND_GET_DEVICE 0x80 168 169 170 /* 171 * Option constants for bizarre disfunctionality and real 172 * features. 173 */ 174 /* Buswidth is 16 bit */ 175 #define NAND_BUSWIDTH_16 0x00000002 176 /* Device supports partial programming without padding */ 177 #define NAND_NO_PADDING 0x00000004 178 /* Chip has cache program function */ 179 #define NAND_CACHEPRG 0x00000008 180 /* Chip has copy back function */ 181 #define NAND_COPYBACK 0x00000010 182 /* 183 * Chip requires ready check on read (for auto-incremented sequential read). 184 * True only for small page devices; large page devices do not support 185 * autoincrement. 186 */ 187 #define NAND_NEED_READRDY 0x00000100 188 189 /* Chip does not allow subpage writes */ 190 #define NAND_NO_SUBPAGE_WRITE 0x00000200 191 192 /* Device is one of 'new' xD cards that expose fake nand command set */ 193 #define NAND_BROKEN_XD 0x00000400 194 195 /* Device behaves just like nand, but is readonly */ 196 #define NAND_ROM 0x00000800 197 198 /* Device supports subpage reads */ 199 #define NAND_SUBPAGE_READ 0x00001000 200 201 /* 202 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 203 * patterns. 204 */ 205 #define NAND_NEED_SCRAMBLING 0x00002000 206 207 /* Options valid for Samsung large page devices */ 208 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 209 210 /* Macros to identify the above */ 211 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 212 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 213 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) 214 215 /* Non chip related options */ 216 /* This option skips the bbt scan during initialization. */ 217 #define NAND_SKIP_BBTSCAN 0x00010000 218 /* 219 * This option is defined if the board driver allocates its own buffers 220 * (e.g. because it needs them DMA-coherent). 221 */ 222 #define NAND_OWN_BUFFERS 0x00020000 223 /* Chip may not exist, so silence any errors in scan */ 224 #define NAND_SCAN_SILENT_NODEV 0x00040000 225 /* 226 * Autodetect nand buswidth with readid/onfi. 227 * This suppose the driver will configure the hardware in 8 bits mode 228 * when calling nand_scan_ident, and update its configuration 229 * before calling nand_scan_tail. 230 */ 231 #define NAND_BUSWIDTH_AUTO 0x00080000 232 /* 233 * This option could be defined by controller drivers to protect against 234 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 235 */ 236 #define NAND_USE_BOUNCE_BUFFER 0x00100000 237 238 /* Options set by nand scan */ 239 /* bbt has already been read */ 240 #define NAND_BBT_SCANNED 0x40000000 241 /* Nand scan has allocated controller struct */ 242 #define NAND_CONTROLLER_ALLOC 0x80000000 243 244 /* Cell info constants */ 245 #define NAND_CI_CHIPNR_MSK 0x03 246 #define NAND_CI_CELLTYPE_MSK 0x0C 247 #define NAND_CI_CELLTYPE_SHIFT 2 248 249 /* Keep gcc happy */ 250 struct nand_chip; 251 252 /* ONFI features */ 253 #define ONFI_FEATURE_16_BIT_BUS (1 << 0) 254 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) 255 256 /* ONFI timing mode, used in both asynchronous and synchronous mode */ 257 #define ONFI_TIMING_MODE_0 (1 << 0) 258 #define ONFI_TIMING_MODE_1 (1 << 1) 259 #define ONFI_TIMING_MODE_2 (1 << 2) 260 #define ONFI_TIMING_MODE_3 (1 << 3) 261 #define ONFI_TIMING_MODE_4 (1 << 4) 262 #define ONFI_TIMING_MODE_5 (1 << 5) 263 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) 264 265 /* ONFI feature address */ 266 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 267 268 /* Vendor-specific feature address (Micron) */ 269 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 270 271 /* ONFI subfeature parameters length */ 272 #define ONFI_SUBFEATURE_PARAM_LEN 4 273 274 /* ONFI optional commands SET/GET FEATURES supported? */ 275 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) 276 277 struct nand_onfi_params { 278 /* rev info and features block */ 279 /* 'O' 'N' 'F' 'I' */ 280 u8 sig[4]; 281 __le16 revision; 282 __le16 features; 283 __le16 opt_cmd; 284 u8 reserved0[2]; 285 __le16 ext_param_page_length; /* since ONFI 2.1 */ 286 u8 num_of_param_pages; /* since ONFI 2.1 */ 287 u8 reserved1[17]; 288 289 /* manufacturer information block */ 290 char manufacturer[12]; 291 char model[20]; 292 u8 jedec_id; 293 __le16 date_code; 294 u8 reserved2[13]; 295 296 /* memory organization block */ 297 __le32 byte_per_page; 298 __le16 spare_bytes_per_page; 299 __le32 data_bytes_per_ppage; 300 __le16 spare_bytes_per_ppage; 301 __le32 pages_per_block; 302 __le32 blocks_per_lun; 303 u8 lun_count; 304 u8 addr_cycles; 305 u8 bits_per_cell; 306 __le16 bb_per_lun; 307 __le16 block_endurance; 308 u8 guaranteed_good_blocks; 309 __le16 guaranteed_block_endurance; 310 u8 programs_per_page; 311 u8 ppage_attr; 312 u8 ecc_bits; 313 u8 interleaved_bits; 314 u8 interleaved_ops; 315 u8 reserved3[13]; 316 317 /* electrical parameter block */ 318 u8 io_pin_capacitance_max; 319 __le16 async_timing_mode; 320 __le16 program_cache_timing_mode; 321 __le16 t_prog; 322 __le16 t_bers; 323 __le16 t_r; 324 __le16 t_ccs; 325 __le16 src_sync_timing_mode; 326 u8 src_ssync_features; 327 __le16 clk_pin_capacitance_typ; 328 __le16 io_pin_capacitance_typ; 329 __le16 input_pin_capacitance_typ; 330 u8 input_pin_capacitance_max; 331 u8 driver_strength_support; 332 __le16 t_int_r; 333 __le16 t_adl; 334 u8 reserved4[8]; 335 336 /* vendor */ 337 __le16 vendor_revision; 338 u8 vendor[88]; 339 340 __le16 crc; 341 } __packed; 342 343 #define ONFI_CRC_BASE 0x4F4E 344 345 /* Extended ECC information Block Definition (since ONFI 2.1) */ 346 struct onfi_ext_ecc_info { 347 u8 ecc_bits; 348 u8 codeword_size; 349 __le16 bb_per_lun; 350 __le16 block_endurance; 351 u8 reserved[2]; 352 } __packed; 353 354 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ 355 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ 356 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ 357 struct onfi_ext_section { 358 u8 type; 359 u8 length; 360 } __packed; 361 362 #define ONFI_EXT_SECTION_MAX 8 363 364 /* Extended Parameter Page Definition (since ONFI 2.1) */ 365 struct onfi_ext_param_page { 366 __le16 crc; 367 u8 sig[4]; /* 'E' 'P' 'P' 'S' */ 368 u8 reserved0[10]; 369 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; 370 371 /* 372 * The actual size of the Extended Parameter Page is in 373 * @ext_param_page_length of nand_onfi_params{}. 374 * The following are the variable length sections. 375 * So we do not add any fields below. Please see the ONFI spec. 376 */ 377 } __packed; 378 379 struct nand_onfi_vendor_micron { 380 u8 two_plane_read; 381 u8 read_cache; 382 u8 read_unique_id; 383 u8 dq_imped; 384 u8 dq_imped_num_settings; 385 u8 dq_imped_feat_addr; 386 u8 rb_pulldown_strength; 387 u8 rb_pulldown_strength_feat_addr; 388 u8 rb_pulldown_strength_num_settings; 389 u8 otp_mode; 390 u8 otp_page_start; 391 u8 otp_data_prot_addr; 392 u8 otp_num_pages; 393 u8 otp_feat_addr; 394 u8 read_retry_options; 395 u8 reserved[72]; 396 u8 param_revision; 397 } __packed; 398 399 struct jedec_ecc_info { 400 u8 ecc_bits; 401 u8 codeword_size; 402 __le16 bb_per_lun; 403 __le16 block_endurance; 404 u8 reserved[2]; 405 } __packed; 406 407 /* JEDEC features */ 408 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) 409 410 struct nand_jedec_params { 411 /* rev info and features block */ 412 /* 'J' 'E' 'S' 'D' */ 413 u8 sig[4]; 414 __le16 revision; 415 __le16 features; 416 u8 opt_cmd[3]; 417 __le16 sec_cmd; 418 u8 num_of_param_pages; 419 u8 reserved0[18]; 420 421 /* manufacturer information block */ 422 char manufacturer[12]; 423 char model[20]; 424 u8 jedec_id[6]; 425 u8 reserved1[10]; 426 427 /* memory organization block */ 428 __le32 byte_per_page; 429 __le16 spare_bytes_per_page; 430 u8 reserved2[6]; 431 __le32 pages_per_block; 432 __le32 blocks_per_lun; 433 u8 lun_count; 434 u8 addr_cycles; 435 u8 bits_per_cell; 436 u8 programs_per_page; 437 u8 multi_plane_addr; 438 u8 multi_plane_op_attr; 439 u8 reserved3[38]; 440 441 /* electrical parameter block */ 442 __le16 async_sdr_speed_grade; 443 __le16 toggle_ddr_speed_grade; 444 __le16 sync_ddr_speed_grade; 445 u8 async_sdr_features; 446 u8 toggle_ddr_features; 447 u8 sync_ddr_features; 448 __le16 t_prog; 449 __le16 t_bers; 450 __le16 t_r; 451 __le16 t_r_multi_plane; 452 __le16 t_ccs; 453 __le16 io_pin_capacitance_typ; 454 __le16 input_pin_capacitance_typ; 455 __le16 clk_pin_capacitance_typ; 456 u8 driver_strength_support; 457 __le16 t_adl; 458 u8 reserved4[36]; 459 460 /* ECC and endurance block */ 461 u8 guaranteed_good_blocks; 462 __le16 guaranteed_block_endurance; 463 struct jedec_ecc_info ecc_info[4]; 464 u8 reserved5[29]; 465 466 /* reserved */ 467 u8 reserved6[148]; 468 469 /* vendor */ 470 __le16 vendor_rev_num; 471 u8 reserved7[88]; 472 473 /* CRC for Parameter Page */ 474 __le16 crc; 475 } __packed; 476 477 /** 478 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 479 * @lock: protection lock 480 * @active: the mtd device which holds the controller currently 481 * @wq: wait queue to sleep on if a NAND operation is in 482 * progress used instead of the per chip wait queue 483 * when a hw controller is available. 484 */ 485 struct nand_hw_control { 486 spinlock_t lock; 487 struct nand_chip *active; 488 }; 489 490 /** 491 * struct nand_ecc_step_info - ECC step information of ECC engine 492 * @stepsize: data bytes per ECC step 493 * @strengths: array of supported strengths 494 * @nstrengths: number of supported strengths 495 */ 496 struct nand_ecc_step_info { 497 int stepsize; 498 const int *strengths; 499 int nstrengths; 500 }; 501 502 /** 503 * struct nand_ecc_caps - capability of ECC engine 504 * @stepinfos: array of ECC step information 505 * @nstepinfos: number of ECC step information 506 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 507 */ 508 struct nand_ecc_caps { 509 const struct nand_ecc_step_info *stepinfos; 510 int nstepinfos; 511 int (*calc_ecc_bytes)(int step_size, int strength); 512 }; 513 514 /** 515 * struct nand_ecc_ctrl - Control structure for ECC 516 * @mode: ECC mode 517 * @steps: number of ECC steps per page 518 * @size: data bytes per ECC step 519 * @bytes: ECC bytes per step 520 * @strength: max number of correctible bits per ECC step 521 * @total: total number of ECC bytes per page 522 * @prepad: padding information for syndrome based ECC generators 523 * @postpad: padding information for syndrome based ECC generators 524 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 525 * @layout: ECC layout control struct pointer 526 * @priv: pointer to private ECC control data 527 * @hwctl: function to control hardware ECC generator. Must only 528 * be provided if an hardware ECC is available 529 * @calculate: function for ECC calculation or readback from ECC hardware 530 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 531 * Should return a positive number representing the number of 532 * corrected bitflips, -EBADMSG if the number of bitflips exceed 533 * ECC strength, or any other error code if the error is not 534 * directly related to correction. 535 * If -EBADMSG is returned the input buffers should be left 536 * untouched. 537 * @read_page_raw: function to read a raw page without ECC. This function 538 * should hide the specific layout used by the ECC 539 * controller and always return contiguous in-band and 540 * out-of-band data even if they're not stored 541 * contiguously on the NAND chip (e.g. 542 * NAND_ECC_HW_SYNDROME interleaves in-band and 543 * out-of-band data). 544 * @write_page_raw: function to write a raw page without ECC. This function 545 * should hide the specific layout used by the ECC 546 * controller and consider the passed data as contiguous 547 * in-band and out-of-band data. ECC controller is 548 * responsible for doing the appropriate transformations 549 * to adapt to its specific layout (e.g. 550 * NAND_ECC_HW_SYNDROME interleaves in-band and 551 * out-of-band data). 552 * @read_page: function to read a page according to the ECC generator 553 * requirements; returns maximum number of bitflips corrected in 554 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error 555 * @read_subpage: function to read parts of the page covered by ECC; 556 * returns same as read_page() 557 * @write_subpage: function to write parts of the page covered by ECC. 558 * @write_page: function to write a page according to the ECC generator 559 * requirements. 560 * @write_oob_raw: function to write chip OOB data without ECC 561 * @read_oob_raw: function to read chip OOB data without ECC 562 * @read_oob: function to read chip OOB data 563 * @write_oob: function to write chip OOB data 564 */ 565 struct nand_ecc_ctrl { 566 nand_ecc_modes_t mode; 567 int steps; 568 int size; 569 int bytes; 570 int total; 571 int strength; 572 int prepad; 573 int postpad; 574 unsigned int options; 575 struct nand_ecclayout *layout; 576 void *priv; 577 void (*hwctl)(struct mtd_info *mtd, int mode); 578 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, 579 uint8_t *ecc_code); 580 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, 581 uint8_t *calc_ecc); 582 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 583 uint8_t *buf, int oob_required, int page); 584 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, 585 const uint8_t *buf, int oob_required, int page); 586 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, 587 uint8_t *buf, int oob_required, int page); 588 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 589 uint32_t offs, uint32_t len, uint8_t *buf, int page); 590 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, 591 uint32_t offset, uint32_t data_len, 592 const uint8_t *data_buf, int oob_required, int page); 593 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 594 const uint8_t *buf, int oob_required, int page); 595 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 596 int page); 597 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, 598 int page); 599 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); 600 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, 601 int page); 602 }; 603 604 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) 605 { 606 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); 607 } 608 609 /** 610 * struct nand_buffers - buffer structure for read/write 611 * @ecccalc: buffer pointer for calculated ECC, size is oobsize. 612 * @ecccode: buffer pointer for ECC read from flash, size is oobsize. 613 * @databuf: buffer pointer for data, size is (page size + oobsize). 614 * 615 * Do not change the order of buffers. databuf and oobrbuf must be in 616 * consecutive order. 617 */ 618 struct nand_buffers { 619 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 620 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; 621 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, 622 ARCH_DMA_MINALIGN)]; 623 }; 624 625 /** 626 * struct nand_sdr_timings - SDR NAND chip timings 627 * 628 * This struct defines the timing requirements of a SDR NAND chip. 629 * These information can be found in every NAND datasheets and the timings 630 * meaning are described in the ONFI specifications: 631 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 632 * Parameters) 633 * 634 * All these timings are expressed in picoseconds. 635 * 636 * @tBERS_max: Block erase time 637 * @tCCS_min: Change column setup time 638 * @tPROG_max: Page program time 639 * @tR_max: Page read time 640 * @tALH_min: ALE hold time 641 * @tADL_min: ALE to data loading time 642 * @tALS_min: ALE setup time 643 * @tAR_min: ALE to RE# delay 644 * @tCEA_max: CE# access time 645 * @tCEH_min: CE# high hold time 646 * @tCH_min: CE# hold time 647 * @tCHZ_max: CE# high to output hi-Z 648 * @tCLH_min: CLE hold time 649 * @tCLR_min: CLE to RE# delay 650 * @tCLS_min: CLE setup time 651 * @tCOH_min: CE# high to output hold 652 * @tCS_min: CE# setup time 653 * @tDH_min: Data hold time 654 * @tDS_min: Data setup time 655 * @tFEAT_max: Busy time for Set Features and Get Features 656 * @tIR_min: Output hi-Z to RE# low 657 * @tITC_max: Interface and Timing Mode Change time 658 * @tRC_min: RE# cycle time 659 * @tREA_max: RE# access time 660 * @tREH_min: RE# high hold time 661 * @tRHOH_min: RE# high to output hold 662 * @tRHW_min: RE# high to WE# low 663 * @tRHZ_max: RE# high to output hi-Z 664 * @tRLOH_min: RE# low to output hold 665 * @tRP_min: RE# pulse width 666 * @tRR_min: Ready to RE# low (data only) 667 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 668 * rising edge of R/B#. 669 * @tWB_max: WE# high to SR[6] low 670 * @tWC_min: WE# cycle time 671 * @tWH_min: WE# high hold time 672 * @tWHR_min: WE# high to RE# low 673 * @tWP_min: WE# pulse width 674 * @tWW_min: WP# transition to WE# low 675 */ 676 struct nand_sdr_timings { 677 u64 tBERS_max; 678 u32 tCCS_min; 679 u64 tPROG_max; 680 u64 tR_max; 681 u32 tALH_min; 682 u32 tADL_min; 683 u32 tALS_min; 684 u32 tAR_min; 685 u32 tCEA_max; 686 u32 tCEH_min; 687 u32 tCH_min; 688 u32 tCHZ_max; 689 u32 tCLH_min; 690 u32 tCLR_min; 691 u32 tCLS_min; 692 u32 tCOH_min; 693 u32 tCS_min; 694 u32 tDH_min; 695 u32 tDS_min; 696 u32 tFEAT_max; 697 u32 tIR_min; 698 u32 tITC_max; 699 u32 tRC_min; 700 u32 tREA_max; 701 u32 tREH_min; 702 u32 tRHOH_min; 703 u32 tRHW_min; 704 u32 tRHZ_max; 705 u32 tRLOH_min; 706 u32 tRP_min; 707 u32 tRR_min; 708 u64 tRST_max; 709 u32 tWB_max; 710 u32 tWC_min; 711 u32 tWH_min; 712 u32 tWHR_min; 713 u32 tWP_min; 714 u32 tWW_min; 715 }; 716 717 /** 718 * enum nand_data_interface_type - NAND interface timing type 719 * @NAND_SDR_IFACE: Single Data Rate interface 720 */ 721 enum nand_data_interface_type { 722 NAND_SDR_IFACE, 723 }; 724 725 /** 726 * struct nand_data_interface - NAND interface timing 727 * @type: type of the timing 728 * @timings: The timing, type according to @type 729 */ 730 struct nand_data_interface { 731 enum nand_data_interface_type type; 732 union { 733 struct nand_sdr_timings sdr; 734 } timings; 735 }; 736 737 /** 738 * nand_get_sdr_timings - get SDR timing from data interface 739 * @conf: The data interface 740 */ 741 static inline const struct nand_sdr_timings * 742 nand_get_sdr_timings(const struct nand_data_interface *conf) 743 { 744 if (conf->type != NAND_SDR_IFACE) 745 return ERR_PTR(-EINVAL); 746 747 return &conf->timings.sdr; 748 } 749 750 /** 751 * struct nand_chip - NAND Private Flash Chip Data 752 * @mtd: MTD device registered to the MTD framework 753 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 754 * flash device 755 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the 756 * flash device. 757 * @flash_node: [BOARDSPECIFIC] device node describing this instance 758 * @read_byte: [REPLACEABLE] read one byte from the chip 759 * @read_word: [REPLACEABLE] read one word from the chip 760 * @write_byte: [REPLACEABLE] write a single byte to the chip on the 761 * low 8 I/O lines 762 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 763 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 764 * @select_chip: [REPLACEABLE] select chip nr 765 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers 766 * @block_markbad: [REPLACEABLE] mark a block bad 767 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling 768 * ALE/CLE/nCE. Also used to write command and address 769 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing 770 * device ready/busy line. If set to NULL no access to 771 * ready/busy is available and the ready/busy information 772 * is read from the chip status register. 773 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing 774 * commands to the chip. 775 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on 776 * ready. 777 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 778 * setting the read-retry mode. Mostly needed for MLC NAND. 779 * @ecc: [BOARDSPECIFIC] ECC control structure 780 * @buffers: buffer structure for read/write 781 * @buf_align: minimum buffer alignment required by a platform 782 * @hwcontrol: platform-specific hardware control structure 783 * @erase: [REPLACEABLE] erase function 784 * @scan_bbt: [REPLACEABLE] function to scan bad block table 785 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring 786 * data from array to read regs (tR). 787 * @state: [INTERN] the current state of the NAND device 788 * @oob_poi: "poison value buffer," used for laying out OOB data 789 * before writing 790 * @page_shift: [INTERN] number of address bits in a page (column 791 * address bits). 792 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 793 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 794 * @chip_shift: [INTERN] number of address bits in one chip 795 * @options: [BOARDSPECIFIC] various chip options. They can partly 796 * be set to inform nand_scan about special functionality. 797 * See the defines for further explanation. 798 * @bbt_options: [INTERN] bad block specific options. All options used 799 * here must come from bbm.h. By default, these options 800 * will be copied to the appropriate nand_bbt_descr's. 801 * @badblockpos: [INTERN] position of the bad block marker in the oob 802 * area. 803 * @badblockbits: [INTERN] minimum number of set bits in a good block's 804 * bad block marker position; i.e., BBM == 11110111b is 805 * not bad when badblockbits == 7 806 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. 807 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. 808 * Minimum amount of bit errors per @ecc_step_ds guaranteed 809 * to be correctable. If unknown, set to zero. 810 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, 811 * also from the datasheet. It is the recommended ECC step 812 * size, if known; if unknown, set to zero. 813 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 814 * set to the actually used ONFI mode if the chip is 815 * ONFI compliant or deduced from the datasheet if 816 * the NAND chip is not ONFI compliant. 817 * @numchips: [INTERN] number of physical chips 818 * @chipsize: [INTERN] the size of one chip for multichip arrays 819 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 820 * @pagebuf: [INTERN] holds the pagenumber which is currently in 821 * data_buf. 822 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is 823 * currently in data_buf. 824 * @subpagesize: [INTERN] holds the subpagesize 825 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), 826 * non 0 if ONFI supported. 827 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), 828 * non 0 if JEDEC supported. 829 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is 830 * supported, 0 otherwise. 831 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is 832 * supported, 0 otherwise. 833 * @read_retries: [INTERN] the number of read retry modes supported 834 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 835 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 836 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If 837 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 838 * means the configuration should not be applied but 839 * only checked. 840 * @bbt: [INTERN] bad block table pointer 841 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 842 * lookup. 843 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 844 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 845 * bad block scan. 846 * @controller: [REPLACEABLE] a pointer to a hardware controller 847 * structure which is shared among multiple independent 848 * devices. 849 * @priv: [OPTIONAL] pointer to private chip data 850 * @write_page: [REPLACEABLE] High-level page write function 851 */ 852 853 struct nand_chip { 854 struct mtd_info mtd; 855 void __iomem *IO_ADDR_R; 856 void __iomem *IO_ADDR_W; 857 858 int flash_node; 859 860 uint8_t (*read_byte)(struct mtd_info *mtd); 861 u16 (*read_word)(struct mtd_info *mtd); 862 void (*write_byte)(struct mtd_info *mtd, uint8_t byte); 863 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 864 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 865 void (*select_chip)(struct mtd_info *mtd, int chip); 866 int (*block_bad)(struct mtd_info *mtd, loff_t ofs); 867 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 868 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 869 int (*dev_ready)(struct mtd_info *mtd); 870 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, 871 int page_addr); 872 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 873 int (*erase)(struct mtd_info *mtd, int page); 874 int (*scan_bbt)(struct mtd_info *mtd); 875 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 876 uint32_t offset, int data_len, const uint8_t *buf, 877 int oob_required, int page, int raw); 878 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, 879 int feature_addr, uint8_t *subfeature_para); 880 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 881 int feature_addr, uint8_t *subfeature_para); 882 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 883 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, 884 const struct nand_data_interface *conf); 885 886 887 int chip_delay; 888 unsigned int options; 889 unsigned int bbt_options; 890 891 int page_shift; 892 int phys_erase_shift; 893 int bbt_erase_shift; 894 int chip_shift; 895 int numchips; 896 uint64_t chipsize; 897 int pagemask; 898 int pagebuf; 899 unsigned int pagebuf_bitflips; 900 int subpagesize; 901 uint8_t bits_per_cell; 902 uint16_t ecc_strength_ds; 903 uint16_t ecc_step_ds; 904 int onfi_timing_mode_default; 905 int badblockpos; 906 int badblockbits; 907 908 int onfi_version; 909 int jedec_version; 910 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 911 struct nand_onfi_params onfi_params; 912 #endif 913 struct nand_jedec_params jedec_params; 914 915 struct nand_data_interface *data_interface; 916 917 int read_retries; 918 919 flstate_t state; 920 921 uint8_t *oob_poi; 922 struct nand_hw_control *controller; 923 struct nand_ecclayout *ecclayout; 924 925 struct nand_ecc_ctrl ecc; 926 struct nand_buffers *buffers; 927 unsigned long buf_align; 928 struct nand_hw_control hwcontrol; 929 930 uint8_t *bbt; 931 struct nand_bbt_descr *bbt_td; 932 struct nand_bbt_descr *bbt_md; 933 934 struct nand_bbt_descr *badblock_pattern; 935 936 void *priv; 937 }; 938 939 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 940 { 941 return container_of(mtd, struct nand_chip, mtd); 942 } 943 944 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 945 { 946 return &chip->mtd; 947 } 948 949 static inline void *nand_get_controller_data(struct nand_chip *chip) 950 { 951 return chip->priv; 952 } 953 954 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 955 { 956 chip->priv = priv; 957 } 958 959 /* 960 * NAND Flash Manufacturer ID Codes 961 */ 962 #define NAND_MFR_TOSHIBA 0x98 963 #define NAND_MFR_SAMSUNG 0xec 964 #define NAND_MFR_FUJITSU 0x04 965 #define NAND_MFR_NATIONAL 0x8f 966 #define NAND_MFR_RENESAS 0x07 967 #define NAND_MFR_STMICRO 0x20 968 #define NAND_MFR_HYNIX 0xad 969 #define NAND_MFR_MICRON 0x2c 970 #define NAND_MFR_AMD 0x01 971 #define NAND_MFR_MACRONIX 0xc2 972 #define NAND_MFR_EON 0x92 973 #define NAND_MFR_SANDISK 0x45 974 #define NAND_MFR_INTEL 0x89 975 #define NAND_MFR_ATO 0x9b 976 977 /* The maximum expected count of bytes in the NAND ID sequence */ 978 #define NAND_MAX_ID_LEN 8 979 980 /* 981 * A helper for defining older NAND chips where the second ID byte fully 982 * defined the chip, including the geometry (chip size, eraseblock size, page 983 * size). All these chips have 512 bytes NAND page size. 984 */ 985 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 986 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 987 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 988 989 /* 990 * A helper for defining newer chips which report their page size and 991 * eraseblock size via the extended ID bytes. 992 * 993 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 994 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 995 * device ID now only represented a particular total chip size (and voltage, 996 * buswidth), and the page size, eraseblock size, and OOB size could vary while 997 * using the same device ID. 998 */ 999 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1000 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1001 .options = (opts) } 1002 1003 #define NAND_ECC_INFO(_strength, _step) \ 1004 { .strength_ds = (_strength), .step_ds = (_step) } 1005 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1006 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1007 1008 /** 1009 * struct nand_flash_dev - NAND Flash Device ID Structure 1010 * @name: a human-readable name of the NAND chip 1011 * @dev_id: the device ID (the second byte of the full chip ID array) 1012 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1013 * memory address as @id[0]) 1014 * @dev_id: device ID part of the full chip ID array (refers the same memory 1015 * address as @id[1]) 1016 * @id: full device ID array 1017 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1018 * well as the eraseblock size) is determined from the extended NAND 1019 * chip ID array) 1020 * @chipsize: total chip size in MiB 1021 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1022 * @options: stores various chip bit options 1023 * @id_len: The valid length of the @id. 1024 * @oobsize: OOB size 1025 * @ecc: ECC correctability and step information from the datasheet. 1026 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1027 * @ecc_strength_ds in nand_chip{}. 1028 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1029 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1030 * For example, the "4bit ECC for each 512Byte" can be set with 1031 * NAND_ECC_INFO(4, 512). 1032 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1033 * reset. Should be deduced from timings described 1034 * in the datasheet. 1035 * 1036 */ 1037 struct nand_flash_dev { 1038 char *name; 1039 union { 1040 struct { 1041 uint8_t mfr_id; 1042 uint8_t dev_id; 1043 }; 1044 uint8_t id[NAND_MAX_ID_LEN]; 1045 }; 1046 unsigned int pagesize; 1047 unsigned int chipsize; 1048 unsigned int erasesize; 1049 unsigned int options; 1050 uint16_t id_len; 1051 uint16_t oobsize; 1052 struct { 1053 uint16_t strength_ds; 1054 uint16_t step_ds; 1055 } ecc; 1056 int onfi_timing_mode_default; 1057 }; 1058 1059 /** 1060 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 1061 * @name: Manufacturer name 1062 * @id: manufacturer ID code of device. 1063 */ 1064 struct nand_manufacturers { 1065 int id; 1066 char *name; 1067 }; 1068 1069 extern struct nand_flash_dev nand_flash_ids[]; 1070 extern struct nand_manufacturers nand_manuf_ids[]; 1071 1072 extern int nand_default_bbt(struct mtd_info *mtd); 1073 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1074 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1075 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1076 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1077 int allowbbt); 1078 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1079 size_t *retlen, uint8_t *buf); 1080 1081 /* 1082 * Constants for oob configuration 1083 */ 1084 #define NAND_SMALL_BADBLOCK_POS 5 1085 #define NAND_LARGE_BADBLOCK_POS 0 1086 1087 /** 1088 * struct platform_nand_chip - chip level device structure 1089 * @nr_chips: max. number of chips to scan for 1090 * @chip_offset: chip number offset 1091 * @nr_partitions: number of partitions pointed to by partitions (or zero) 1092 * @partitions: mtd partition list 1093 * @chip_delay: R/B delay value in us 1094 * @options: Option flags, e.g. 16bit buswidth 1095 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH 1096 * @part_probe_types: NULL-terminated array of probe types 1097 */ 1098 struct platform_nand_chip { 1099 int nr_chips; 1100 int chip_offset; 1101 int nr_partitions; 1102 struct mtd_partition *partitions; 1103 int chip_delay; 1104 unsigned int options; 1105 unsigned int bbt_options; 1106 const char **part_probe_types; 1107 }; 1108 1109 /* Keep gcc happy */ 1110 struct platform_device; 1111 1112 /** 1113 * struct platform_nand_ctrl - controller level device structure 1114 * @probe: platform specific function to probe/setup hardware 1115 * @remove: platform specific function to remove/teardown hardware 1116 * @hwcontrol: platform specific hardware control structure 1117 * @dev_ready: platform specific function to read ready/busy pin 1118 * @select_chip: platform specific chip select function 1119 * @cmd_ctrl: platform specific function for controlling 1120 * ALE/CLE/nCE. Also used to write command and address 1121 * @write_buf: platform specific function for write buffer 1122 * @read_buf: platform specific function for read buffer 1123 * @read_byte: platform specific function to read one byte from chip 1124 * @priv: private data to transport driver specific settings 1125 * 1126 * All fields are optional and depend on the hardware driver requirements 1127 */ 1128 struct platform_nand_ctrl { 1129 int (*probe)(struct platform_device *pdev); 1130 void (*remove)(struct platform_device *pdev); 1131 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 1132 int (*dev_ready)(struct mtd_info *mtd); 1133 void (*select_chip)(struct mtd_info *mtd, int chip); 1134 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 1135 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 1136 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 1137 unsigned char (*read_byte)(struct mtd_info *mtd); 1138 void *priv; 1139 }; 1140 1141 /** 1142 * struct platform_nand_data - container structure for platform-specific data 1143 * @chip: chip level chip structure 1144 * @ctrl: controller level device structure 1145 */ 1146 struct platform_nand_data { 1147 struct platform_nand_chip chip; 1148 struct platform_nand_ctrl ctrl; 1149 }; 1150 1151 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION 1152 /* return the supported features. */ 1153 static inline int onfi_feature(struct nand_chip *chip) 1154 { 1155 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; 1156 } 1157 1158 /* return the supported asynchronous timing mode. */ 1159 static inline int onfi_get_async_timing_mode(struct nand_chip *chip) 1160 { 1161 if (!chip->onfi_version) 1162 return ONFI_TIMING_MODE_UNKNOWN; 1163 return le16_to_cpu(chip->onfi_params.async_timing_mode); 1164 } 1165 1166 /* return the supported synchronous timing mode. */ 1167 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) 1168 { 1169 if (!chip->onfi_version) 1170 return ONFI_TIMING_MODE_UNKNOWN; 1171 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1172 } 1173 #endif 1174 1175 int onfi_init_data_interface(struct nand_chip *chip, 1176 struct nand_data_interface *iface, 1177 enum nand_data_interface_type type, 1178 int timing_mode); 1179 1180 /* 1181 * Check if it is a SLC nand. 1182 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1183 * We do not distinguish the MLC and TLC now. 1184 */ 1185 static inline bool nand_is_slc(struct nand_chip *chip) 1186 { 1187 return chip->bits_per_cell == 1; 1188 } 1189 1190 /** 1191 * Check if the opcode's address should be sent only on the lower 8 bits 1192 * @command: opcode to check 1193 */ 1194 static inline int nand_opcode_8bits(unsigned int command) 1195 { 1196 switch (command) { 1197 case NAND_CMD_READID: 1198 case NAND_CMD_PARAM: 1199 case NAND_CMD_GET_FEATURES: 1200 case NAND_CMD_SET_FEATURES: 1201 return 1; 1202 default: 1203 break; 1204 } 1205 return 0; 1206 } 1207 1208 /* return the supported JEDEC features. */ 1209 static inline int jedec_feature(struct nand_chip *chip) 1210 { 1211 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) 1212 : 0; 1213 } 1214 1215 /* Standard NAND functions from nand_base.c */ 1216 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); 1217 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); 1218 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); 1219 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); 1220 uint8_t nand_read_byte(struct mtd_info *mtd); 1221 1222 /* get timing characteristics from ONFI timing mode. */ 1223 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1224 /* get data interface from ONFI timing mode 0, used after reset. */ 1225 const struct nand_data_interface *nand_get_default_data_interface(void); 1226 1227 int nand_check_erased_ecc_chunk(void *data, int datalen, 1228 void *ecc, int ecclen, 1229 void *extraoob, int extraooblen, 1230 int threshold); 1231 1232 int nand_check_ecc_caps(struct nand_chip *chip, 1233 const struct nand_ecc_caps *caps, int oobavail); 1234 1235 int nand_match_ecc_req(struct nand_chip *chip, 1236 const struct nand_ecc_caps *caps, int oobavail); 1237 1238 int nand_maximize_ecc(struct nand_chip *chip, 1239 const struct nand_ecc_caps *caps, int oobavail); 1240 1241 /* Reset and initialize a NAND device */ 1242 int nand_reset(struct nand_chip *chip, int chipnr); 1243 1244 #endif /* __LINUX_MTD_NAND_H */ 1245