1*672d3078SWyon Bi /* SPDX-License-Identifier: GPL-2.0 */ 2*672d3078SWyon Bi /* 3*672d3078SWyon Bi * Copyright (C) 2019 Cadence Design Systems Inc. 4*672d3078SWyon Bi */ 5*672d3078SWyon Bi 6*672d3078SWyon Bi #ifndef __PHY_DP_H_ 7*672d3078SWyon Bi #define __PHY_DP_H_ 8*672d3078SWyon Bi 9*672d3078SWyon Bi /** 10*672d3078SWyon Bi * struct phy_configure_opts_dp - DisplayPort PHY configuration set 11*672d3078SWyon Bi * 12*672d3078SWyon Bi * This structure is used to represent the configuration state of a 13*672d3078SWyon Bi * DisplayPort phy. 14*672d3078SWyon Bi */ 15*672d3078SWyon Bi struct phy_configure_opts_dp { 16*672d3078SWyon Bi /** 17*672d3078SWyon Bi * @link_rate: 18*672d3078SWyon Bi * 19*672d3078SWyon Bi * Link Rate, in Mb/s, of the main link. 20*672d3078SWyon Bi * 21*672d3078SWyon Bi * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s 22*672d3078SWyon Bi */ 23*672d3078SWyon Bi unsigned int link_rate; 24*672d3078SWyon Bi 25*672d3078SWyon Bi /** 26*672d3078SWyon Bi * @lanes: 27*672d3078SWyon Bi * 28*672d3078SWyon Bi * Number of active, consecutive, data lanes, starting from 29*672d3078SWyon Bi * lane 0, used for the transmissions on main link. 30*672d3078SWyon Bi * 31*672d3078SWyon Bi * Allowed values: 1, 2, 4 32*672d3078SWyon Bi */ 33*672d3078SWyon Bi unsigned int lanes; 34*672d3078SWyon Bi 35*672d3078SWyon Bi /** 36*672d3078SWyon Bi * @voltage: 37*672d3078SWyon Bi * 38*672d3078SWyon Bi * Voltage swing levels, as specified by DisplayPort specification, 39*672d3078SWyon Bi * to be used by particular lanes. One value per lane. 40*672d3078SWyon Bi * voltage[0] is for lane 0, voltage[1] is for lane 1, etc. 41*672d3078SWyon Bi * 42*672d3078SWyon Bi * Maximum value: 3 43*672d3078SWyon Bi */ 44*672d3078SWyon Bi unsigned int voltage[4]; 45*672d3078SWyon Bi 46*672d3078SWyon Bi /** 47*672d3078SWyon Bi * @pre: 48*672d3078SWyon Bi * 49*672d3078SWyon Bi * Pre-emphasis levels, as specified by DisplayPort specification, to be 50*672d3078SWyon Bi * used by particular lanes. One value per lane. 51*672d3078SWyon Bi * 52*672d3078SWyon Bi * Maximum value: 3 53*672d3078SWyon Bi */ 54*672d3078SWyon Bi unsigned int pre[4]; 55*672d3078SWyon Bi 56*672d3078SWyon Bi /** 57*672d3078SWyon Bi * @ssc: 58*672d3078SWyon Bi * 59*672d3078SWyon Bi * Flag indicating, whether or not to enable spread-spectrum clocking. 60*672d3078SWyon Bi * 61*672d3078SWyon Bi */ 62*672d3078SWyon Bi u8 ssc : 1; 63*672d3078SWyon Bi 64*672d3078SWyon Bi /** 65*672d3078SWyon Bi * @set_rate: 66*672d3078SWyon Bi * 67*672d3078SWyon Bi * Flag indicating, whether or not reconfigure link rate and SSC to 68*672d3078SWyon Bi * requested values. 69*672d3078SWyon Bi * 70*672d3078SWyon Bi */ 71*672d3078SWyon Bi u8 set_rate : 1; 72*672d3078SWyon Bi 73*672d3078SWyon Bi /** 74*672d3078SWyon Bi * @set_lanes: 75*672d3078SWyon Bi * 76*672d3078SWyon Bi * Flag indicating, whether or not reconfigure lane count to 77*672d3078SWyon Bi * requested value. 78*672d3078SWyon Bi * 79*672d3078SWyon Bi */ 80*672d3078SWyon Bi u8 set_lanes : 1; 81*672d3078SWyon Bi 82*672d3078SWyon Bi /** 83*672d3078SWyon Bi * @set_voltages: 84*672d3078SWyon Bi * 85*672d3078SWyon Bi * Flag indicating, whether or not reconfigure voltage swing 86*672d3078SWyon Bi * and pre-emphasis to requested values. Only lanes specified 87*672d3078SWyon Bi * by "lanes" parameter will be affected. 88*672d3078SWyon Bi * 89*672d3078SWyon Bi */ 90*672d3078SWyon Bi u8 set_voltages : 1; 91*672d3078SWyon Bi }; 92*672d3078SWyon Bi 93*672d3078SWyon Bi #endif /* __PHY_DP_H_ */ 94