1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __DWMMC_HW_H 9 #define __DWMMC_HW_H 10 11 #include <asm/io.h> 12 #include <mmc.h> 13 14 #define DWMCI_CTRL 0x000 15 #define DWMCI_PWREN 0x004 16 #define DWMCI_CLKDIV 0x008 17 #define DWMCI_CLKSRC 0x00C 18 #define DWMCI_CLKENA 0x010 19 #define DWMCI_TMOUT 0x014 20 #define DWMCI_CTYPE 0x018 21 #define DWMCI_BLKSIZ 0x01C 22 #define DWMCI_BYTCNT 0x020 23 #define DWMCI_INTMASK 0x024 24 #define DWMCI_CMDARG 0x028 25 #define DWMCI_CMD 0x02C 26 #define DWMCI_RESP0 0x030 27 #define DWMCI_RESP1 0x034 28 #define DWMCI_RESP2 0x038 29 #define DWMCI_RESP3 0x03C 30 #define DWMCI_MINTSTS 0x040 31 #define DWMCI_RINTSTS 0x044 32 #define DWMCI_STATUS 0x048 33 #define DWMCI_FIFOTH 0x04C 34 #define DWMCI_CDETECT 0x050 35 #define DWMCI_WRTPRT 0x054 36 #define DWMCI_GPIO 0x058 37 #define DWMCI_TCMCNT 0x05C 38 #define DWMCI_TBBCNT 0x060 39 #define DWMCI_DEBNCE 0x064 40 #define DWMCI_USRID 0x068 41 #define DWMCI_VERID 0x06C 42 #define DWMCI_HCON 0x070 43 #define DWMCI_UHS_REG 0x074 44 #define DWMCI_BMOD 0x080 45 #define DWMCI_PLDMND 0x084 46 #define DWMCI_DBADDR 0x088 47 #define DWMCI_IDSTS 0x08C 48 #define DWMCI_IDINTEN 0x090 49 #define DWMCI_DSCADDR 0x094 50 #define DWMCI_BUFADDR 0x098 51 #define DWMCI_CARDTHRCTL 0x100 52 #define DWMCI_DATA 0x200 53 54 /* Interrupt Mask register */ 55 #define DWMCI_INTMSK_ALL 0xffffffff 56 #define DWMCI_INTMSK_RE (1 << 1) 57 #define DWMCI_INTMSK_CDONE (1 << 2) 58 #define DWMCI_INTMSK_DTO (1 << 3) 59 #define DWMCI_INTMSK_TXDR (1 << 4) 60 #define DWMCI_INTMSK_RXDR (1 << 5) 61 #define DWMCI_INTMSK_DCRC (1 << 7) 62 #define DWMCI_INTMSK_RTO (1 << 8) 63 #define DWMCI_INTMSK_DRTO (1 << 9) 64 #define DWMCI_INTMSK_HTO (1 << 10) 65 #define DWMCI_INTMSK_FRUN (1 << 11) 66 #define DWMCI_INTMSK_HLE (1 << 12) 67 #define DWMCI_INTMSK_SBE (1 << 13) 68 #define DWMCI_INTMSK_ACD (1 << 14) 69 #define DWMCI_INTMSK_EBE (1 << 15) 70 71 /* Raw interrupt Regsiter */ 72 #define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ 73 DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) 74 #define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) 75 /* CTRL register */ 76 #define DWMCI_CTRL_RESET (1 << 0) 77 #define DWMCI_CTRL_FIFO_RESET (1 << 1) 78 #define DWMCI_CTRL_DMA_RESET (1 << 2) 79 #define DWMCI_DMA_EN (1 << 5) 80 #define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) 81 #define DWMCI_IDMAC_EN (1 << 25) 82 #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ 83 DWMCI_CTRL_DMA_RESET) 84 85 /* CMD register */ 86 #define DWMCI_CMD_RESP_EXP (1 << 6) 87 #define DWMCI_CMD_RESP_LENGTH (1 << 7) 88 #define DWMCI_CMD_CHECK_CRC (1 << 8) 89 #define DWMCI_CMD_DATA_EXP (1 << 9) 90 #define DWMCI_CMD_RW (1 << 10) 91 #define DWMCI_CMD_SEND_STOP (1 << 12) 92 #define DWMCI_CMD_ABORT_STOP (1 << 14) 93 #define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) 94 #define DWMCI_CMD_UPD_CLK (1 << 21) 95 #define DWMCI_CMD_USE_HOLD_REG (1 << 29) 96 #define DWMCI_CMD_START (1 << 31) 97 98 /* CLKENA register */ 99 #define DWMCI_CLKEN_ENABLE (1 << 0) 100 #define DWMCI_CLKEN_LOW_PWR (1 << 16) 101 102 /* Card-type registe */ 103 #define DWMCI_CTYPE_1BIT 0 104 #define DWMCI_CTYPE_4BIT (1 << 0) 105 #define DWMCI_CTYPE_8BIT (1 << 16) 106 107 /* Status Register */ 108 #define DWMCI_BUSY (1 << 9) 109 #define DWMCI_FIFO_MASK 0x1fff 110 #define DWMCI_FIFO_SHIFT 17 111 112 /* FIFOTH Register */ 113 #define MSIZE(x) ((x) << 28) 114 #define RX_WMARK(x) ((x) << 16) 115 #define TX_WMARK(x) (x) 116 #define RX_WMARK_SHIFT 16 117 #define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) 118 119 /* HCON Register */ 120 #define DMA_INTERFACE_IDMA (0x0) 121 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) 122 123 #define DWMCI_IDMAC_OWN (1 << 31) 124 #define DWMCI_IDMAC_CH (1 << 4) 125 #define DWMCI_IDMAC_FS (1 << 3) 126 #define DWMCI_IDMAC_LD (1 << 2) 127 128 /* Bus Mode Register */ 129 #define DWMCI_BMOD_IDMAC_RESET (1 << 0) 130 #define DWMCI_BMOD_IDMAC_FB (1 << 1) 131 #define DWMCI_BMOD_IDMAC_EN (1 << 7) 132 133 /* UHS register */ 134 #define DWMCI_DDR_MODE (1 << 16) 135 136 /* quirks */ 137 #define DWMCI_QUIRK_DISABLE_SMU (1 << 0) 138 139 /* 140 * DWMCI_MSIZE is uses to set burst size of multiple transaction. 141 * The burst size is set to 128 if DWMCI_MSIZE is set to 0x6. 142 */ 143 #define DWMCI_MSIZE 0x6 144 145 /* The DW MMC Controller Version */ 146 #define DW_MMC_240A 0x240a 147 148 /* sdmmc cardthrctl set */ 149 #define DWMCI_CDTHRCTRL_CONFIG (1 + (0x200 << 16)) 150 151 /** 152 * struct dwmci_host - Information about a designware MMC host 153 * 154 * @name: Device name 155 * @ioaddr: Base I/O address of controller 156 * @quirks: Quick flags - see DWMCI_QUIRK_... 157 * @caps: Capabilities - see MMC_MODE_... 158 * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL 159 * @div: Arbitrary clock divider value for use by controller 160 * @dev_index: Arbitrary device index for use by controller 161 * @dev_id: Arbitrary device ID for use by controller 162 * @buswidth: Bus width in bits (8 or 4) 163 * @fifoth_val: Value for FIFOTH register (or 0 to leave unset) 164 * @mmc: Pointer to generic MMC structure for this device 165 * @priv: Private pointer for use by controller 166 * @stride_pio: Provide the ability of accessing fifo with burst mode 167 */ 168 struct dwmci_host { 169 const char *name; 170 void *ioaddr; 171 unsigned int quirks; 172 unsigned int caps; 173 unsigned int version; 174 unsigned int clock; 175 unsigned int bus_hz; 176 unsigned int div; 177 int dev_index; 178 int dev_id; 179 int buswidth; 180 u32 fifoth_val; 181 struct mmc *mmc; 182 void *priv; 183 bool stride_pio; 184 185 void (*clksel)(struct dwmci_host *host); 186 void (*board_init)(struct dwmci_host *host); 187 188 /** 189 * Get / set a particular MMC clock frequency 190 * 191 * This is used to request the current clock frequency of the clock 192 * that drives the DWMMC peripheral. The caller will then use this 193 * information to work out the divider it needs to achieve the 194 * required MMC bus clock frequency. If you want to handle the 195 * clock external to DWMMC, use @freq to select the frequency and 196 * return that value too. Then DWMMC will put itself in bypass mode. 197 * 198 * @host: DWMMC host 199 * @freq: Frequency the host is trying to achieve 200 */ 201 unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); 202 int (*execute_tuning)(struct dwmci_host *host, u32 opcode); 203 #ifndef CONFIG_BLK 204 struct mmc_config cfg; 205 #endif 206 207 /* use fifo mode to read and write data */ 208 bool fifo_mode; 209 }; 210 211 struct dwmci_idmac { 212 u32 flags; 213 u32 cnt; 214 u32 addr; 215 u32 next_addr; 216 } __aligned(ARCH_DMA_MINALIGN); 217 218 static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) 219 { 220 writel(val, host->ioaddr + reg); 221 } 222 223 static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val) 224 { 225 writew(val, host->ioaddr + reg); 226 } 227 228 static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) 229 { 230 writeb(val, host->ioaddr + reg); 231 } 232 static inline u32 dwmci_readl(struct dwmci_host *host, int reg) 233 { 234 return readl(host->ioaddr + reg); 235 } 236 237 static inline u16 dwmci_readw(struct dwmci_host *host, int reg) 238 { 239 return readw(host->ioaddr + reg); 240 } 241 242 static inline u8 dwmci_readb(struct dwmci_host *host, int reg) 243 { 244 return readb(host->ioaddr + reg); 245 } 246 247 #ifdef CONFIG_BLK 248 /** 249 * dwmci_setup_cfg() - Set up the configuration for DWMMC 250 * 251 * This is used to set up a DWMMC device when you are using CONFIG_BLK. 252 * 253 * This should be called from your MMC driver's probe() method once you have 254 * the information required. 255 * 256 * Generally your driver will have a platform data structure which holds both 257 * the configuration (struct mmc_config) and the MMC device info (struct mmc). 258 * For example: 259 * 260 * struct rockchip_mmc_plat { 261 * struct mmc_config cfg; 262 * struct mmc mmc; 263 * }; 264 * 265 * ... 266 * 267 * Inside U_BOOT_DRIVER(): 268 * .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), 269 * 270 * To access platform data: 271 * struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 272 * 273 * See rockchip_dw_mmc.c for an example. 274 * 275 * @cfg: Configuration structure to fill in (generally &plat->mmc) 276 * @host: DWMMC host 277 * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) 278 * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) 279 */ 280 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 281 u32 max_clk, u32 min_clk); 282 283 /** 284 * dwmci_bind() - Set up a new MMC block device 285 * 286 * This is used to set up a DWMMC block device when you are using CONFIG_BLK. 287 * It should be called from your driver's bind() method. 288 * 289 * See rockchip_dw_mmc.c for an example. 290 * 291 * @dev: Device to set up 292 * @mmc: Pointer to mmc structure (normally &plat->mmc) 293 * @cfg: Empty configuration structure (generally &plat->cfg). This is 294 * normally all zeroes at this point. The only purpose of passing 295 * this in is to set mmc->cfg to it. 296 * @return 0 if OK, -ve if the block device could not be created 297 */ 298 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); 299 300 #else 301 /** 302 * add_dwmci() - Add a new DWMMC interface 303 * 304 * This is used when you are not using CONFIG_BLK. Convert your driver over! 305 * 306 * @host: DWMMC host structure 307 * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) 308 * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) 309 * @return 0 if OK, -ve on error 310 */ 311 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); 312 #endif /* !CONFIG_BLK */ 313 314 #ifdef CONFIG_DM_MMC 315 /* Export the operations to drivers */ 316 int dwmci_probe(struct udevice *dev); 317 extern const struct dm_mmc_ops dm_dwmci_ops; 318 #endif 319 320 #endif /* __DWMMC_HW_H */ 321