1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __DWMMC_HW_H 9 #define __DWMMC_HW_H 10 11 #include <asm/io.h> 12 #include <mmc.h> 13 14 #define DWMCI_CTRL 0x000 15 #define DWMCI_PWREN 0x004 16 #define DWMCI_CLKDIV 0x008 17 #define DWMCI_CLKSRC 0x00C 18 #define DWMCI_CLKENA 0x010 19 #define DWMCI_TMOUT 0x014 20 #define DWMCI_CTYPE 0x018 21 #define DWMCI_BLKSIZ 0x01C 22 #define DWMCI_BYTCNT 0x020 23 #define DWMCI_INTMASK 0x024 24 #define DWMCI_CMDARG 0x028 25 #define DWMCI_CMD 0x02C 26 #define DWMCI_RESP0 0x030 27 #define DWMCI_RESP1 0x034 28 #define DWMCI_RESP2 0x038 29 #define DWMCI_RESP3 0x03C 30 #define DWMCI_MINTSTS 0x040 31 #define DWMCI_RINTSTS 0x044 32 #define DWMCI_STATUS 0x048 33 #define DWMCI_FIFOTH 0x04C 34 #define DWMCI_CDETECT 0x050 35 #define DWMCI_WRTPRT 0x054 36 #define DWMCI_GPIO 0x058 37 #define DWMCI_TCMCNT 0x05C 38 #define DWMCI_TBBCNT 0x060 39 #define DWMCI_DEBNCE 0x064 40 #define DWMCI_USRID 0x068 41 #define DWMCI_VERID 0x06C 42 #define DWMCI_HCON 0x070 43 #define DWMCI_UHS_REG 0x074 44 #define DWMCI_BMOD 0x080 45 #define DWMCI_PLDMND 0x084 46 #define DWMCI_DBADDR 0x088 47 #define DWMCI_IDSTS 0x08C 48 #define DWMCI_IDINTEN 0x090 49 #define DWMCI_DSCADDR 0x094 50 #define DWMCI_BUFADDR 0x098 51 #define DWMCI_DATA 0x200 52 53 /* Interrupt Mask register */ 54 #define DWMCI_INTMSK_ALL 0xffffffff 55 #define DWMCI_INTMSK_RE (1 << 1) 56 #define DWMCI_INTMSK_CDONE (1 << 2) 57 #define DWMCI_INTMSK_DTO (1 << 3) 58 #define DWMCI_INTMSK_TXDR (1 << 4) 59 #define DWMCI_INTMSK_RXDR (1 << 5) 60 #define DWMCI_INTMSK_DCRC (1 << 7) 61 #define DWMCI_INTMSK_RTO (1 << 8) 62 #define DWMCI_INTMSK_DRTO (1 << 9) 63 #define DWMCI_INTMSK_HTO (1 << 10) 64 #define DWMCI_INTMSK_FRUN (1 << 11) 65 #define DWMCI_INTMSK_HLE (1 << 12) 66 #define DWMCI_INTMSK_SBE (1 << 13) 67 #define DWMCI_INTMSK_ACD (1 << 14) 68 #define DWMCI_INTMSK_EBE (1 << 15) 69 70 /* Raw interrupt Regsiter */ 71 #define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ 72 DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) 73 #define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) 74 /* CTRL register */ 75 #define DWMCI_CTRL_RESET (1 << 0) 76 #define DWMCI_CTRL_FIFO_RESET (1 << 1) 77 #define DWMCI_CTRL_DMA_RESET (1 << 2) 78 #define DWMCI_DMA_EN (1 << 5) 79 #define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) 80 #define DWMCI_IDMAC_EN (1 << 25) 81 #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ 82 DWMCI_CTRL_DMA_RESET) 83 84 /* CMD register */ 85 #define DWMCI_CMD_RESP_EXP (1 << 6) 86 #define DWMCI_CMD_RESP_LENGTH (1 << 7) 87 #define DWMCI_CMD_CHECK_CRC (1 << 8) 88 #define DWMCI_CMD_DATA_EXP (1 << 9) 89 #define DWMCI_CMD_RW (1 << 10) 90 #define DWMCI_CMD_SEND_STOP (1 << 12) 91 #define DWMCI_CMD_ABORT_STOP (1 << 14) 92 #define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) 93 #define DWMCI_CMD_UPD_CLK (1 << 21) 94 #define DWMCI_CMD_USE_HOLD_REG (1 << 29) 95 #define DWMCI_CMD_START (1 << 31) 96 97 /* CLKENA register */ 98 #define DWMCI_CLKEN_ENABLE (1 << 0) 99 #define DWMCI_CLKEN_LOW_PWR (1 << 16) 100 101 /* Card-type registe */ 102 #define DWMCI_CTYPE_1BIT 0 103 #define DWMCI_CTYPE_4BIT (1 << 0) 104 #define DWMCI_CTYPE_8BIT (1 << 16) 105 106 /* Status Register */ 107 #define DWMCI_BUSY (1 << 9) 108 #define DWMCI_FIFO_MASK 0x1fff 109 #define DWMCI_FIFO_SHIFT 17 110 111 /* FIFOTH Register */ 112 #define MSIZE(x) ((x) << 28) 113 #define RX_WMARK(x) ((x) << 16) 114 #define TX_WMARK(x) (x) 115 #define RX_WMARK_SHIFT 16 116 #define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) 117 118 /* HCON Register */ 119 #define DMA_INTERFACE_IDMA (0x0) 120 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) 121 122 #define DWMCI_IDMAC_OWN (1 << 31) 123 #define DWMCI_IDMAC_CH (1 << 4) 124 #define DWMCI_IDMAC_FS (1 << 3) 125 #define DWMCI_IDMAC_LD (1 << 2) 126 127 /* Bus Mode Register */ 128 #define DWMCI_BMOD_IDMAC_RESET (1 << 0) 129 #define DWMCI_BMOD_IDMAC_FB (1 << 1) 130 #define DWMCI_BMOD_IDMAC_EN (1 << 7) 131 132 /* UHS register */ 133 #define DWMCI_DDR_MODE (1 << 16) 134 135 /* quirks */ 136 #define DWMCI_QUIRK_DISABLE_SMU (1 << 0) 137 138 /* 139 * DWMCI_MSIZE is uses to set burst size of multiple transaction. 140 * The burst size is set to 128 if DWMCI_MSIZE is set to 0x6. 141 */ 142 #define DWMCI_MSIZE 0x6 143 144 /** 145 * struct dwmci_host - Information about a designware MMC host 146 * 147 * @name: Device name 148 * @ioaddr: Base I/O address of controller 149 * @quirks: Quick flags - see DWMCI_QUIRK_... 150 * @caps: Capabilities - see MMC_MODE_... 151 * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL 152 * @div: Arbitrary clock divider value for use by controller 153 * @dev_index: Arbitrary device index for use by controller 154 * @dev_id: Arbitrary device ID for use by controller 155 * @buswidth: Bus width in bits (8 or 4) 156 * @fifoth_val: Value for FIFOTH register (or 0 to leave unset) 157 * @mmc: Pointer to generic MMC structure for this device 158 * @priv: Private pointer for use by controller 159 * @stride_pio: Provide the ability of accessing fifo with burst mode 160 */ 161 struct dwmci_host { 162 const char *name; 163 void *ioaddr; 164 unsigned int quirks; 165 unsigned int caps; 166 unsigned int version; 167 unsigned int clock; 168 unsigned int bus_hz; 169 unsigned int div; 170 int dev_index; 171 int dev_id; 172 int buswidth; 173 u32 fifoth_val; 174 struct mmc *mmc; 175 void *priv; 176 bool stride_pio; 177 178 void (*clksel)(struct dwmci_host *host); 179 void (*board_init)(struct dwmci_host *host); 180 181 /** 182 * Get / set a particular MMC clock frequency 183 * 184 * This is used to request the current clock frequency of the clock 185 * that drives the DWMMC peripheral. The caller will then use this 186 * information to work out the divider it needs to achieve the 187 * required MMC bus clock frequency. If you want to handle the 188 * clock external to DWMMC, use @freq to select the frequency and 189 * return that value too. Then DWMMC will put itself in bypass mode. 190 * 191 * @host: DWMMC host 192 * @freq: Frequency the host is trying to achieve 193 */ 194 unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); 195 int (*execute_tuning)(struct dwmci_host *host, u32 opcode); 196 #ifndef CONFIG_BLK 197 struct mmc_config cfg; 198 #endif 199 200 /* use fifo mode to read and write data */ 201 bool fifo_mode; 202 }; 203 204 struct dwmci_idmac { 205 u32 flags; 206 u32 cnt; 207 u32 addr; 208 u32 next_addr; 209 } __aligned(ARCH_DMA_MINALIGN); 210 211 static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) 212 { 213 writel(val, host->ioaddr + reg); 214 } 215 216 static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val) 217 { 218 writew(val, host->ioaddr + reg); 219 } 220 221 static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) 222 { 223 writeb(val, host->ioaddr + reg); 224 } 225 static inline u32 dwmci_readl(struct dwmci_host *host, int reg) 226 { 227 return readl(host->ioaddr + reg); 228 } 229 230 static inline u16 dwmci_readw(struct dwmci_host *host, int reg) 231 { 232 return readw(host->ioaddr + reg); 233 } 234 235 static inline u8 dwmci_readb(struct dwmci_host *host, int reg) 236 { 237 return readb(host->ioaddr + reg); 238 } 239 240 #ifdef CONFIG_BLK 241 /** 242 * dwmci_setup_cfg() - Set up the configuration for DWMMC 243 * 244 * This is used to set up a DWMMC device when you are using CONFIG_BLK. 245 * 246 * This should be called from your MMC driver's probe() method once you have 247 * the information required. 248 * 249 * Generally your driver will have a platform data structure which holds both 250 * the configuration (struct mmc_config) and the MMC device info (struct mmc). 251 * For example: 252 * 253 * struct rockchip_mmc_plat { 254 * struct mmc_config cfg; 255 * struct mmc mmc; 256 * }; 257 * 258 * ... 259 * 260 * Inside U_BOOT_DRIVER(): 261 * .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), 262 * 263 * To access platform data: 264 * struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 265 * 266 * See rockchip_dw_mmc.c for an example. 267 * 268 * @cfg: Configuration structure to fill in (generally &plat->mmc) 269 * @host: DWMMC host 270 * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) 271 * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) 272 */ 273 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 274 u32 max_clk, u32 min_clk); 275 276 /** 277 * dwmci_bind() - Set up a new MMC block device 278 * 279 * This is used to set up a DWMMC block device when you are using CONFIG_BLK. 280 * It should be called from your driver's bind() method. 281 * 282 * See rockchip_dw_mmc.c for an example. 283 * 284 * @dev: Device to set up 285 * @mmc: Pointer to mmc structure (normally &plat->mmc) 286 * @cfg: Empty configuration structure (generally &plat->cfg). This is 287 * normally all zeroes at this point. The only purpose of passing 288 * this in is to set mmc->cfg to it. 289 * @return 0 if OK, -ve if the block device could not be created 290 */ 291 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); 292 293 #else 294 /** 295 * add_dwmci() - Add a new DWMMC interface 296 * 297 * This is used when you are not using CONFIG_BLK. Convert your driver over! 298 * 299 * @host: DWMMC host structure 300 * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) 301 * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) 302 * @return 0 if OK, -ve on error 303 */ 304 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); 305 #endif /* !CONFIG_BLK */ 306 307 #ifdef CONFIG_DM_MMC 308 /* Export the operations to drivers */ 309 int dwmci_probe(struct udevice *dev); 310 extern const struct dm_mmc_ops dm_dwmci_ops; 311 #endif 312 313 #endif /* __DWMMC_HW_H */ 314