1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co. Ltd. 3 * Author: Shawn Lin <shawn.lin@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 9 10 /* pll id */ 11 #define PLL_APLL 0 12 #define PLL_DPLL 1 13 #define PLL_GPLL 2 14 #define ARMCLK 3 15 16 /* sclk gates (special clocks) */ 17 #define SCLK_MAC 64 18 #define SCLK_SPI0 65 19 #define SCLK_NANDC 67 20 #define SCLK_SDMMC 68 21 #define SCLK_SDIO 69 22 #define SCLK_EMMC 71 23 #define SCLK_UART0 72 24 #define SCLK_UART1 73 25 #define SCLK_UART2 74 26 #define SCLK_I2S0 75 27 #define SCLK_I2S1 76 28 #define SCLK_I2S2 77 29 #define SCLK_TIMER0 78 30 #define SCLK_TIMER1 79 31 #define SCLK_SFC 80 32 #define SCLK_SDMMC_DRV 81 33 #define SCLK_SDIO_DRV 82 34 #define SCLK_EMMC_DRV 83 35 #define SCLK_SDMMC_SAMPLE 84 36 #define SCLK_SDIO_SAMPLE 85 37 #define SCLK_EMMC_SAMPLE 86 38 #define SCLK_MAC_RX 87 39 #define SCLK_MAC_TX 88 40 #define SCLK_MACREF 89 41 #define SCLK_MACREF_OUT 90 42 #define SCLK_SARADC 91 43 44 #define DCLK_VOP 187 45 46 /* aclk gates */ 47 #define ACLK_DMAC 192 48 #define ACLK_PRE 193 49 #define ACLK_CORE 194 50 #define ACLK_ENMCORE 195 51 #define ACLK_GMAC 196 52 #define ACLK_VIO0 200 53 #define ACLK_VIO1 201 54 #define ACLK_PERI 209 55 56 /* pclk gates */ 57 #define PCLK_GPIO1 256 58 #define PCLK_GPIO2 257 59 #define PCLK_GPIO3 258 60 #define PCLK_GRF 259 61 #define PCLK_I2C1 260 62 #define PCLK_I2C2 261 63 #define PCLK_I2C3 262 64 #define PCLK_SPI 263 65 #define PCLK_SFC 264 66 #define PCLK_UART0 265 67 #define PCLK_UART1 266 68 #define PCLK_UART2 267 69 #define PCLK_TSADC 268 70 #define PCLK_PWM 269 71 #define PCLK_TIMER 270 72 #define PCLK_PERI 271 73 #define PCLK_GMAC 272 74 #define PCLK_SARADC 273 75 #define PCLK_VIO 276 76 77 /* hclk gates */ 78 #define HCLK_I2S0_8CH 320 79 #define HCLK_I2S1_8CH 321 80 #define HCLK_I2S2_2CH 322 81 #define HCLK_NANDC 323 82 #define HCLK_SDMMC 324 83 #define HCLK_SDIO 325 84 #define HCLK_EMMC 326 85 #define HCLK_PERI 327 86 #define HCLK_SFC 328 87 #define HCLK_VIO 332 88 89 #define CLK_NR_CLKS (HCLK_VIO + 1) 90 91 /* reset id */ 92 #define SRST_CORE_PO_AD 0 93 #define SRST_CORE_AD 1 94 #define SRST_L2_AD 2 95 #define SRST_CPU_NIU_AD 3 96 #define SRST_CORE_PO 4 97 #define SRST_CORE 5 98 #define SRST_L2 6 99 #define SRST_CORE_DBG 8 100 #define PRST_DBG 9 101 #define RST_DAP 10 102 #define PRST_DBG_NIU 11 103 #define ARST_STRC_SYS_AD 15 104 105 #define SRST_DDRPHY_CLKDIV 16 106 #define SRST_DDRPHY 17 107 #define PRST_DDRPHY 18 108 #define PRST_HDMIPHY 19 109 #define PRST_VDACPHY 20 110 #define PRST_VADCPHY 21 111 #define PRST_MIPI_CSI_PHY 22 112 #define PRST_MIPI_DSI_PHY 23 113 #define PRST_ACODEC 24 114 #define ARST_BUS_NIU 25 115 #define PRST_TOP_NIU 26 116 #define ARST_INTMEM 27 117 #define HRST_ROM 28 118 #define ARST_DMAC 29 119 #define SRST_MSCH_NIU 30 120 #define PRST_MSCH_NIU 31 121 122 #define PRST_DDRUPCTL 32 123 #define NRST_DDRUPCTL 33 124 #define PRST_DDRMON 34 125 #define HRST_I2S0_8CH 35 126 #define MRST_I2S0_8CH 36 127 #define HRST_I2S1_2CH 37 128 #define MRST_IS21_2CH 38 129 #define HRST_I2S2_2CH 39 130 #define MRST_I2S2_2CH 40 131 #define HRST_CRYPTO 41 132 #define SRST_CRYPTO 42 133 #define PRST_SPI 43 134 #define SRST_SPI 44 135 #define PRST_UART0 45 136 #define PRST_UART1 46 137 #define PRST_UART2 47 138 139 #define SRST_UART0 48 140 #define SRST_UART1 49 141 #define SRST_UART2 50 142 #define PRST_I2C1 51 143 #define PRST_I2C2 52 144 #define PRST_I2C3 53 145 #define SRST_I2C1 54 146 #define SRST_I2C2 55 147 #define SRST_I2C3 56 148 #define PRST_PWM1 58 149 #define SRST_PWM1 60 150 #define PRST_WDT 61 151 #define PRST_GPIO1 62 152 #define PRST_GPIO2 63 153 154 #define PRST_GPIO3 64 155 #define PRST_GRF 65 156 #define PRST_EFUSE 66 157 #define PRST_EFUSE512 67 158 #define PRST_TIMER0 68 159 #define SRST_TIMER0 69 160 #define SRST_TIMER1 70 161 #define PRST_TSADC 71 162 #define SRST_TSADC 72 163 #define PRST_SARADC 73 164 #define SRST_SARADC 74 165 #define HRST_SYSBUS 75 166 #define PRST_USBGRF 76 167 168 #define ARST_PERIPH_NIU 80 169 #define HRST_PERIPH_NIU 81 170 #define PRST_PERIPH_NIU 82 171 #define HRST_PERIPH 83 172 #define HRST_SDMMC 84 173 #define HRST_SDIO 85 174 #define HRST_EMMC 86 175 #define HRST_NANDC 87 176 #define NRST_NANDC 88 177 #define HRST_SFC 89 178 #define SRST_SFC 90 179 #define ARST_GMAC 91 180 #define HRST_OTG 92 181 #define SRST_OTG 93 182 #define SRST_OTG_ADP 94 183 #define HRST_HOST0 95 184 185 #define HRST_HOST0_AUX 96 186 #define HRST_HOST0_ARB 97 187 #define SRST_HOST0_EHCIPHY 98 188 #define SRST_HOST0_UTMI 99 189 #define SRST_USBPOR 100 190 #define SRST_UTMI0 101 191 #define SRST_UTMI1 102 192 193 #define ARST_VIO0_NIU 102 194 #define ARST_VIO1_NIU 103 195 #define HRST_VIO_NIU 104 196 #define PRST_VIO_NIU 105 197 #define ARST_VOP 106 198 #define HRST_VOP 107 199 #define DRST_VOP 108 200 #define ARST_IEP 109 201 #define HRST_IEP 110 202 #define ARST_RGA 111 203 #define HRST_RGA 112 204 #define SRST_RGA 113 205 #define PRST_CVBS 114 206 #define PRST_HDMI 115 207 #define SRST_HDMI 116 208 #define PRST_MIPI_DSI 117 209 210 #define ARST_ISP_NIU 118 211 #define HRST_ISP_NIU 119 212 #define HRST_ISP 120 213 #define SRST_ISP 121 214 #define ARST_VIP0 122 215 #define HRST_VIP0 123 216 #define PRST_VIP0 124 217 #define ARST_VIP1 125 218 #define HRST_VIP1 126 219 #define PRST_VIP1 127 220 #define ARST_VIP2 128 221 #define HRST_VIP2 129 222 #define PRST_VIP2 120 223 #define ARST_VIP3 121 224 #define HRST_VIP3 122 225 #define PRST_VIP4 123 226 227 #define PRST_CIF1TO4 124 228 #define SRST_CVBS_CLK 125 229 #define HRST_CVBS 126 230 231 #define ARST_VPU_NIU 140 232 #define HRST_VPU_NIU 141 233 #define ARST_VPU 142 234 #define HRST_VPU 143 235 #define ARST_RKVDEC_NIU 144 236 #define HRST_RKVDEC_NIU 145 237 #define ARST_RKVDEC 146 238 #define HRST_RKVDEC 147 239 #define SRST_RKVDEC_CABAC 148 240 #define SRST_RKVDEC_CORE 149 241 #define ARST_RKVENC_NIU 150 242 #define HRST_RKVENC_NIU 151 243 #define ARST_RKVENC 152 244 #define HRST_RKVENC 153 245 #define SRST_RKVENC_CORE 154 246 247 #define SRST_DSP_CORE 156 248 #define SRST_DSP_SYS 157 249 #define SRST_DSP_GLOBAL 158 250 #define SRST_DSP_OECM 159 251 #define PRST_DSP_IOP_NIU 160 252 #define ARST_DSP_EPP_NIU 161 253 #define ARST_DSP_EDP_NIU 162 254 #define PRST_DSP_DBG_NIU 163 255 #define PRST_DSP_CFG_NIU 164 256 #define PRST_DSP_GRF 165 257 #define PRST_DSP_MAILBOX 166 258 #define PRST_DSP_INTC 167 259 #define PRST_DSP_PFM_MON 169 260 #define SRST_DSP_PFM_MON 170 261 #define ARST_DSP_EDAP_NIU 171 262 263 #define SRST_PMU 172 264 #define SRST_PMU_I2C0 173 265 #define PRST_PMU_I2C0 174 266 #define PRST_PMU_GPIO0 175 267 #define PRST_PMU_INTMEM 176 268 #define PRST_PMU_PWM0 177 269 #define SRST_PMU_PWM0 178 270 #define PRST_PMU_GRF 179 271 #define SRST_PMU_NIU 180 272 #define SRST_PMU_PVTM 181 273 #define ARST_DSP_EDP_PERF 184 274 #define ARST_DSP_EPP_PERF 185 275 276 #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ 277