1*c7964f86SEnric Balletbò i Serra /* 2*c7964f86SEnric Balletbò i Serra * ti_omap3_common.h 3*c7964f86SEnric Balletbò i Serra * 4*c7964f86SEnric Balletbò i Serra * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5*c7964f86SEnric Balletbò i Serra * 6*c7964f86SEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 7*c7964f86SEnric Balletbò i Serra * 8*c7964f86SEnric Balletbò i Serra * For more details, please see the technical documents listed at 9*c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/omap3530 10*c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/omap3630 11*c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/dm3730 12*c7964f86SEnric Balletbò i Serra */ 13*c7964f86SEnric Balletbò i Serra 14*c7964f86SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP3_COMMON_H__ 15*c7964f86SEnric Balletbò i Serra #define __CONFIG_TI_OMAP3_COMMON_H__ 16*c7964f86SEnric Balletbò i Serra 17*c7964f86SEnric Balletbò i Serra #define CONFIG_OMAP34XX 18*c7964f86SEnric Balletbò i Serra 19*c7964f86SEnric Balletbò i Serra #include <asm/arch/cpu.h> 20*c7964f86SEnric Balletbò i Serra #include <asm/arch/omap3.h> 21*c7964f86SEnric Balletbò i Serra 22*c7964f86SEnric Balletbò i Serra /* The chip has SDRC controller */ 23*c7964f86SEnric Balletbò i Serra #define CONFIG_SDRC 24*c7964f86SEnric Balletbò i Serra 25*c7964f86SEnric Balletbò i Serra /* Clock Defines */ 26*c7964f86SEnric Balletbò i Serra #define V_OSCK 26000000 /* Clock output from T2 */ 27*c7964f86SEnric Balletbò i Serra #define V_SCLK (V_OSCK >> 1) 28*c7964f86SEnric Balletbò i Serra 29*c7964f86SEnric Balletbò i Serra /* NS16550 Configuration */ 30*c7964f86SEnric Balletbò i Serra #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 31*c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550 32*c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL 33*c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE (-4) 34*c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 35*c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 36*c7964f86SEnric Balletbò i Serra 115200} 37*c7964f86SEnric Balletbò i Serra 38*c7964f86SEnric Balletbò i Serra /* Select serial console configuration */ 39*c7964f86SEnric Balletbò i Serra #define CONFIG_CONS_INDEX 3 40*c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 41*c7964f86SEnric Balletbò i Serra #define CONFIG_SERIAL3 3 42*c7964f86SEnric Balletbò i Serra 43*c7964f86SEnric Balletbò i Serra /* Physical Memory Map */ 44*c7964f86SEnric Balletbò i Serra #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 45*c7964f86SEnric Balletbò i Serra #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 46*c7964f86SEnric Balletbò i Serra 47*c7964f86SEnric Balletbò i Serra /* 48*c7964f86SEnric Balletbò i Serra * OMAP3 has 12 GP timers, they can be driven by the system clock 49*c7964f86SEnric Balletbò i Serra * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 50*c7964f86SEnric Balletbò i Serra * This rate is divided by a local divisor. 51*c7964f86SEnric Balletbò i Serra */ 52*c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 53*c7964f86SEnric Balletbò i Serra 54*c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_MONITOR_LEN (256 << 10) 55*c7964f86SEnric Balletbò i Serra 56*c7964f86SEnric Balletbò i Serra /* TWL4030 */ 57*c7964f86SEnric Balletbò i Serra #define CONFIG_TWL4030_POWER 1 58*c7964f86SEnric Balletbò i Serra 59*c7964f86SEnric Balletbò i Serra /* SPL */ 60*c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40200800 61*c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_MAX_SIZE (54 * 1024) 62*c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 63*c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_POWER_SUPPORT 64*c7964f86SEnric Balletbò i Serra 65*c7964f86SEnric Balletbò i Serra #ifdef CONFIG_NAND 66*c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_NAND_SUPPORT 67*c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_NAND_SIMPLE 68*c7964f86SEnric Balletbò i Serra #endif 69*c7964f86SEnric Balletbò i Serra 70*c7964f86SEnric Balletbò i Serra /* Now bring in the rest of the common code. */ 71*c7964f86SEnric Balletbò i Serra #include <configs/ti_armv7_common.h> 72*c7964f86SEnric Balletbò i Serra 73*c7964f86SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ 74