1c7964f86SEnric Balletbò i Serra /* 2c7964f86SEnric Balletbò i Serra * ti_omap3_common.h 3c7964f86SEnric Balletbò i Serra * 4c7964f86SEnric Balletbò i Serra * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5c7964f86SEnric Balletbò i Serra * 6c7964f86SEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 7c7964f86SEnric Balletbò i Serra * 8c7964f86SEnric Balletbò i Serra * For more details, please see the technical documents listed at 9c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/omap3530 10c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/omap3630 11c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/dm3730 12c7964f86SEnric Balletbò i Serra */ 13c7964f86SEnric Balletbò i Serra 14c7964f86SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP3_COMMON_H__ 15c7964f86SEnric Balletbò i Serra #define __CONFIG_TI_OMAP3_COMMON_H__ 16c7964f86SEnric Balletbò i Serra 17*3709844fSAlbert ARIBAUD /* 18*3709844fSAlbert ARIBAUD * High Level Configuration Options 19*3709844fSAlbert ARIBAUD */ 20*3709844fSAlbert ARIBAUD 21c7964f86SEnric Balletbò i Serra #include <asm/arch/cpu.h> 22987ec585SNishanth Menon #include <asm/arch/omap.h> 23c7964f86SEnric Balletbò i Serra 24c7964f86SEnric Balletbò i Serra /* The chip has SDRC controller */ 25c7964f86SEnric Balletbò i Serra #define CONFIG_SDRC 26c7964f86SEnric Balletbò i Serra 27c7964f86SEnric Balletbò i Serra /* Clock Defines */ 28c7964f86SEnric Balletbò i Serra #define V_OSCK 26000000 /* Clock output from T2 */ 29c7964f86SEnric Balletbò i Serra #define V_SCLK (V_OSCK >> 1) 30c7964f86SEnric Balletbò i Serra 31c7964f86SEnric Balletbò i Serra /* NS16550 Configuration */ 32c7964f86SEnric Balletbò i Serra #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 33c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 34b3f4ca11SSimon Glass #ifdef CONFIG_SPL_BUILD 35c7964f86SEnric Balletbò i Serra # define CONFIG_SYS_NS16550_SERIAL 36c7964f86SEnric Balletbò i Serra # define CONFIG_SYS_NS16550_REG_SIZE (-4) 37b3f4ca11SSimon Glass #endif 38c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 39c7964f86SEnric Balletbò i Serra 115200} 40c7964f86SEnric Balletbò i Serra 41c7964f86SEnric Balletbò i Serra /* Select serial console configuration */ 42c7964f86SEnric Balletbò i Serra #define CONFIG_CONS_INDEX 3 43b3f4ca11SSimon Glass #ifdef CONFIG_SPL_BUILD 44c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 45c7964f86SEnric Balletbò i Serra #define CONFIG_SERIAL3 3 46b3f4ca11SSimon Glass #endif 47c7964f86SEnric Balletbò i Serra 48c7964f86SEnric Balletbò i Serra /* Physical Memory Map */ 49c7964f86SEnric Balletbò i Serra #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 50c7964f86SEnric Balletbò i Serra #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 51c7964f86SEnric Balletbò i Serra 52c7964f86SEnric Balletbò i Serra /* 53c7964f86SEnric Balletbò i Serra * OMAP3 has 12 GP timers, they can be driven by the system clock 54c7964f86SEnric Balletbò i Serra * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 55c7964f86SEnric Balletbò i Serra * This rate is divided by a local divisor. 56c7964f86SEnric Balletbò i Serra */ 57c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 58c7964f86SEnric Balletbò i Serra 59c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_MONITOR_LEN (256 << 10) 60c7964f86SEnric Balletbò i Serra 61c7964f86SEnric Balletbò i Serra /* SPL */ 62c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40200800 63d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 64d3289aacSTom Rini (64 << 20)) 65d3289aacSTom Rini 66c7964f86SEnric Balletbò i Serra #ifdef CONFIG_NAND 67df4dbb5dSTom Rini #define CONFIG_SYS_NAND_BASE 0x30000000 68c7964f86SEnric Balletbò i Serra #endif 69c7964f86SEnric Balletbò i Serra 70c7964f86SEnric Balletbò i Serra /* Now bring in the rest of the common code. */ 719a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h> 72c7964f86SEnric Balletbò i Serra 73c7964f86SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ 74