1 /* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_RV1106_COMMON_H 8 #define __CONFIG_RV1106_COMMON_H 9 10 #define CFG_CPUID_OFFSET 0xa 11 12 #include "rockchip-common.h" 13 14 #define COUNTER_FREQUENCY 24000000 15 #define CONFIG_SYS_MALLOC_LEN (16 << 20) 16 #define CONFIG_SYS_CBSIZE 1024 17 #define CONFIG_SYS_NS16550_MEM32 18 19 #ifdef CONFIG_SUPPORT_USBPLUG 20 #define CONFIG_SYS_TEXT_BASE 0x00000000 21 #else 22 #define CONFIG_SYS_TEXT_BASE 0x00200000 23 #endif 24 #define CONFIG_SYS_INIT_SP_ADDR 0x00400000 25 #define CONFIG_SYS_LOAD_ADDR 0x00e00800 26 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 27 #define GICD_BASE 0xff1f1000 28 #define GICC_BASE 0xff1f2000 29 #define CONFIG_SYS_SDRAM_BASE 0 30 #define SDRAM_MAX_SIZE 0xff000000 31 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 32 #define CONFIG_PERIPH_DEVICE_START_ADDR (CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE) 33 #define CONFIG_PERIPH_DEVICE_END_ADDR SZ_4G 34 35 /* SPL */ 36 #define CONFIG_SPL_FRAMEWORK 37 #define CONFIG_SPL_TEXT_BASE 0x00000000 38 #define CONFIG_SPL_MAX_SIZE 0x28000 39 #define CONFIG_SPL_BSS_START_ADDR 0x001fe000 40 #define CONFIG_SPL_BSS_MAX_SIZE 0x20000 41 #define CONFIG_SPL_STACK 0x001fe000 42 43 /* secure otp */ 44 #define OTP_UBOOT_ROLLBACK_OFFSET 0xe0 45 #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 46 #define OTP_ALL_ONES_NUM_BITS 32 47 #define OTP_SECURE_BOOT_ENABLE_ADDR 0x80 48 #define OTP_SECURE_BOOT_ENABLE_SIZE 2 49 #define OTP_RSA_HASH_ADDR 0x90 50 #define OTP_RSA_HASH_SIZE 32 51 52 /* MMC/SD IP block */ 53 #define CONFIG_BOUNCE_BUFFER 54 55 #ifndef CONFIG_SPL_BUILD 56 /* usb mass storage */ 57 #define CONFIG_USB_FUNCTION_MASS_STORAGE 58 #define CONFIG_ROCKUSB_G_DNL_PID 0x110c 59 60 #define CONFIG_LIB_HW_RAND 61 #define CONFIG_PREBOOT 62 63 #if CONFIG_USB_FUNCTION_DFU 64 #define CONFIG_SET_DFU_ALT_INFO 65 #endif 66 67 #ifdef CONFIG_ENV_MEM_LAYOUT 68 #define ENV_MEM_LAYOUT_SETTINGS CONFIG_ENV_MEM_LAYOUT_SETTINGS 69 #else 70 /* 71 * Image: 0 - 8M 72 * zImage: 8 - 12M 73 * fdt: 12 - 13M 74 * ramdisk: 14 ... 75 */ 76 #define ENV_MEM_LAYOUT_SETTINGS \ 77 "scriptaddr=0x00b00000\0" \ 78 "pxefile_addr_r=0x00c00000\0" \ 79 "fdt_addr_r=0x00c00000\0" \ 80 "kernel_addr_c=0x00808000\0" \ 81 "kernel_addr_r=0x00008000\0" \ 82 "ramdisk_addr_r=0x000e00000\0" 83 #endif 84 85 #define CONFIG_EXTRA_ENV_SETTINGS \ 86 ENV_MEM_LAYOUT_SETTINGS \ 87 ROCKCHIP_DEVICE_SETTINGS \ 88 RKIMG_DET_BOOTDEV 89 90 #undef RKIMG_BOOTCOMMAND 91 #ifdef CONFIG_FIT_SIGNATURE 92 #define RKIMG_BOOTCOMMAND \ 93 "boot_fit;" 94 #else 95 #define RKIMG_BOOTCOMMAND \ 96 "boot_fit;" \ 97 "boot_android ${devtype} ${devnum};" 98 #endif 99 100 /* Update define for tiny image */ 101 #ifdef CONFIG_ROCKCHIP_IMAGE_TINY 102 #undef RKIMG_BOOTCOMMAND 103 #undef RKIMG_DET_BOOTDEV 104 #undef CONFIG_EXTRA_ENV_SETTINGS 105 #undef CONFIG_AUTO_COMPLETE 106 #undef CONFIG_SYS_LONGHELP 107 #undef CONFIG_ZLIB 108 #undef CONFIG_GZIP 109 /* TODO: #define CONFIG_LIB_HW_RAND */ 110 111 #define RKIMG_BOOTCOMMAND "boot_fit;" 112 #define CONFIG_EXTRA_ENV_SETTINGS ENV_MEM_LAYOUT_SETTINGS 113 #endif 114 #endif /* !CONFIG_SPL_BUILD */ 115 116 #endif 117