17e26af38SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 27e26af38SJoseph Chen /* 37e26af38SJoseph Chen * (C) Copyright 2020 Rockchip Electronics Co., Ltd 47e26af38SJoseph Chen * 57e26af38SJoseph Chen */ 67e26af38SJoseph Chen 77e26af38SJoseph Chen #ifndef __CONFIG_RK3568_COMMON_H 87e26af38SJoseph Chen #define __CONFIG_RK3568_COMMON_H 97e26af38SJoseph Chen 107e26af38SJoseph Chen #include "rockchip-common.h" 117e26af38SJoseph Chen 127e26af38SJoseph Chen #define CONFIG_SPL_FRAMEWORK 137e26af38SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 147e26af38SJoseph Chen #define CONFIG_SPL_MAX_SIZE 0x00020000 157e26af38SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 167e26af38SJoseph Chen #define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 177e26af38SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 187e26af38SJoseph Chen 197e26af38SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 207e26af38SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 217e26af38SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 227e26af38SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00600000 237e26af38SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 247e26af38SJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00800800 257e26af38SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 267e26af38SJoseph Chen #define COUNTER_FREQUENCY 24000000 277e26af38SJoseph Chen 287e26af38SJoseph Chen #define GICD_BASE 0xfd400000 297e26af38SJoseph Chen #define GICR_BASE 0xfd460000 307e26af38SJoseph Chen 317e26af38SJoseph Chen /* MMC/SD IP block */ 327e26af38SJoseph Chen #define CONFIG_BOUNCE_BUFFER 337e26af38SJoseph Chen #define CONFIG_SUPPORT_EMMC_RPMB 347e26af38SJoseph Chen 357e26af38SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 367e26af38SJoseph Chen #define SDRAM_MAX_SIZE 0xf0000000 377e26af38SJoseph Chen #define CONFIG_PREBOOT 387e26af38SJoseph Chen 397e26af38SJoseph Chen #ifndef CONFIG_SPL_BUILD 407e26af38SJoseph Chen /* usb mass storage */ 417e26af38SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 427e26af38SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350a 437e26af38SJoseph Chen 447e26af38SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 457e26af38SJoseph Chen "scriptaddr=0x00500000\0" \ 467e26af38SJoseph Chen "pxefile_addr_r=0x00600000\0" \ 477e26af38SJoseph Chen "fdt_addr_r=0x01f00000\0" \ 487e26af38SJoseph Chen "kernel_addr_no_bl32_r=0x00280000\0" \ 497e26af38SJoseph Chen "kernel_addr_r=0x00680000\0" \ 507e26af38SJoseph Chen "kernel_addr_c=0x04080000\0" \ 517e26af38SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 527e26af38SJoseph Chen 537e26af38SJoseph Chen #include <config_distro_bootcmd.h> 547e26af38SJoseph Chen 557e26af38SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 567e26af38SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 577e26af38SJoseph Chen "partitions=" PARTS_DEFAULT \ 587e26af38SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 597e26af38SJoseph Chen RKIMG_DET_BOOTDEV \ 607e26af38SJoseph Chen BOOTENV 617e26af38SJoseph Chen #endif 627e26af38SJoseph Chen 63*858bd926SRen Jianing /* rockchip ohci host driver */ 64*858bd926SRen Jianing #define CONFIG_USB_OHCI_NEW 65*858bd926SRen Jianing #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 66*858bd926SRen Jianing 677e26af38SJoseph Chen #endif 68