1*7e26af38SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2*7e26af38SJoseph Chen /* 3*7e26af38SJoseph Chen * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4*7e26af38SJoseph Chen * 5*7e26af38SJoseph Chen */ 6*7e26af38SJoseph Chen 7*7e26af38SJoseph Chen #ifndef __CONFIG_RK3568_COMMON_H 8*7e26af38SJoseph Chen #define __CONFIG_RK3568_COMMON_H 9*7e26af38SJoseph Chen 10*7e26af38SJoseph Chen #include "rockchip-common.h" 11*7e26af38SJoseph Chen 12*7e26af38SJoseph Chen #define CONFIG_SPL_FRAMEWORK 13*7e26af38SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 14*7e26af38SJoseph Chen #define CONFIG_SPL_MAX_SIZE 0x00020000 15*7e26af38SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16*7e26af38SJoseph Chen #define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 17*7e26af38SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 18*7e26af38SJoseph Chen 19*7e26af38SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20*7e26af38SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 21*7e26af38SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 22*7e26af38SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00600000 23*7e26af38SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 24*7e26af38SJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00800800 25*7e26af38SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 26*7e26af38SJoseph Chen #define COUNTER_FREQUENCY 24000000 27*7e26af38SJoseph Chen 28*7e26af38SJoseph Chen #define GICD_BASE 0xfd400000 29*7e26af38SJoseph Chen #define GICR_BASE 0xfd460000 30*7e26af38SJoseph Chen 31*7e26af38SJoseph Chen /* MMC/SD IP block */ 32*7e26af38SJoseph Chen #define CONFIG_BOUNCE_BUFFER 33*7e26af38SJoseph Chen #define CONFIG_SUPPORT_EMMC_RPMB 34*7e26af38SJoseph Chen 35*7e26af38SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 36*7e26af38SJoseph Chen #define SDRAM_MAX_SIZE 0xf0000000 37*7e26af38SJoseph Chen #define CONFIG_PREBOOT 38*7e26af38SJoseph Chen 39*7e26af38SJoseph Chen #ifndef CONFIG_SPL_BUILD 40*7e26af38SJoseph Chen /* usb mass storage */ 41*7e26af38SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 42*7e26af38SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350a 43*7e26af38SJoseph Chen 44*7e26af38SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 45*7e26af38SJoseph Chen "scriptaddr=0x00500000\0" \ 46*7e26af38SJoseph Chen "pxefile_addr_r=0x00600000\0" \ 47*7e26af38SJoseph Chen "fdt_addr_r=0x01f00000\0" \ 48*7e26af38SJoseph Chen "kernel_addr_no_bl32_r=0x00280000\0" \ 49*7e26af38SJoseph Chen "kernel_addr_r=0x00680000\0" \ 50*7e26af38SJoseph Chen "kernel_addr_c=0x04080000\0" \ 51*7e26af38SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 52*7e26af38SJoseph Chen 53*7e26af38SJoseph Chen #include <config_distro_bootcmd.h> 54*7e26af38SJoseph Chen 55*7e26af38SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 56*7e26af38SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 57*7e26af38SJoseph Chen "partitions=" PARTS_DEFAULT \ 58*7e26af38SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 59*7e26af38SJoseph Chen RKIMG_DET_BOOTDEV \ 60*7e26af38SJoseph Chen BOOTENV 61*7e26af38SJoseph Chen #endif 62*7e26af38SJoseph Chen 63*7e26af38SJoseph Chen #endif 64