17e26af38SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 27e26af38SJoseph Chen /* 37e26af38SJoseph Chen * (C) Copyright 2020 Rockchip Electronics Co., Ltd 47e26af38SJoseph Chen * 57e26af38SJoseph Chen */ 67e26af38SJoseph Chen 77e26af38SJoseph Chen #ifndef __CONFIG_RK3568_COMMON_H 87e26af38SJoseph Chen #define __CONFIG_RK3568_COMMON_H 97e26af38SJoseph Chen 107e26af38SJoseph Chen #include "rockchip-common.h" 117e26af38SJoseph Chen 127e26af38SJoseph Chen #define CONFIG_SPL_FRAMEWORK 137e26af38SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 14*5d96bba9SYifeng Zhao #define CONFIG_SPL_MAX_SIZE 0x00038000 157e26af38SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16*5d96bba9SYifeng Zhao #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 177e26af38SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 187e26af38SJoseph Chen 197e26af38SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 207e26af38SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 217e26af38SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 22186b0010SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00a00000 23186b0010SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 24186b0010SJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00c00800 257e26af38SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 267e26af38SJoseph Chen #define COUNTER_FREQUENCY 24000000 277e26af38SJoseph Chen 287e26af38SJoseph Chen #define GICD_BASE 0xfd400000 297e26af38SJoseph Chen #define GICR_BASE 0xfd460000 305033f049SJoseph Chen #define GICC_BASE 0xfd800000 317e26af38SJoseph Chen 327e26af38SJoseph Chen /* MMC/SD IP block */ 337e26af38SJoseph Chen #define CONFIG_BOUNCE_BUFFER 3469b42caeSJon Lin 3569b42caeSJon Lin /* Nand */ 3669b42caeSJon Lin #define CONFIG_SYS_MAX_NAND_DEVICE 1 3769b42caeSJon Lin #define CONFIG_SYS_NAND_ONFI_DETECTION 3869b42caeSJon Lin #define CONFIG_SYS_NAND_PAGE_SIZE 2048 3969b42caeSJon Lin #define CONFIG_SYS_NAND_PAGE_COUNT 64 4069b42caeSJon Lin #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 4169b42caeSJon Lin 427e26af38SJoseph Chen #define CONFIG_SUPPORT_EMMC_RPMB 437e26af38SJoseph Chen 447e26af38SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 457e26af38SJoseph Chen #define SDRAM_MAX_SIZE 0xf0000000 467e26af38SJoseph Chen #define CONFIG_PREBOOT 477e26af38SJoseph Chen 487e26af38SJoseph Chen #ifndef CONFIG_SPL_BUILD 497e26af38SJoseph Chen /* usb mass storage */ 507e26af38SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 517e26af38SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350a 527e26af38SJoseph Chen 537e26af38SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 54186b0010SJoseph Chen "scriptaddr=0x00b00000\0" \ 55186b0010SJoseph Chen "pxefile_addr_r=0x00a00000\0" \ 565033f049SJoseph Chen "fdt_addr_r=0x0a100000\0" \ 577e26af38SJoseph Chen "kernel_addr_no_bl32_r=0x00280000\0" \ 58186b0010SJoseph Chen "kernel_addr_r=0x00a80000\0" \ 597e26af38SJoseph Chen "kernel_addr_c=0x04080000\0" \ 607e26af38SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 617e26af38SJoseph Chen 627e26af38SJoseph Chen #include <config_distro_bootcmd.h> 637e26af38SJoseph Chen 647e26af38SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 657e26af38SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 667e26af38SJoseph Chen "partitions=" PARTS_DEFAULT \ 677e26af38SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 687e26af38SJoseph Chen RKIMG_DET_BOOTDEV \ 697e26af38SJoseph Chen BOOTENV 705033f049SJoseph Chen 715033f049SJoseph Chen #undef RKIMG_BOOTCOMMAND 725033f049SJoseph Chen #define RKIMG_BOOTCOMMAND \ 735033f049SJoseph Chen "boot_fit;" \ 745033f049SJoseph Chen "boot_android ${devtype} ${devnum};" 757e26af38SJoseph Chen #endif 767e26af38SJoseph Chen 77858bd926SRen Jianing /* rockchip ohci host driver */ 78858bd926SRen Jianing #define CONFIG_USB_OHCI_NEW 79858bd926SRen Jianing #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 80858bd926SRen Jianing 817e26af38SJoseph Chen #endif 82