17e26af38SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 27e26af38SJoseph Chen /* 37e26af38SJoseph Chen * (C) Copyright 2020 Rockchip Electronics Co., Ltd 47e26af38SJoseph Chen * 57e26af38SJoseph Chen */ 67e26af38SJoseph Chen 77e26af38SJoseph Chen #ifndef __CONFIG_RK3568_COMMON_H 87e26af38SJoseph Chen #define __CONFIG_RK3568_COMMON_H 97e26af38SJoseph Chen 107e26af38SJoseph Chen #include "rockchip-common.h" 117e26af38SJoseph Chen 127e26af38SJoseph Chen #define CONFIG_SPL_FRAMEWORK 137e26af38SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 145d96bba9SYifeng Zhao #define CONFIG_SPL_MAX_SIZE 0x00038000 157e26af38SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 165d96bba9SYifeng Zhao #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 177e26af38SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 187e26af38SJoseph Chen 197e26af38SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 207e26af38SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 217e26af38SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 225f73fdb1SYifeng Zhao 235f73fdb1SYifeng Zhao #ifdef CONFIG_SUPPORT_USBPLUG 245f73fdb1SYifeng Zhao #define CONFIG_SYS_TEXT_BASE 0x00000000 255f73fdb1SYifeng Zhao #else 26186b0010SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00a00000 275f73fdb1SYifeng Zhao #endif 285f73fdb1SYifeng Zhao 29186b0010SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 30186b0010SJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00c00800 317e26af38SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 327e26af38SJoseph Chen #define COUNTER_FREQUENCY 24000000 337e26af38SJoseph Chen 347e26af38SJoseph Chen #define GICD_BASE 0xfd400000 357e26af38SJoseph Chen #define GICR_BASE 0xfd460000 365033f049SJoseph Chen #define GICC_BASE 0xfd800000 377e26af38SJoseph Chen 38219085f0SJason Zhu /* secure otp */ 39219085f0SJason Zhu #define OTP_UBOOT_ROLLBACK_OFFSET 0xe0 40219085f0SJason Zhu #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 41219085f0SJason Zhu #define OTP_ALL_ONES_NUM_BITS 32 42219085f0SJason Zhu #define OTP_SECURE_BOOT_ENABLE_ADDR 0x80 43219085f0SJason Zhu #define OTP_SECURE_BOOT_ENABLE_SIZE 2 44219085f0SJason Zhu #define OTP_RSA_HASH_ADDR 0x90 45219085f0SJason Zhu #define OTP_RSA_HASH_SIZE 32 46219085f0SJason Zhu 477e26af38SJoseph Chen /* MMC/SD IP block */ 487e26af38SJoseph Chen #define CONFIG_BOUNCE_BUFFER 49*5d68fdf1SYifeng Zhao #ifdef CONFIG_AHCI 50*5d68fdf1SYifeng Zhao #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 51*5d68fdf1SYifeng Zhao #define CONFIG_SYS_SCSI_MAX_LUN 1 52*5d68fdf1SYifeng Zhao /*#define CONFIG_SCSI_AHCI_PLAT */ 53*5d68fdf1SYifeng Zhao #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 54*5d68fdf1SYifeng Zhao CONFIG_SYS_SCSI_MAX_LUN) 55*5d68fdf1SYifeng Zhao #endif 5669b42caeSJon Lin /* Nand */ 5769b42caeSJon Lin #define CONFIG_SYS_MAX_NAND_DEVICE 1 5869b42caeSJon Lin #define CONFIG_SYS_NAND_ONFI_DETECTION 5969b42caeSJon Lin #define CONFIG_SYS_NAND_PAGE_SIZE 2048 6069b42caeSJon Lin #define CONFIG_SYS_NAND_PAGE_COUNT 64 6169b42caeSJon Lin #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 6269b42caeSJon Lin 637e26af38SJoseph Chen #define CONFIG_SUPPORT_EMMC_RPMB 647e26af38SJoseph Chen 657e26af38SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 667e26af38SJoseph Chen #define SDRAM_MAX_SIZE 0xf0000000 677e26af38SJoseph Chen #define CONFIG_PREBOOT 687e26af38SJoseph Chen 6933a014bdSDavid Wu #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 7033a014bdSDavid Wu 717e26af38SJoseph Chen #ifndef CONFIG_SPL_BUILD 727e26af38SJoseph Chen /* usb mass storage */ 737e26af38SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 747e26af38SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350a 757e26af38SJoseph Chen 767e26af38SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 7794519358SJoseph Chen "scriptaddr=0x00c00000\0" \ 7894519358SJoseph Chen "pxefile_addr_r=0x00e00000\0" \ 795033f049SJoseph Chen "fdt_addr_r=0x0a100000\0" \ 807e26af38SJoseph Chen "kernel_addr_no_bl32_r=0x00280000\0" \ 81186b0010SJoseph Chen "kernel_addr_r=0x00a80000\0" \ 827e26af38SJoseph Chen "kernel_addr_c=0x04080000\0" \ 837e26af38SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 847e26af38SJoseph Chen 857e26af38SJoseph Chen #include <config_distro_bootcmd.h> 867e26af38SJoseph Chen 877e26af38SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 887e26af38SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 89e3a5bc90SJoseph Chen "partitions=" PARTS_RKIMG \ 907e26af38SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 917e26af38SJoseph Chen RKIMG_DET_BOOTDEV \ 927e26af38SJoseph Chen BOOTENV 935033f049SJoseph Chen 945033f049SJoseph Chen #undef RKIMG_BOOTCOMMAND 955033f049SJoseph Chen #define RKIMG_BOOTCOMMAND \ 965033f049SJoseph Chen "boot_fit;" \ 97e3a5bc90SJoseph Chen "boot_android ${devtype} ${devnum};" \ 98e3a5bc90SJoseph Chen "run distro_bootcmd;" 997e26af38SJoseph Chen #endif 1007e26af38SJoseph Chen 101858bd926SRen Jianing /* rockchip ohci host driver */ 102858bd926SRen Jianing #define CONFIG_USB_OHCI_NEW 103858bd926SRen Jianing #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 104858bd926SRen Jianing 1053ae4136eSJoseph Chen #define CONFIG_LIB_HW_RAND 1063ae4136eSJoseph Chen 1077e26af38SJoseph Chen #endif 108