17e26af38SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 27e26af38SJoseph Chen /* 37e26af38SJoseph Chen * (C) Copyright 2020 Rockchip Electronics Co., Ltd 47e26af38SJoseph Chen * 57e26af38SJoseph Chen */ 67e26af38SJoseph Chen 77e26af38SJoseph Chen #ifndef __CONFIG_RK3568_COMMON_H 87e26af38SJoseph Chen #define __CONFIG_RK3568_COMMON_H 97e26af38SJoseph Chen 1059eb0619SSugar Zhang #define CFG_CPUID_OFFSET 0xa 1159eb0619SSugar Zhang 127e26af38SJoseph Chen #include "rockchip-common.h" 137e26af38SJoseph Chen 147e26af38SJoseph Chen #define CONFIG_SPL_FRAMEWORK 157e26af38SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 16da465681SJason Zhu #define CONFIG_SPL_MAX_SIZE 0x00040000 177e26af38SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 185d96bba9SYifeng Zhao #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 197e26af38SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 2020ca5a7eSJon Lin #ifdef CONFIG_SPL_LOAD_FIT_ADDRESS 2120ca5a7eSJon Lin #undef CONFIG_SPL_LOAD_FIT_ADDRESS 2220ca5a7eSJon Lin #endif 2320ca5a7eSJon Lin #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000 247e26af38SJoseph Chen 257e26af38SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 267e26af38SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 277e26af38SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 285f73fdb1SYifeng Zhao 295f73fdb1SYifeng Zhao #ifdef CONFIG_SUPPORT_USBPLUG 305f73fdb1SYifeng Zhao #define CONFIG_SYS_TEXT_BASE 0x00000000 315f73fdb1SYifeng Zhao #else 32186b0010SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00a00000 335f73fdb1SYifeng Zhao #endif 345f73fdb1SYifeng Zhao 35186b0010SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 36186b0010SJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00c00800 377e26af38SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 387e26af38SJoseph Chen #define COUNTER_FREQUENCY 24000000 397e26af38SJoseph Chen 407e26af38SJoseph Chen #define GICD_BASE 0xfd400000 417e26af38SJoseph Chen #define GICR_BASE 0xfd460000 425033f049SJoseph Chen #define GICC_BASE 0xfd800000 437e26af38SJoseph Chen 44219085f0SJason Zhu /* secure otp */ 45219085f0SJason Zhu #define OTP_UBOOT_ROLLBACK_OFFSET 0xe0 46219085f0SJason Zhu #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 47219085f0SJason Zhu #define OTP_ALL_ONES_NUM_BITS 32 48219085f0SJason Zhu #define OTP_SECURE_BOOT_ENABLE_ADDR 0x80 49219085f0SJason Zhu #define OTP_SECURE_BOOT_ENABLE_SIZE 2 50219085f0SJason Zhu #define OTP_RSA_HASH_ADDR 0x90 51219085f0SJason Zhu #define OTP_RSA_HASH_SIZE 32 52219085f0SJason Zhu 537e26af38SJoseph Chen /* MMC/SD IP block */ 547e26af38SJoseph Chen #define CONFIG_BOUNCE_BUFFER 555d68fdf1SYifeng Zhao #ifdef CONFIG_AHCI 565d68fdf1SYifeng Zhao #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 575d68fdf1SYifeng Zhao #define CONFIG_SYS_SCSI_MAX_LUN 1 585d68fdf1SYifeng Zhao /*#define CONFIG_SCSI_AHCI_PLAT */ 595d68fdf1SYifeng Zhao #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 605d68fdf1SYifeng Zhao CONFIG_SYS_SCSI_MAX_LUN) 615d68fdf1SYifeng Zhao #endif 6269b42caeSJon Lin /* Nand */ 63*468ac886SJon Lin #define CONFIG_SYS_NAND_BASE 0xFE330000 6469b42caeSJon Lin #define CONFIG_SYS_MAX_NAND_DEVICE 1 6569b42caeSJon Lin #define CONFIG_SYS_NAND_ONFI_DETECTION 6669b42caeSJon Lin #define CONFIG_SYS_NAND_PAGE_SIZE 2048 6769b42caeSJon Lin #define CONFIG_SYS_NAND_PAGE_COUNT 64 6869b42caeSJon Lin #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 6969b42caeSJon Lin 707e26af38SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 717e26af38SJoseph Chen #define SDRAM_MAX_SIZE 0xf0000000 727e26af38SJoseph Chen #define CONFIG_PREBOOT 737e26af38SJoseph Chen 7433a014bdSDavid Wu #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 7533a014bdSDavid Wu 767e26af38SJoseph Chen #ifndef CONFIG_SPL_BUILD 777e26af38SJoseph Chen /* usb mass storage */ 787e26af38SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 797e26af38SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350a 807e26af38SJoseph Chen 817e26af38SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 8294519358SJoseph Chen "scriptaddr=0x00c00000\0" \ 8394519358SJoseph Chen "pxefile_addr_r=0x00e00000\0" \ 849a0ff0a8SJoseph Chen "fdt_addr_r=0x08300000\0" \ 85ee6a3c94SJoseph Chen "kernel_addr_r=0x00280000\0" \ 867e26af38SJoseph Chen "kernel_addr_c=0x04080000\0" \ 877e26af38SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 887e26af38SJoseph Chen 897e26af38SJoseph Chen #include <config_distro_bootcmd.h> 907e26af38SJoseph Chen 917e26af38SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 927e26af38SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 93e3a5bc90SJoseph Chen "partitions=" PARTS_RKIMG \ 947e26af38SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 957e26af38SJoseph Chen RKIMG_DET_BOOTDEV \ 967e26af38SJoseph Chen BOOTENV 977e26af38SJoseph Chen #endif 987e26af38SJoseph Chen 99858bd926SRen Jianing /* rockchip ohci host driver */ 100858bd926SRen Jianing #define CONFIG_USB_OHCI_NEW 101858bd926SRen Jianing #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 102858bd926SRen Jianing 1033ae4136eSJoseph Chen #define CONFIG_LIB_HW_RAND 1043ae4136eSJoseph Chen 1057e26af38SJoseph Chen #endif 106