156f7d184SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 256f7d184SJoseph Chen /* 356f7d184SJoseph Chen * (C) Copyright 2022 Rockchip Electronics Co., Ltd 456f7d184SJoseph Chen * 556f7d184SJoseph Chen */ 656f7d184SJoseph Chen 756f7d184SJoseph Chen #ifndef __CONFIG_RK3562_COMMON_H 856f7d184SJoseph Chen #define __CONFIG_RK3562_COMMON_H 956f7d184SJoseph Chen 1056f7d184SJoseph Chen #include "rockchip-common.h" 1156f7d184SJoseph Chen 1256f7d184SJoseph Chen #define CONFIG_SPL_FRAMEWORK 1356f7d184SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 1456f7d184SJoseph Chen #define CONFIG_SPL_MAX_SIZE 0x00040000 1556f7d184SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 1656f7d184SJoseph Chen #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 1756f7d184SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 1856f7d184SJoseph Chen 1956f7d184SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 2056f7d184SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 2156f7d184SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 2256f7d184SJoseph Chen 2356f7d184SJoseph Chen #ifdef CONFIG_SUPPORT_USBPLUG 2456f7d184SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00000000 2556f7d184SJoseph Chen #else 2656f7d184SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00200000 2756f7d184SJoseph Chen #endif 2856f7d184SJoseph Chen 2956f7d184SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 3056f7d184SJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00c00800 3156f7d184SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 3256f7d184SJoseph Chen #define COUNTER_FREQUENCY 24000000 3356f7d184SJoseph Chen 3456f7d184SJoseph Chen #define GICD_BASE 0xfe901000 3556f7d184SJoseph Chen #define GICC_BASE 0xfe902000 3656f7d184SJoseph Chen 37*08735c34SXuhui Lin /* secure otp */ 38*08735c34SXuhui Lin #define OTP_UBOOT_ROLLBACK_OFFSET 0x350 39*08735c34SXuhui Lin #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 40*08735c34SXuhui Lin #define OTP_ALL_ONES_NUM_BITS 32 41*08735c34SXuhui Lin #define OTP_SECURE_BOOT_ENABLE_ADDR 0x20 42*08735c34SXuhui Lin #define OTP_SECURE_BOOT_ENABLE_SIZE 1 43*08735c34SXuhui Lin #define OTP_RSA_HASH_ADDR 0x180 44*08735c34SXuhui Lin #define OTP_RSA_HASH_SIZE 32 45*08735c34SXuhui Lin 4656f7d184SJoseph Chen /* MMC/SD IP block */ 4756f7d184SJoseph Chen #define CONFIG_BOUNCE_BUFFER 4856f7d184SJoseph Chen 4956f7d184SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 5056f7d184SJoseph Chen #define SDRAM_MAX_SIZE 0xfc000000 5156f7d184SJoseph Chen #define CONFIG_PREBOOT 5256f7d184SJoseph Chen #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 5356f7d184SJoseph Chen 5456f7d184SJoseph Chen #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x2000000 5556f7d184SJoseph Chen 5656f7d184SJoseph Chen #ifndef CONFIG_SPL_BUILD 5756f7d184SJoseph Chen /* usb mass storage */ 5856f7d184SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 5956f7d184SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350d 6056f7d184SJoseph Chen 6156f7d184SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 6256f7d184SJoseph Chen "scriptaddr=0x00c00000\0" \ 6356f7d184SJoseph Chen "pxefile_addr_r=0x00e00000\0" \ 6456f7d184SJoseph Chen "fdt_addr_r=0x08300000\0" \ 65460307b5SJoseph Chen "kernel_addr_r=0x00400000\0" \ 6656f7d184SJoseph Chen "kernel_addr_c=0x04080000\0" \ 6756f7d184SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 6856f7d184SJoseph Chen 6956f7d184SJoseph Chen #include <config_distro_bootcmd.h> 7056f7d184SJoseph Chen 7156f7d184SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 7256f7d184SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 7356f7d184SJoseph Chen "partitions=" PARTS_RKIMG \ 7456f7d184SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 7556f7d184SJoseph Chen RKIMG_DET_BOOTDEV \ 7656f7d184SJoseph Chen BOOTENV 7756f7d184SJoseph Chen #endif 7856f7d184SJoseph Chen 7956f7d184SJoseph Chen /* rockchip ohci host driver */ 8056f7d184SJoseph Chen #define CONFIG_USB_OHCI_NEW 8156f7d184SJoseph Chen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 829dc7b00cSJoseph Chen #define CONFIG_LIB_HW_RAND 8356f7d184SJoseph Chen 8456f7d184SJoseph Chen #endif 85