1*c6f7c1a3SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2*c6f7c1a3SJoseph Chen /* 3*c6f7c1a3SJoseph Chen * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4*c6f7c1a3SJoseph Chen * 5*c6f7c1a3SJoseph Chen */ 6*c6f7c1a3SJoseph Chen 7*c6f7c1a3SJoseph Chen #ifndef __CONFIG_RK3528_COMMON_H 8*c6f7c1a3SJoseph Chen #define __CONFIG_RK3528_COMMON_H 9*c6f7c1a3SJoseph Chen 10*c6f7c1a3SJoseph Chen #include "rockchip-common.h" 11*c6f7c1a3SJoseph Chen 12*c6f7c1a3SJoseph Chen #define CONFIG_SPL_FRAMEWORK 13*c6f7c1a3SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 14*c6f7c1a3SJoseph Chen #define CONFIG_SPL_MAX_SIZE 0x00040000 15*c6f7c1a3SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16*c6f7c1a3SJoseph Chen #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 17*c6f7c1a3SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 18*c6f7c1a3SJoseph Chen 19*c6f7c1a3SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20*c6f7c1a3SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 21*c6f7c1a3SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 22*c6f7c1a3SJoseph Chen 23*c6f7c1a3SJoseph Chen #ifdef CONFIG_SUPPORT_USBPLUG 24*c6f7c1a3SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00000000 25*c6f7c1a3SJoseph Chen #else 26*c6f7c1a3SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00200000 27*c6f7c1a3SJoseph Chen #endif 28*c6f7c1a3SJoseph Chen 29*c6f7c1a3SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 30*c6f7c1a3SJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00c00800 31*c6f7c1a3SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 32*c6f7c1a3SJoseph Chen #define COUNTER_FREQUENCY 24000000 33*c6f7c1a3SJoseph Chen 34*c6f7c1a3SJoseph Chen #define GICD_BASE 0xfed01000 35*c6f7c1a3SJoseph Chen #define GICC_BASE 0xfed02000 36*c6f7c1a3SJoseph Chen 37*c6f7c1a3SJoseph Chen /* MMC/SD IP block */ 38*c6f7c1a3SJoseph Chen #define CONFIG_BOUNCE_BUFFER 39*c6f7c1a3SJoseph Chen 40*c6f7c1a3SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 41*c6f7c1a3SJoseph Chen #define SDRAM_MAX_SIZE 0xfc000000 42*c6f7c1a3SJoseph Chen #define CONFIG_PREBOOT 43*c6f7c1a3SJoseph Chen #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 44*c6f7c1a3SJoseph Chen 45*c6f7c1a3SJoseph Chen #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x2000000 46*c6f7c1a3SJoseph Chen 47*c6f7c1a3SJoseph Chen #ifndef CONFIG_SPL_BUILD 48*c6f7c1a3SJoseph Chen /* usb mass storage */ 49*c6f7c1a3SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 50*c6f7c1a3SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350d 51*c6f7c1a3SJoseph Chen 52*c6f7c1a3SJoseph Chen #ifdef CONFIG_ARM64 53*c6f7c1a3SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 54*c6f7c1a3SJoseph Chen "scriptaddr=0x00c00000\0" \ 55*c6f7c1a3SJoseph Chen "pxefile_addr_r=0x00e00000\0" \ 56*c6f7c1a3SJoseph Chen "fdt_addr_r=0x08300000\0" \ 57*c6f7c1a3SJoseph Chen "kernel_addr_r=0x00280000\0" \ 58*c6f7c1a3SJoseph Chen "kernel_addr_c=0x04080000\0" \ 59*c6f7c1a3SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 60*c6f7c1a3SJoseph Chen #else 61*c6f7c1a3SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 62*c6f7c1a3SJoseph Chen "scriptaddr=0x00000000\0" \ 63*c6f7c1a3SJoseph Chen "pxefile_addr_r=0x00100000\0" \ 64*c6f7c1a3SJoseph Chen "fdt_addr_r=0x08300000\0" \ 65*c6f7c1a3SJoseph Chen "kernel_addr_c=0x02008000\0" \ 66*c6f7c1a3SJoseph Chen "kernel_addr_r=0x00208000\0" \ 67*c6f7c1a3SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 68*c6f7c1a3SJoseph Chen #endif 69*c6f7c1a3SJoseph Chen 70*c6f7c1a3SJoseph Chen #include <config_distro_bootcmd.h> 71*c6f7c1a3SJoseph Chen 72*c6f7c1a3SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 73*c6f7c1a3SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 74*c6f7c1a3SJoseph Chen "partitions=" PARTS_RKIMG \ 75*c6f7c1a3SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 76*c6f7c1a3SJoseph Chen RKIMG_DET_BOOTDEV \ 77*c6f7c1a3SJoseph Chen BOOTENV 78*c6f7c1a3SJoseph Chen #endif 79*c6f7c1a3SJoseph Chen 80*c6f7c1a3SJoseph Chen /* rockchip ohci host driver */ 81*c6f7c1a3SJoseph Chen #define CONFIG_USB_OHCI_NEW 82*c6f7c1a3SJoseph Chen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 83*c6f7c1a3SJoseph Chen 84*c6f7c1a3SJoseph Chen #endif 85