1c6f7c1a3SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2c6f7c1a3SJoseph Chen /* 3c6f7c1a3SJoseph Chen * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4c6f7c1a3SJoseph Chen * 5c6f7c1a3SJoseph Chen */ 6c6f7c1a3SJoseph Chen 7c6f7c1a3SJoseph Chen #ifndef __CONFIG_RK3528_COMMON_H 8c6f7c1a3SJoseph Chen #define __CONFIG_RK3528_COMMON_H 9c6f7c1a3SJoseph Chen 10c6f7c1a3SJoseph Chen #include "rockchip-common.h" 11c6f7c1a3SJoseph Chen 12c6f7c1a3SJoseph Chen #define CONFIG_SPL_FRAMEWORK 13c6f7c1a3SJoseph Chen #define CONFIG_SPL_TEXT_BASE 0x00000000 14c6f7c1a3SJoseph Chen #define CONFIG_SPL_MAX_SIZE 0x00040000 15c6f7c1a3SJoseph Chen #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16c6f7c1a3SJoseph Chen #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 17c6f7c1a3SJoseph Chen #define CONFIG_SPL_STACK 0x03fe0000 18c6f7c1a3SJoseph Chen 19c6f7c1a3SJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20c6f7c1a3SJoseph Chen #define CONFIG_SYS_CBSIZE 1024 21c6f7c1a3SJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 22c6f7c1a3SJoseph Chen 23c6f7c1a3SJoseph Chen #ifdef CONFIG_SUPPORT_USBPLUG 24c6f7c1a3SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00000000 25c6f7c1a3SJoseph Chen #else 26c6f7c1a3SJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00200000 27c6f7c1a3SJoseph Chen #endif 28c6f7c1a3SJoseph Chen 29c6f7c1a3SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 30c6f7c1a3SJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00c00800 31c6f7c1a3SJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 32c6f7c1a3SJoseph Chen #define COUNTER_FREQUENCY 24000000 33c6f7c1a3SJoseph Chen 34c6f7c1a3SJoseph Chen #define GICD_BASE 0xfed01000 35c6f7c1a3SJoseph Chen #define GICC_BASE 0xfed02000 36c6f7c1a3SJoseph Chen 37c6f7c1a3SJoseph Chen /* MMC/SD IP block */ 38c6f7c1a3SJoseph Chen #define CONFIG_BOUNCE_BUFFER 39c6f7c1a3SJoseph Chen 40c6f7c1a3SJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 41c6f7c1a3SJoseph Chen #define SDRAM_MAX_SIZE 0xfc000000 42c6f7c1a3SJoseph Chen #define CONFIG_PREBOOT 43c6f7c1a3SJoseph Chen #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 44c6f7c1a3SJoseph Chen 45c6f7c1a3SJoseph Chen #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x2000000 46c6f7c1a3SJoseph Chen 47c6f7c1a3SJoseph Chen #ifndef CONFIG_SPL_BUILD 48c6f7c1a3SJoseph Chen /* usb mass storage */ 49c6f7c1a3SJoseph Chen #define CONFIG_USB_FUNCTION_MASS_STORAGE 50c6f7c1a3SJoseph Chen #define CONFIG_ROCKUSB_G_DNL_PID 0x350d 51c6f7c1a3SJoseph Chen 52c6f7c1a3SJoseph Chen #ifdef CONFIG_ARM64 53c6f7c1a3SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 54c6f7c1a3SJoseph Chen "scriptaddr=0x00c00000\0" \ 55c6f7c1a3SJoseph Chen "pxefile_addr_r=0x00e00000\0" \ 56c6f7c1a3SJoseph Chen "fdt_addr_r=0x08300000\0" \ 57c6f7c1a3SJoseph Chen "kernel_addr_r=0x00280000\0" \ 58c6f7c1a3SJoseph Chen "kernel_addr_c=0x04080000\0" \ 59c6f7c1a3SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 60c6f7c1a3SJoseph Chen #else 61c6f7c1a3SJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 62c6f7c1a3SJoseph Chen "scriptaddr=0x00000000\0" \ 63c6f7c1a3SJoseph Chen "pxefile_addr_r=0x00100000\0" \ 64c6f7c1a3SJoseph Chen "fdt_addr_r=0x08300000\0" \ 65c6f7c1a3SJoseph Chen "kernel_addr_c=0x02008000\0" \ 66c6f7c1a3SJoseph Chen "kernel_addr_r=0x00208000\0" \ 67c6f7c1a3SJoseph Chen "ramdisk_addr_r=0x0a200000\0" 68c6f7c1a3SJoseph Chen #endif 69c6f7c1a3SJoseph Chen 70c6f7c1a3SJoseph Chen #include <config_distro_bootcmd.h> 71c6f7c1a3SJoseph Chen 72c6f7c1a3SJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 73c6f7c1a3SJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 74c6f7c1a3SJoseph Chen "partitions=" PARTS_RKIMG \ 75c6f7c1a3SJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 76c6f7c1a3SJoseph Chen RKIMG_DET_BOOTDEV \ 77c6f7c1a3SJoseph Chen BOOTENV 78c6f7c1a3SJoseph Chen #endif 79c6f7c1a3SJoseph Chen 80c6f7c1a3SJoseph Chen /* rockchip ohci host driver */ 81c6f7c1a3SJoseph Chen #define CONFIG_USB_OHCI_NEW 82c6f7c1a3SJoseph Chen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 83c6f7c1a3SJoseph Chen 84*9c74bf7cSJoseph Chen #define CONFIG_LIB_HW_RAND 85*9c74bf7cSJoseph Chen 86c6f7c1a3SJoseph Chen #endif 87