1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_RK3308_COMMON_H 8 #define __CONFIG_RK3308_COMMON_H 9 10 #include "rockchip-common.h" 11 12 #define CONFIG_SYS_MALLOC_LEN (10 << 20) 13 #define CONFIG_SYS_CBSIZE 1024 14 #define CONFIG_SKIP_LOWLEVEL_INIT 15 16 #define CONFIG_SPL_FRAMEWORK 17 18 #define CONFIG_SYS_NS16550_MEM32 19 20 #define CONFIG_SYS_TEXT_BASE 0x00600000 21 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 22 #define CONFIG_SYS_LOAD_ADDR 0x00C00800 23 #define CONFIG_SPL_STACK 0x00400000 24 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 25 26 #define COUNTER_FREQUENCY 24000000 27 28 #define GICD_BASE 0xff581000 29 #define GICC_BASE 0xff582000 30 31 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 32 33 /* MMC/SD IP block */ 34 #define CONFIG_BOUNCE_BUFFER 35 36 #define CONFIG_SYS_SDRAM_BASE 0 37 #define SDRAM_MAX_SIZE 0xff000000 38 #define SDRAM_BANK_SIZE (2UL << 30) 39 #define CONFIG_PREBOOT 40 41 #ifndef CONFIG_SPL_BUILD 42 43 /* usb mass storage */ 44 #define CONFIG_USB_FUNCTION_MASS_STORAGE 45 #define CONFIG_ROCKUSB_G_DNL_PID 0x330d 46 47 #ifdef CONFIG_ARM64 48 #define ENV_MEM_LAYOUT_SETTINGS \ 49 "scriptaddr=0x00500000\0" \ 50 "pxefile_addr_r=0x00600000\0" \ 51 "fdt_addr_r=0x01f00000\0" \ 52 "kernel_addr_no_bl32_r=0x00280000\0" \ 53 "kernel_addr_r=0x00680000\0" \ 54 "kernel_addr_c=0x02480000\0" \ 55 "ramdisk_addr_r=0x04000000\0" 56 #else 57 #define ENV_MEM_LAYOUT_SETTINGS \ 58 "scriptaddr=0x00500000\0" \ 59 "pxefile_addr_r=0x00600000\0" \ 60 "fdt_addr_r=0x03200000\0" \ 61 "kernel_addr_r=0x00058000\0" \ 62 "kernel_addr_c=0x2008000\0" \ 63 "ramdisk_addr_r=0x03080000\0" 64 #endif 65 66 #include <config_distro_bootcmd.h> 67 #define CONFIG_EXTRA_ENV_SETTINGS \ 68 ENV_MEM_LAYOUT_SETTINGS \ 69 "partitions=" PARTS_DEFAULT \ 70 ROCKCHIP_DEVICE_SETTINGS \ 71 RKIMG_DET_BOOTDEV \ 72 BOOTENV_SHARED_RKNAND \ 73 BOOTENV 74 75 #endif 76 77 #endif 78