1*3d78ac3eSAndy Yan /* 2*3d78ac3eSAndy Yan * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3*3d78ac3eSAndy Yan * 4*3d78ac3eSAndy Yan * SPDX-License-Identifier: GPL-2.0+ 5*3d78ac3eSAndy Yan */ 6*3d78ac3eSAndy Yan 7*3d78ac3eSAndy Yan #ifndef __CONFIG_RK3308_COMMON_H 8*3d78ac3eSAndy Yan #define __CONFIG_RK3308_COMMON_H 9*3d78ac3eSAndy Yan 10*3d78ac3eSAndy Yan #include "rockchip-common.h" 11*3d78ac3eSAndy Yan 12*3d78ac3eSAndy Yan #define CONFIG_SYS_MALLOC_LEN (32 << 20) 13*3d78ac3eSAndy Yan #define CONFIG_SYS_CBSIZE 1024 14*3d78ac3eSAndy Yan #define CONFIG_SKIP_LOWLEVEL_INIT 15*3d78ac3eSAndy Yan 16*3d78ac3eSAndy Yan #define CONFIG_SPL_FRAMEWORK 17*3d78ac3eSAndy Yan 18*3d78ac3eSAndy Yan #define CONFIG_SYS_NS16550_MEM32 19*3d78ac3eSAndy Yan 20*3d78ac3eSAndy Yan #define CONFIG_SYS_TEXT_BASE 0x00200000 21*3d78ac3eSAndy Yan #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 22*3d78ac3eSAndy Yan #define CONFIG_SYS_LOAD_ADDR 0x00800800 23*3d78ac3eSAndy Yan #define CONFIG_SPL_STACK 0x00400000 24*3d78ac3eSAndy Yan #define CONFIG_SPL_TEXT_BASE 0x00000000 25*3d78ac3eSAndy Yan #define CONFIG_SPL_MAX_SIZE 0x10000 26*3d78ac3eSAndy Yan #define CONFIG_SPL_BSS_START_ADDR 0x2000000 27*3d78ac3eSAndy Yan #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 28*3d78ac3eSAndy Yan #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 29*3d78ac3eSAndy Yan 30*3d78ac3eSAndy Yan #define COUNTER_FREQUENCY 24000000 31*3d78ac3eSAndy Yan 32*3d78ac3eSAndy Yan #define GICD_BASE 0xff131000 33*3d78ac3eSAndy Yan #define GICC_BASE 0xff132000 34*3d78ac3eSAndy Yan 35*3d78ac3eSAndy Yan #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 36*3d78ac3eSAndy Yan 37*3d78ac3eSAndy Yan /* MMC/SD IP block */ 38*3d78ac3eSAndy Yan #define CONFIG_BOUNCE_BUFFER 39*3d78ac3eSAndy Yan 40*3d78ac3eSAndy Yan #define CONFIG_SYS_SDRAM_BASE 0 41*3d78ac3eSAndy Yan #define CONFIG_NR_DRAM_BANKS 2 42*3d78ac3eSAndy Yan #define SDRAM_MAX_SIZE 0xff000000 43*3d78ac3eSAndy Yan #define SDRAM_BANK_SIZE (2UL << 30) 44*3d78ac3eSAndy Yan #define CONFIG_PREBOOT 45*3d78ac3eSAndy Yan 46*3d78ac3eSAndy Yan #ifndef CONFIG_SPL_BUILD 47*3d78ac3eSAndy Yan 48*3d78ac3eSAndy Yan /* usb mass storage */ 49*3d78ac3eSAndy Yan #define CONFIG_USB_FUNCTION_MASS_STORAGE 50*3d78ac3eSAndy Yan #define CONFIG_ROCKUSB_G_DNL_PID 0x330d 51*3d78ac3eSAndy Yan 52*3d78ac3eSAndy Yan #define ENV_MEM_LAYOUT_SETTINGS \ 53*3d78ac3eSAndy Yan "scriptaddr=0x00500000\0" \ 54*3d78ac3eSAndy Yan "pxefile_addr_r=0x00600000\0" \ 55*3d78ac3eSAndy Yan "fdt_addr_r=0x01f00000\0" \ 56*3d78ac3eSAndy Yan "kernel_addr_r=0x02080000\0" \ 57*3d78ac3eSAndy Yan "ramdisk_addr_r=0x04000000\0" 58*3d78ac3eSAndy Yan 59*3d78ac3eSAndy Yan #include <config_distro_bootcmd.h> 60*3d78ac3eSAndy Yan #define CONFIG_EXTRA_ENV_SETTINGS \ 61*3d78ac3eSAndy Yan ENV_MEM_LAYOUT_SETTINGS \ 62*3d78ac3eSAndy Yan "partitions=" PARTS_DEFAULT \ 63*3d78ac3eSAndy Yan BOOTENV 64*3d78ac3eSAndy Yan 65*3d78ac3eSAndy Yan #endif 66*3d78ac3eSAndy Yan 67*3d78ac3eSAndy Yan #endif 68