13d78ac3eSAndy Yan /* 23d78ac3eSAndy Yan * (C) Copyright 2017 Rockchip Electronics Co., Ltd 33d78ac3eSAndy Yan * 43d78ac3eSAndy Yan * SPDX-License-Identifier: GPL-2.0+ 53d78ac3eSAndy Yan */ 63d78ac3eSAndy Yan 73d78ac3eSAndy Yan #ifndef __CONFIG_RK3308_COMMON_H 83d78ac3eSAndy Yan #define __CONFIG_RK3308_COMMON_H 93d78ac3eSAndy Yan 103d78ac3eSAndy Yan #include "rockchip-common.h" 113d78ac3eSAndy Yan 12b4bed602SAndy Yan #define CONFIG_SYS_MALLOC_LEN (10 << 20) 133d78ac3eSAndy Yan #define CONFIG_SYS_CBSIZE 1024 143d78ac3eSAndy Yan #define CONFIG_SKIP_LOWLEVEL_INIT 15fa935894SYifeng Zhao #define CONFIG_SYS_MAX_NAND_DEVICE 1 165adc7dedSYifeng Zhao #define CONFIG_SYS_NAND_ONFI_DETECTION 17fa935894SYifeng Zhao #define CONFIG_SYS_NAND_PAGE_SIZE 2048 18fa935894SYifeng Zhao #define CONFIG_SYS_NAND_PAGE_COUNT 64 1977496606SYifeng Zhao #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 203d78ac3eSAndy Yan #define CONFIG_SPL_FRAMEWORK 21951488b0SAndy Yan #define CONFIG_SPL_TEXT_BASE 0x00000000 22951488b0SAndy Yan #define CONFIG_SPL_MAX_SIZE 0x20000 23951488b0SAndy Yan #define CONFIG_SPL_BSS_START_ADDR 0x00400000 24951488b0SAndy Yan #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 253d78ac3eSAndy Yan 263d78ac3eSAndy Yan #define CONFIG_SYS_NS16550_MEM32 273d78ac3eSAndy Yan 28c791e8a8SAndy Yan #define CONFIG_SYS_TEXT_BASE 0x00600000 29a25a7031SJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 30c791e8a8SAndy Yan #define CONFIG_SYS_LOAD_ADDR 0x00C00800 313d78ac3eSAndy Yan #define CONFIG_SPL_STACK 0x00400000 323d78ac3eSAndy Yan #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 333d78ac3eSAndy Yan 343d78ac3eSAndy Yan #define COUNTER_FREQUENCY 24000000 353d78ac3eSAndy Yan 360b4bf976SJoseph Chen #define GICD_BASE 0xff581000 370b4bf976SJoseph Chen #define GICC_BASE 0xff582000 383d78ac3eSAndy Yan 393d78ac3eSAndy Yan #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 403d78ac3eSAndy Yan 413d78ac3eSAndy Yan /* MMC/SD IP block */ 423d78ac3eSAndy Yan #define CONFIG_BOUNCE_BUFFER 433d78ac3eSAndy Yan 443d78ac3eSAndy Yan #define CONFIG_SYS_SDRAM_BASE 0 453d78ac3eSAndy Yan #define SDRAM_MAX_SIZE 0xff000000 463d78ac3eSAndy Yan #define SDRAM_BANK_SIZE (2UL << 30) 4760137d81SJoseph Chen #ifdef CONFIG_DM_DVFS 4860137d81SJoseph Chen #define CONFIG_PREBOOT "dvfs repeat" 4960137d81SJoseph Chen #else 503d78ac3eSAndy Yan #define CONFIG_PREBOOT 5160137d81SJoseph Chen #endif 523d78ac3eSAndy Yan 533d78ac3eSAndy Yan #ifndef CONFIG_SPL_BUILD 543d78ac3eSAndy Yan 553d78ac3eSAndy Yan /* usb mass storage */ 563d78ac3eSAndy Yan #define CONFIG_USB_FUNCTION_MASS_STORAGE 573d78ac3eSAndy Yan #define CONFIG_ROCKUSB_G_DNL_PID 0x330d 583d78ac3eSAndy Yan 59b4bed602SAndy Yan #ifdef CONFIG_ARM64 603d78ac3eSAndy Yan #define ENV_MEM_LAYOUT_SETTINGS \ 613d78ac3eSAndy Yan "scriptaddr=0x00500000\0" \ 623d78ac3eSAndy Yan "pxefile_addr_r=0x00600000\0" \ 633d78ac3eSAndy Yan "fdt_addr_r=0x01f00000\0" \ 64f90a7d86SJoseph Chen "kernel_addr_no_bl32_r=0x00280000\0" \ 65203b897eSAndy Yan "kernel_addr_r=0x00680000\0" \ 66203b897eSAndy Yan "kernel_addr_c=0x02480000\0" \ 673d78ac3eSAndy Yan "ramdisk_addr_r=0x04000000\0" 68b4bed602SAndy Yan #else 69b4bed602SAndy Yan #define ENV_MEM_LAYOUT_SETTINGS \ 70b4bed602SAndy Yan "scriptaddr=0x00500000\0" \ 71b4bed602SAndy Yan "pxefile_addr_r=0x00600000\0" \ 72f9ca6757SJoseph Chen "fdt_addr_r=0x02f00000\0" \ 730958c00cSAndy Yan "kernel_addr_r=0x00058000\0" \ 740958c00cSAndy Yan "kernel_addr_c=0x2008000\0" \ 75*0b84b74aSJoseph Chen "ramdisk_addr_r=0x02880000\0" 76b4bed602SAndy Yan #endif 773d78ac3eSAndy Yan 783d78ac3eSAndy Yan #include <config_distro_bootcmd.h> 793d78ac3eSAndy Yan #define CONFIG_EXTRA_ENV_SETTINGS \ 803d78ac3eSAndy Yan ENV_MEM_LAYOUT_SETTINGS \ 813d78ac3eSAndy Yan "partitions=" PARTS_DEFAULT \ 825c651246SSandy Huang ROCKCHIP_DEVICE_SETTINGS \ 8331c3ca32SKever Yang RKIMG_DET_BOOTDEV \ 84eb01a124SCody Xie BOOTENV_SHARED_RKNAND \ 853d78ac3eSAndy Yan BOOTENV 863d78ac3eSAndy Yan 873d78ac3eSAndy Yan #endif 883d78ac3eSAndy Yan 893d78ac3eSAndy Yan #endif 90