1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_RK3288_COMMON_H 8 #define __CONFIG_RK3288_COMMON_H 9 10 #define CONFIG_SYS_CACHELINE_SIZE 64 11 12 #include <asm/arch/hardware.h> 13 14 #define CONFIG_SYS_NO_FLASH 15 #define CONFIG_NR_DRAM_BANKS 1 16 #define CONFIG_ENV_SIZE 0x2000 17 #define CONFIG_SYS_MAXARGS 16 18 #define CONFIG_BAUDRATE 115200 19 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20 #define CONFIG_SYS_CBSIZE 1024 21 #define CONFIG_SYS_THUMB_BUILD 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) 25 #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ 26 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) 27 28 #define CONFIG_SPL_FRAMEWORK 29 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 30 #define CONFIG_SPL_LIBCOMMON_SUPPORT 31 #define CONFIG_SPL_LIBGENERIC_SUPPORT 32 #define CONFIG_SPL_SERIAL_SUPPORT 33 #define CONFIG_SYS_NS16550_MEM32 34 #define CONFIG_SPL_BOARD_INIT 35 36 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 37 /* Bootrom will load u-boot binary to 0x0 once return from SPL */ 38 #define CONFIG_SYS_TEXT_BASE 0x00000000 39 #else 40 #define CONFIG_SYS_TEXT_BASE 0x00100000 41 #endif 42 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 43 #define CONFIG_SYS_LOAD_ADDR 0x00800800 44 #define CONFIG_SPL_STACK 0xff718000 45 #define CONFIG_SPL_TEXT_BASE 0xff704004 46 47 #define CONFIG_SILENT_CONSOLE 48 #ifndef CONFIG_SPL_BUILD 49 # define CONFIG_SYS_CONSOLE_IS_IN_ENV 50 # define CONFIG_CONSOLE_MUX 51 #endif 52 53 /* MMC/SD IP block */ 54 #define CONFIG_MMC 55 #define CONFIG_GENERIC_MMC 56 #define CONFIG_DWMMC 57 #define CONFIG_BOUNCE_BUFFER 58 59 #define CONFIG_DOS_PARTITION 60 #define CONFIG_FAT_WRITE 61 #define CONFIG_PARTITION_UUIDS 62 #define CONFIG_CMD_PART 63 64 /* RAW SD card / eMMC locations. */ 65 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 66 #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) 67 68 /* FAT sd card locations. */ 69 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 70 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 71 72 #define CONFIG_SPL_PINCTRL_SUPPORT 73 #define CONFIG_SPL_RAM_SUPPORT 74 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 75 76 #define CONFIG_SYS_SDRAM_BASE 0 77 #define CONFIG_NR_DRAM_BANKS 1 78 #define SDRAM_BANK_SIZE (2UL << 30) 79 80 #define CONFIG_SPI_FLASH 81 #define CONFIG_SPI 82 #define CONFIG_SF_DEFAULT_SPEED 20000000 83 84 /* usb otg */ 85 #define CONFIG_USB_GADGET 86 #define CONFIG_USB_GADGET_DUALSPEED 87 #define CONFIG_USB_GADGET_DWC2_OTG 88 #define CONFIG_ROCKCHIP_USB2_PHY 89 #define CONFIG_USB_GADGET_VBUS_DRAW 0 90 91 /* fastboot */ 92 #define CONFIG_CMD_FASTBOOT 93 #define CONFIG_USB_FUNCTION_FASTBOOT 94 #define CONFIG_FASTBOOT_FLASH 95 #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ 96 /* stroe safely fastboot buffer data to the middle of bank */ 97 #define CONFIG_FASTBOOT_BUF_ADDR (CONFIG_SYS_SDRAM_BASE \ 98 + SDRAM_BANK_SIZE / 2) 99 #define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 100 101 #define CONFIG_USB_GADGET_DOWNLOAD 102 #define CONFIG_G_DNL_MANUFACTURER "Rockchip" 103 #define CONFIG_G_DNL_VENDOR_NUM 0x2207 104 #define CONFIG_G_DNL_PRODUCT_NUM 0x320a 105 106 /* Enable gpt partition table */ 107 #define CONFIG_CMD_GPT 108 #define CONFIG_EFI_PARTITION 109 110 #ifndef CONFIG_SPL_BUILD 111 #include <config_distro_defaults.h> 112 113 #define ENV_MEM_LAYOUT_SETTINGS \ 114 "scriptaddr=0x00000000\0" \ 115 "pxefile_addr_r=0x00100000\0" \ 116 "fdt_addr_r=0x01f00000\0" \ 117 "kernel_addr_r=0x02000000\0" \ 118 "ramdisk_addr_r=0x04000000\0" 119 120 /* First try to boot from SD (index 0), then eMMC (index 1 */ 121 #define BOOT_TARGET_DEVICES(func) \ 122 func(MMC, mmc, 0) \ 123 func(MMC, mmc, 1) 124 125 #include <config_distro_bootcmd.h> 126 127 /* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so 128 * limit the fdt reallocation to that */ 129 #define CONFIG_EXTRA_ENV_SETTINGS \ 130 "fdt_high=0x1fffffff\0" \ 131 "initrd_high=0x1fffffff\0" \ 132 ENV_MEM_LAYOUT_SETTINGS \ 133 ROCKCHIP_DEVICE_SETTINGS \ 134 BOOTENV 135 #endif 136 137 #endif 138