1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_PX30_COMMON_H 8 #define __CONFIG_PX30_COMMON_H 9 10 #include "rockchip-common.h" 11 12 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 13 #define CONFIG_SYS_CBSIZE 1024 14 #define CONFIG_SKIP_LOWLEVEL_INIT 15 16 #define CONFIG_SPL_FRAMEWORK 17 18 #define CONFIG_SYS_NS16550_MEM32 19 20 #define CONFIG_SYS_TEXT_BASE 0x00200000 21 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 22 #define CONFIG_SYS_LOAD_ADDR 0x00800800 23 #define CONFIG_SPL_STACK 0x00400000 24 #define CONFIG_SPL_TEXT_BASE 0x00000000 25 #define CONFIG_SPL_MAX_SIZE 0x10000 26 #define CONFIG_SPL_BSS_START_ADDR 0x2000000 27 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 28 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 29 30 #define COUNTER_FREQUENCY 24000000 31 32 #define GICD_BASE 0xFF811000 33 #define GICC_BASE 0xFF812000 34 35 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 36 37 /* MMC/SD IP block */ 38 #define CONFIG_BOUNCE_BUFFER 39 40 #define CONFIG_SYS_SDRAM_BASE 0 41 #define CONFIG_NR_DRAM_BANKS 1 42 #define SDRAM_MAX_SIZE 0xff000000 43 #define SDRAM_BANK_SIZE (2UL << 30) 44 45 46 #ifndef CONFIG_SPL_BUILD 47 48 #define ENV_MEM_LAYOUT_SETTINGS \ 49 "scriptaddr=0x00500000\0" \ 50 "pxefile_addr_r=0x00600000\0" \ 51 "fdt_addr_r=0x01f00000\0" \ 52 "kernel_addr_r=0x02080000\0" \ 53 "ramdisk_addr_r=0x04000000\0" 54 55 #include <config_distro_bootcmd.h> 56 #define CONFIG_EXTRA_ENV_SETTINGS \ 57 ENV_MEM_LAYOUT_SETTINGS \ 58 "partitions=" PARTS_DEFAULT \ 59 BOOTENV 60 61 #endif 62 63 #endif 64