1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <linux/list.h> 17 #include <linux/media-bus-format.h> 18 #include <clk.h> 19 #include <asm/arch/clock.h> 20 #include <linux/err.h> 21 #include <linux/ioport.h> 22 #include <dm/device.h> 23 #include <dm/read.h> 24 #include <fixp-arith.h> 25 #include <syscon.h> 26 27 #include "rockchip_display.h" 28 #include "rockchip_crtc.h" 29 #include "rockchip_connector.h" 30 31 /* System registers definition */ 32 #define RK3568_REG_CFG_DONE 0x000 33 #define CFG_DONE_EN BIT(15) 34 35 #define RK3568_VERSION_INFO 0x004 36 #define EN_MASK 1 37 38 #define RK3568_AUTO_GATING_CTRL 0x008 39 40 #define RK3568_SYS_AXI_LUT_CTRL 0x024 41 #define LUT_DMA_EN_SHIFT 0 42 43 #define RK3568_DSP_IF_EN 0x028 44 #define RGB_EN_SHIFT 0 45 #define HDMI0_EN_SHIFT 1 46 #define EDP0_EN_SHIFT 3 47 #define MIPI0_EN_SHIFT 4 48 #define MIPI1_EN_SHIFT 20 49 #define LVDS0_EN_SHIFT 5 50 #define LVDS1_EN_SHIFT 24 51 #define BT1120_EN_SHIFT 6 52 #define BT656_EN_SHIFT 7 53 #define IF_MUX_MASK 3 54 #define RGB_MUX_SHIFT 8 55 #define HDMI0_MUX_SHIFT 10 56 #define EDP0_MUX_SHIFT 14 57 #define MIPI0_MUX_SHIFT 16 58 #define MIPI1_MUX_SHIFT 21 59 #define LVDS0_MUX_SHIFT 18 60 #define LVDS1_MUX_SHIFT 25 61 62 #define RK3568_DSP_IF_CTRL 0x02c 63 #define LVDS_DUAL_EN_SHIFT 0 64 #define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1 65 #define LVDS_DUAL_SWAP_EN_SHIFT 2 66 #define RK3568_DSP_IF_POL 0x030 67 #define IF_CTRL_REG_DONE_IMD_MASK 1 68 #define IF_CTRL_REG_DONE_IMD_SHIFT 28 69 #define IF_CRTL_MIPI_DCLK_POL_SHIT 19 70 #define IF_CRTL_EDP_DCLK_POL_SHIT 15 71 #define IF_CRTL_HDMI_DCLK_POL_SHIT 7 72 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7 73 #define IF_CRTL_HDMI_PIN_POL_SHIT 4 74 #define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3 75 #define RK3568_SYS_OTP_WIN_EN 0x50 76 #define OTP_WIN_EN_SHIFT 0 77 #define RK3568_SYS_LUT_PORT_SEL 0x58 78 #define GAMMA_PORT_SEL_MASK 0x3 79 #define GAMMA_PORT_SEL_SHIFT 0 80 81 #define RK3568_VP0_LINE_FLAG 0x70 82 #define RK3568_VP1_LINE_FLAG 0x74 83 #define RK3568_VP2_LINE_FLAG 0x78 84 #define RK3568_SYS0_INT_EN 0x80 85 #define RK3568_SYS0_INT_CLR 0x84 86 #define RK3568_SYS0_INT_STATUS 0x88 87 #define RK3568_SYS1_INT_EN 0x90 88 #define RK3568_SYS1_INT_CLR 0x94 89 #define RK3568_SYS1_INT_STATUS 0x98 90 #define RK3568_VP0_INT_EN 0xA0 91 #define RK3568_VP0_INT_CLR 0xA4 92 #define RK3568_VP0_INT_STATUS 0xA8 93 #define RK3568_VP1_INT_EN 0xB0 94 #define RK3568_VP1_INT_CLR 0xB4 95 #define RK3568_VP1_INT_STATUS 0xB8 96 #define RK3568_VP2_INT_EN 0xC0 97 #define RK3568_VP2_INT_CLR 0xC4 98 #define RK3568_VP2_INT_STATUS 0xC8 99 100 /* Overlay registers definition */ 101 #define RK3568_OVL_CTRL 0x600 102 #define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28 103 #define RK3568_OVL_LAYER_SEL 0x604 104 #define LAYER_SEL_MASK 0xf 105 106 #define RK3568_OVL_PORT_SEL 0x608 107 #define PORT_MUX_MASK 0xf 108 #define PORT_MUX_SHIFT 0 109 #define LAYER_SEL_PORT_MASK 0x3 110 #define LAYER_SEL_PORT_SHIFT 16 111 112 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 113 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 114 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 115 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 116 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 117 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 118 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 119 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 120 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 121 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 122 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 123 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 124 #define RK3568_VP0_BG_MIX_CTRL 0x6E0 125 #define BG_MIX_CTRL_MASK 0xff 126 #define BG_MIX_CTRL_SHIFT 24 127 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 128 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 129 #define RK3568_CLUSTER_DLY_NUM 0x6F0 130 #define RK3568_SMART_DLY_NUM 0x6F8 131 132 /* Video Port registers definition */ 133 #define RK3568_VP0_DSP_CTRL 0xC00 134 #define OUT_MODE_MASK 0xf 135 #define OUT_MODE_SHIFT 0 136 #define DATA_SWAP_MASK 0x1f 137 #define DATA_SWAP_SHIFT 8 138 #define DSP_RB_SWAP 2 139 #define CORE_DCLK_DIV_EN_SHIFT 4 140 #define P2I_EN_SHIFT 5 141 #define DSP_FILED_POL 6 142 #define INTERLACE_EN_SHIFT 7 143 #define POST_DSP_OUT_R2Y_SHIFT 15 144 #define PRE_DITHER_DOWN_EN_SHIFT 16 145 #define DITHER_DOWN_EN_SHIFT 17 146 #define DSP_LUT_EN_SHIFT 28 147 148 #define STANDBY_EN_SHIFT 31 149 150 #define RK3568_VP0_MIPI_CTRL 0xC04 151 #define DCLK_DIV2_SHIFT 4 152 #define DCLK_DIV2_MASK 0x3 153 #define MIPI_DUAL_EN_SHIFT 20 154 #define MIPI_DUAL_SWAP_EN_SHIFT 21 155 156 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 157 #define RK3568_VP0_3D_LUT_CTRL 0xC10 158 #define VP0_3D_LUT_EN_SHIFT 0 159 #define VP0_3D_LUT_UPDATE_SHIFT 2 160 161 #define RK3568_VP0_3D_LUT_MST 0xC20 162 163 #define RK3568_VP0_DSP_BG 0xC2C 164 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 165 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 166 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 167 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C 168 #define RK3568_VP0_POST_SCL_CTRL 0xC40 169 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 170 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 171 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C 172 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 173 #define RK3568_VP0_DSP_VACT_ST_END 0xC54 174 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 175 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C 176 177 #define RK3568_VP0_BCSH_CTRL 0xC60 178 #define BCSH_CTRL_Y2R_SHIFT 0 179 #define BCSH_CTRL_Y2R_MASK 0x1 180 #define BCSH_CTRL_Y2R_CSC_MODE_SHIFT 2 181 #define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3 182 #define BCSH_CTRL_R2Y_SHIFT 4 183 #define BCSH_CTRL_R2Y_MASK 0x1 184 #define BCSH_CTRL_R2Y_CSC_MODE_SHIFT 6 185 #define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3 186 187 #define RK3568_VP0_BCSH_BCS 0xC64 188 #define BCSH_BRIGHTNESS_SHIFT 0 189 #define BCSH_BRIGHTNESS_MASK 0xFF 190 #define BCSH_CONTRAST_SHIFT 8 191 #define BCSH_CONTRAST_MASK 0x1FF 192 #define BCSH_SATURATION_SHIFT 20 193 #define BCSH_SATURATION_MASK 0x3FF 194 #define BCSH_OUT_MODE_SHIFT 30 195 #define BCSH_OUT_MODE_MASK 0x3 196 197 #define RK3568_VP0_BCSH_H 0xC68 198 #define BCSH_SIN_HUE_SHIFT 0 199 #define BCSH_SIN_HUE_MASK 0x1FF 200 #define BCSH_COS_HUE_SHIFT 16 201 #define BCSH_COS_HUE_MASK 0x1FF 202 203 #define RK3568_VP0_BCSH_COLOR 0xC6C 204 #define BCSH_EN_SHIFT 31 205 #define BCSH_EN_MASK 1 206 207 #define RK3568_VP1_DSP_CTRL 0xD00 208 #define RK3568_VP1_MIPI_CTRL 0xD04 209 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 210 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 211 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 212 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 213 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C 214 #define RK3568_VP1_POST_SCL_CTRL 0xD40 215 #define RK3568_VP1_DSP_HACT_INFO 0xD34 216 #define RK3568_VP1_DSP_VACT_INFO 0xD38 217 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 218 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 219 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C 220 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 221 #define RK3568_VP1_DSP_VACT_ST_END 0xD54 222 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 223 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C 224 225 #define RK3568_VP2_DSP_CTRL 0xE00 226 #define RK3568_VP2_MIPI_CTRL 0xE04 227 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 228 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 229 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 230 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 231 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C 232 #define RK3568_VP2_POST_SCL_CTRL 0xE40 233 #define RK3568_VP2_DSP_HACT_INFO 0xE34 234 #define RK3568_VP2_DSP_VACT_INFO 0xE38 235 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 236 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 237 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C 238 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 239 #define RK3568_VP2_DSP_VACT_ST_END 0xE54 240 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 241 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C 242 243 /* Cluster0 register definition */ 244 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 245 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 246 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 247 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 248 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 249 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 250 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 251 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 252 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 253 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 254 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 255 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C 256 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 257 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 258 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 259 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C 260 261 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 262 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 263 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 264 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 265 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 266 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 267 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 268 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 269 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 270 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 271 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 272 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC 273 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 274 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 275 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 276 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC 277 278 #define RK3568_CLUSTER0_CTRL 0x1100 279 280 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 281 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 282 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 283 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 284 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 285 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 286 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 287 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 288 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 289 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 290 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 291 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C 292 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 293 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 294 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 295 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C 296 297 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 298 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 299 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 300 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 301 #define RK3568_CLUSTER1_WIN1_VIR 0x1298 302 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 303 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 304 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 305 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 306 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 307 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 308 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC 309 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 310 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 311 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 312 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC 313 314 #define RK3568_CLUSTER1_CTRL 0x1300 315 316 /* Esmart register definition */ 317 #define RK3568_ESMART0_CTRL0 0x1800 318 #define RGB2YUV_EN_SHIFT 1 319 #define CSC_MODE_SHIFT 2 320 #define CSC_MODE_MASK 0x3 321 322 #define RK3568_ESMART0_CTRL1 0x1804 323 #define YMIRROR_EN_SHIFT 31 324 #define RK3568_ESMART0_REGION0_CTRL 0x1810 325 #define REGION0_RB_SWAP_SHIFT 14 326 #define WIN_EN_SHIFT 0 327 #define WIN_FORMAT_MASK 0x1f 328 #define WIN_FORMAT_SHIFT 1 329 330 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 331 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 332 #define RK3568_ESMART0_REGION0_VIR 0x181C 333 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 334 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 335 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828 336 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 337 #define YRGB_XSCL_MODE_MASK 0x3 338 #define YRGB_XSCL_MODE_SHIFT 0 339 #define YRGB_XSCL_FILTER_MODE_MASK 0x3 340 #define YRGB_XSCL_FILTER_MODE_SHIFT 2 341 #define YRGB_YSCL_MODE_MASK 0x3 342 #define YRGB_YSCL_MODE_SHIFT 4 343 #define YRGB_YSCL_FILTER_MODE_MASK 0x3 344 #define YRGB_YSCL_FILTER_MODE_SHIFT 6 345 346 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 347 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 348 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C 349 #define RK3568_ESMART0_REGION1_CTRL 0x1840 350 #define YRGB_GT2_MASK 0x1 351 #define YRGB_GT2_SHIFT 8 352 #define YRGB_GT4_MASK 0x1 353 #define YRGB_GT4_SHIFT 9 354 355 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 356 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848 357 #define RK3568_ESMART0_REGION1_VIR 0x184C 358 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 359 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 360 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858 361 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 362 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 363 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 364 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C 365 #define RK3568_ESMART0_REGION2_CTRL 0x1870 366 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 367 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878 368 #define RK3568_ESMART0_REGION2_VIR 0x187C 369 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 370 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 371 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888 372 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 373 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 374 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 375 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C 376 #define RK3568_ESMART0_REGION3_CTRL 0x18A0 377 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 378 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 379 #define RK3568_ESMART0_REGION3_VIR 0x18AC 380 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 381 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 382 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 383 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 384 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 385 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 386 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC 387 388 #define RK3568_ESMART1_CTRL0 0x1A00 389 #define RK3568_ESMART1_CTRL1 0x1A04 390 #define RK3568_ESMART1_REGION0_CTRL 0x1A10 391 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 392 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 393 #define RK3568_ESMART1_REGION0_VIR 0x1A1C 394 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 395 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 396 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 397 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 398 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 399 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 400 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C 401 #define RK3568_ESMART1_REGION1_CTRL 0x1A40 402 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 403 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 404 #define RK3568_ESMART1_REGION1_VIR 0x1A4C 405 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 406 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 407 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 408 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 409 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 410 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 411 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C 412 #define RK3568_ESMART1_REGION2_CTRL 0x1A70 413 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 414 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 415 #define RK3568_ESMART1_REGION2_VIR 0x1A7C 416 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 417 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 418 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 419 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 420 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 421 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 422 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C 423 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0 424 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 425 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 426 #define RK3568_ESMART1_REGION3_VIR 0x1AAC 427 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 428 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 429 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 430 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 431 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 432 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 433 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC 434 435 #define RK3568_SMART0_CTRL0 0x1C00 436 #define RK3568_SMART0_CTRL1 0x1C04 437 #define RK3568_SMART0_REGION0_CTRL 0x1C10 438 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 439 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18 440 #define RK3568_SMART0_REGION0_VIR 0x1C1C 441 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 442 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 443 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28 444 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 445 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 446 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 447 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C 448 #define RK3568_SMART0_REGION1_CTRL 0x1C40 449 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 450 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48 451 #define RK3568_SMART0_REGION1_VIR 0x1C4C 452 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 453 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 454 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58 455 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 456 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 457 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 458 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C 459 #define RK3568_SMART0_REGION2_CTRL 0x1C70 460 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 461 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78 462 #define RK3568_SMART0_REGION2_VIR 0x1C7C 463 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 464 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 465 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88 466 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 467 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 468 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 469 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C 470 #define RK3568_SMART0_REGION3_CTRL 0x1CA0 471 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 472 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 473 #define RK3568_SMART0_REGION3_VIR 0x1CAC 474 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 475 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 476 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 477 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 478 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 479 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 480 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC 481 482 #define RK3568_SMART1_CTRL0 0x1E00 483 #define RK3568_SMART1_CTRL1 0x1E04 484 #define RK3568_SMART1_REGION0_CTRL 0x1E10 485 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 486 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18 487 #define RK3568_SMART1_REGION0_VIR 0x1E1C 488 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 489 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 490 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28 491 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 492 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 493 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 494 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C 495 #define RK3568_SMART1_REGION1_CTRL 0x1E40 496 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 497 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48 498 #define RK3568_SMART1_REGION1_VIR 0x1E4C 499 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 500 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 501 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58 502 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 503 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 504 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 505 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C 506 #define RK3568_SMART1_REGION2_CTRL 0x1E70 507 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 508 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78 509 #define RK3568_SMART1_REGION2_VIR 0x1E7C 510 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 511 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 512 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88 513 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 514 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 515 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 516 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C 517 #define RK3568_SMART1_REGION3_CTRL 0x1EA0 518 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 519 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 520 #define RK3568_SMART1_REGION3_VIR 0x1EAC 521 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 522 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 523 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 524 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 525 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 526 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 527 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC 528 529 #define RK3568_MAX_REG 0x1ED0 530 531 #define RK3568_GRF_VO_CON1 0x0364 532 #define GRF_BT656_CLK_INV_SHIFT 1 533 #define GRF_BT1120_CLK_INV_SHIFT 2 534 #define GRF_RGB_DCLK_INV_SHIFT 3 535 536 #define VOP2_LAYER_MAX 8 537 538 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 539 540 enum vop2_csc_format { 541 CSC_BT601L, 542 CSC_BT709L, 543 CSC_BT601F, 544 CSC_BT2020, 545 }; 546 547 enum vop2_pol { 548 HSYNC_POSITIVE = 0, 549 VSYNC_POSITIVE = 1, 550 DEN_NEGATIVE = 2, 551 DCLK_INVERT = 3 552 }; 553 554 enum vop2_bcsh_out_mode { 555 BCSH_OUT_MODE_BLACK, 556 BCSH_OUT_MODE_BLUE, 557 BCSH_OUT_MODE_COLOR_BAR, 558 BCSH_OUT_MODE_NORMAL_VIDEO, 559 }; 560 561 #define _VOP_REG(off, _mask, _shift, _write_mask) \ 562 { \ 563 .offset = off, \ 564 .mask = _mask, \ 565 .shift = _shift, \ 566 .write_mask = _write_mask, \ 567 } 568 569 #define VOP_REG(off, _mask, _shift) \ 570 _VOP_REG(off, _mask, _shift, false) 571 enum dither_down_mode { 572 RGB888_TO_RGB565 = 0x0, 573 RGB888_TO_RGB666 = 0x1 574 }; 575 576 enum vop2_video_ports_id { 577 VOP2_VP0, 578 VOP2_VP1, 579 VOP2_VP2, 580 VOP2_VP3, 581 VOP2_VP_MAX, 582 }; 583 584 enum vop2_layer_type { 585 CLUSTER_LAYER = 0, 586 ESMART_LAYER = 1, 587 SMART_LAYER = 2, 588 }; 589 590 /* This define must same with kernel win phy id */ 591 enum vop2_layer_phy_id { 592 ROCKCHIP_VOP2_CLUSTER0 = 0, 593 ROCKCHIP_VOP2_CLUSTER1, 594 ROCKCHIP_VOP2_ESMART0, 595 ROCKCHIP_VOP2_ESMART1, 596 ROCKCHIP_VOP2_SMART0, 597 ROCKCHIP_VOP2_SMART1, 598 ROCKCHIP_VOP2_CLUSTER2, 599 ROCKCHIP_VOP2_CLUSTER3, 600 ROCKCHIP_VOP2_ESMART2, 601 ROCKCHIP_VOP2_ESMART3, 602 ROCKCHIP_VOP2_LAYER_MAX, 603 }; 604 605 enum vop2_scale_up_mode { 606 VOP2_SCALE_UP_NRST_NBOR, 607 VOP2_SCALE_UP_BIL, 608 VOP2_SCALE_UP_BIC, 609 }; 610 611 enum vop2_scale_down_mode { 612 VOP2_SCALE_DOWN_NRST_NBOR, 613 VOP2_SCALE_DOWN_BIL, 614 VOP2_SCALE_DOWN_AVG, 615 }; 616 617 enum scale_mode { 618 SCALE_NONE = 0x0, 619 SCALE_UP = 0x1, 620 SCALE_DOWN = 0x2 621 }; 622 623 struct vop2_layer { 624 u8 id; 625 /** 626 * @win_phys_id: window id of the layer selected. 627 * Every layer must make sure to select different 628 * windows of others. 629 */ 630 u8 win_phys_id; 631 }; 632 633 struct vop2_win_data { 634 char *name; 635 u8 phys_id; 636 u8 win_sel_port_offset; 637 u8 layer_sel_win_id; 638 u32 reg_offset; 639 }; 640 641 struct vop2_vp_data { 642 u32 feature; 643 u8 pre_scan_max_dly; 644 struct vop_rect max_output; 645 }; 646 647 struct vop2_plane_table { 648 enum vop2_layer_phy_id plane_id; 649 enum vop2_layer_type plane_type; 650 }; 651 652 struct vop2_vp_plane_mask { 653 u8 primary_plane_id; /* use this win to show logo */ 654 u8 attached_layers_nr; /* number layers attach to this vp */ 655 u8 attached_layers[VOP2_LAYER_MAX]; /* the layers attached to this vp */ 656 u32 plane_mask; 657 int cursor_plane_id; 658 }; 659 660 struct vop2_data { 661 u32 version; 662 struct vop2_vp_data *vp_data; 663 struct vop2_win_data *win_data; 664 struct vop2_vp_plane_mask *plane_mask; 665 struct vop2_plane_table *plane_table; 666 u8 nr_vps; 667 u8 nr_layers; 668 u8 nr_mixers; 669 u8 nr_gammas; 670 }; 671 672 struct vop2 { 673 u32 *regsbak; 674 void *regs; 675 void *grf; 676 u32 reg_len; 677 u32 version; 678 bool global_init; 679 const struct vop2_data *data; 680 struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX]; 681 }; 682 683 static struct vop2 *rockchip_vop2; 684 /* 685 * bli_sd_factor = (src - 1) / (dst - 1) << 12; 686 * avg_sd_factor: 687 * bli_su_factor: 688 * bic_su_factor: 689 * = (src - 1) / (dst - 1) << 16; 690 * 691 * gt2 enable: dst get one line from two line of the src 692 * gt4 enable: dst get one line from four line of the src. 693 * 694 */ 695 #define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1)) 696 #define VOP2_COMMON_SCL(src, dst) (((src - 1) << 16) / (dst - 1)) 697 698 #define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \ 699 (fac * (dst - 1) >> 12 < (src - 1)) 700 #define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \ 701 (fac * (dst - 1) >> 16 < (src - 1)) 702 703 static uint16_t vop2_scale_factor(enum scale_mode mode, 704 int32_t filter_mode, 705 uint32_t src, uint32_t dst) 706 { 707 uint32_t fac = 0; 708 int i = 0; 709 710 if (mode == SCALE_NONE) 711 return 0; 712 713 /* 714 * A workaround to avoid zero div. 715 */ 716 if ((dst == 1) || (src == 1)) { 717 dst = dst + 1; 718 src = src + 1; 719 } 720 721 if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) { 722 fac = VOP2_BILI_SCL_DN(src, dst); 723 for (i = 0; i < 100; i++) { 724 if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac)) 725 break; 726 fac -= 1; 727 printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 728 } 729 } else { 730 fac = VOP2_COMMON_SCL(src, dst); 731 for (i = 0; i < 100; i++) { 732 if (VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac)) 733 break; 734 fac -= 1; 735 printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 736 } 737 } 738 739 return fac; 740 } 741 742 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 743 { 744 if (src < dst) 745 return SCALE_UP; 746 else if (src > dst) 747 return SCALE_DOWN; 748 749 return SCALE_NONE; 750 } 751 752 static u8 vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 753 ROCKCHIP_VOP2_SMART0, 754 ROCKCHIP_VOP2_SMART1, 755 ROCKCHIP_VOP2_ESMART1, 756 }; 757 758 static inline int interpolate(int x1, int y1, int x2, int y2, int x) 759 { 760 return y1 + (y2 - y1) * (x - x1) / (x2 - x1); 761 } 762 763 static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask) 764 { 765 int i = 0; 766 767 for (i = 0; i < vop2->data->nr_vps; i++) { 768 if (plane_mask & BIT(vop2_vp_primary_plane_order[i])) 769 return vop2_vp_primary_plane_order[i]; 770 } 771 772 return ROCKCHIP_VOP2_SMART0; 773 } 774 775 static inline u16 scl_cal_scale(int src, int dst, int shift) 776 { 777 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 778 } 779 780 static inline u16 scl_cal_scale2(int src, int dst) 781 { 782 return ((src - 1) << 12) / (dst - 1); 783 } 784 785 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 786 { 787 writel(v, vop2->regs + offset); 788 vop2->regsbak[offset >> 2] = v; 789 } 790 791 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) 792 { 793 return readl(vop2->regs + offset); 794 } 795 796 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, 797 u32 mask, u32 shift, u32 v, 798 bool write_mask) 799 { 800 if (!mask) 801 return; 802 803 if (write_mask) { 804 v = ((v & mask) << shift) | (mask << (shift + 16)); 805 } else { 806 u32 cached_val = vop2->regsbak[offset >> 2]; 807 808 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 809 vop2->regsbak[offset >> 2] = v; 810 } 811 812 writel(v, vop2->regs + offset); 813 } 814 815 static inline void vop2_grf_writel(struct vop2 *vop, u32 offset, 816 u32 mask, u32 shift, u32 v) 817 { 818 u32 val = 0; 819 820 val = (v << shift) | (mask << (shift + 16)); 821 writel(val, vop->grf + offset); 822 } 823 824 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 825 { 826 return us * mode->clock / mode->htotal / 1000; 827 } 828 829 static char* get_output_if_name(u32 output_if, char *name) 830 { 831 if (output_if & VOP_OUTPUT_IF_RGB) 832 strcat(name, " RGB"); 833 if (output_if & VOP_OUTPUT_IF_BT1120) 834 strcat(name, " BT1120"); 835 if (output_if & VOP_OUTPUT_IF_BT656) 836 strcat(name, " BT656"); 837 if (output_if & VOP_OUTPUT_IF_LVDS0) 838 strcat(name, " LVDS0"); 839 if (output_if & VOP_OUTPUT_IF_LVDS1) 840 strcat(name, " LVDS1"); 841 if (output_if & VOP_OUTPUT_IF_MIPI0) 842 strcat(name, " MIPI0"); 843 if (output_if & VOP_OUTPUT_IF_MIPI1) 844 strcat(name, " MIPI1"); 845 if (output_if & VOP_OUTPUT_IF_eDP0) 846 strcat(name, " eDP0"); 847 if (output_if & VOP_OUTPUT_IF_eDP1) 848 strcat(name, " eDP1"); 849 if (output_if & VOP_OUTPUT_IF_DP0) 850 strcat(name, " DP0"); 851 if (output_if & VOP_OUTPUT_IF_DP1) 852 strcat(name, " DP1"); 853 if (output_if & VOP_OUTPUT_IF_HDMI0) 854 strcat(name, " HDMI0"); 855 if (output_if & VOP_OUTPUT_IF_HDMI1) 856 strcat(name, " HDMI1"); 857 858 return name; 859 } 860 861 static char *get_plane_name(int plane_id, char *name) 862 { 863 switch (plane_id) { 864 case ROCKCHIP_VOP2_CLUSTER0: 865 strcat(name, "Cluster0"); 866 break; 867 case ROCKCHIP_VOP2_CLUSTER1: 868 strcat(name, "Cluster1"); 869 break; 870 case ROCKCHIP_VOP2_ESMART0: 871 strcat(name, "Esmart0"); 872 break; 873 case ROCKCHIP_VOP2_ESMART1: 874 strcat(name, "Esmart1"); 875 break; 876 case ROCKCHIP_VOP2_SMART0: 877 strcat(name, "Smart0"); 878 break; 879 case ROCKCHIP_VOP2_SMART1: 880 strcat(name, "Smart1"); 881 break; 882 case ROCKCHIP_VOP2_CLUSTER2: 883 strcat(name, "Cluster2"); 884 break; 885 case ROCKCHIP_VOP2_CLUSTER3: 886 strcat(name, "Cluster3"); 887 break; 888 case ROCKCHIP_VOP2_ESMART2: 889 strcat(name, "Esmart2"); 890 break; 891 case ROCKCHIP_VOP2_ESMART3: 892 strcat(name, "Esmart3"); 893 break; 894 } 895 896 return name; 897 } 898 899 static bool is_yuv_output(u32 bus_format) 900 { 901 switch (bus_format) { 902 case MEDIA_BUS_FMT_YUV8_1X24: 903 case MEDIA_BUS_FMT_YUV10_1X30: 904 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 905 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 906 case MEDIA_BUS_FMT_YUYV8_2X8: 907 case MEDIA_BUS_FMT_YVYU8_2X8: 908 case MEDIA_BUS_FMT_UYVY8_2X8: 909 case MEDIA_BUS_FMT_VYUY8_2X8: 910 case MEDIA_BUS_FMT_YUYV8_1X16: 911 case MEDIA_BUS_FMT_YVYU8_1X16: 912 case MEDIA_BUS_FMT_UYVY8_1X16: 913 case MEDIA_BUS_FMT_VYUY8_1X16: 914 return true; 915 default: 916 return false; 917 } 918 } 919 920 static int vop2_convert_csc_mode(int csc_mode) 921 { 922 switch (csc_mode) { 923 case V4L2_COLORSPACE_SMPTE170M: 924 case V4L2_COLORSPACE_470_SYSTEM_M: 925 case V4L2_COLORSPACE_470_SYSTEM_BG: 926 return CSC_BT601L; 927 case V4L2_COLORSPACE_REC709: 928 case V4L2_COLORSPACE_SMPTE240M: 929 case V4L2_COLORSPACE_DEFAULT: 930 return CSC_BT709L; 931 case V4L2_COLORSPACE_JPEG: 932 return CSC_BT601F; 933 case V4L2_COLORSPACE_BT2020: 934 return CSC_BT2020; 935 default: 936 return CSC_BT709L; 937 } 938 } 939 940 static bool is_uv_swap(u32 bus_format, u32 output_mode) 941 { 942 /* 943 * FIXME: 944 * 945 * There is no media type for YUV444 output, 946 * so when out_mode is AAAA or P888, assume output is YUV444 on 947 * yuv format. 948 * 949 * From H/W testing, YUV444 mode need a rb swap. 950 */ 951 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 952 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 953 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 954 output_mode == ROCKCHIP_OUT_MODE_P888)) 955 return true; 956 else 957 return false; 958 } 959 960 static inline bool is_hot_plug_devices(int output_type) 961 { 962 switch (output_type) { 963 case DRM_MODE_CONNECTOR_HDMIA: 964 case DRM_MODE_CONNECTOR_HDMIB: 965 case DRM_MODE_CONNECTOR_TV: 966 case DRM_MODE_CONNECTOR_DisplayPort: 967 case DRM_MODE_CONNECTOR_VGA: 968 case DRM_MODE_CONNECTOR_Unknown: 969 return true; 970 default: 971 return false; 972 } 973 } 974 975 static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, 976 struct display_state *state) 977 { 978 struct connector_state *conn_state = &state->conn_state; 979 struct crtc_state *cstate = &state->crtc_state; 980 struct resource gamma_res; 981 fdt_size_t lut_size; 982 int i, lut_len, ret = 0; 983 u32 *lut_regs; 984 u32 *lut_val; 985 u32 r, g, b; 986 u32 vp_offset = cstate->crtc_id * 0x100; 987 struct base2_disp_info *disp_info = conn_state->disp_info; 988 static int gamma_lut_en_num = 1; 989 990 if (gamma_lut_en_num > vop2->data->nr_gammas) { 991 printf("warn: only %d vp support gamma\n", vop2->data->nr_gammas); 992 return 0; 993 } 994 995 if (!disp_info) 996 return 0; 997 998 if (!disp_info->gamma_lut_data.size) 999 return 0; 1000 1001 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); 1002 if (ret) 1003 printf("failed to get gamma lut res\n"); 1004 lut_regs = (u32 *)gamma_res.start; 1005 lut_size = gamma_res.end - gamma_res.start + 1; 1006 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 1007 printf("failed to get gamma lut register\n"); 1008 return 0; 1009 } 1010 lut_len = lut_size / 4; 1011 if (lut_len != 256 && lut_len != 1024) { 1012 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 1013 return 0; 1014 } 1015 lut_val = (u32 *)calloc(1, lut_size); 1016 for (i = 0; i < lut_len; i++) { 1017 r = disp_info->gamma_lut_data.lred[i] * (lut_len - 1) / 0xffff; 1018 g = disp_info->gamma_lut_data.lgreen[i] * (lut_len - 1) / 0xffff; 1019 b = disp_info->gamma_lut_data.lblue[i] * (lut_len - 1) / 0xffff; 1020 1021 lut_val[i] = b * lut_len * lut_len + g * lut_len + r; 1022 } 1023 1024 for (i = 0; i < lut_len; i++) 1025 writel(lut_val[i], lut_regs + i); 1026 1027 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, 1028 GAMMA_PORT_SEL_MASK, GAMMA_PORT_SEL_SHIFT, 1029 cstate->crtc_id , false); 1030 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1031 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); 1032 gamma_lut_en_num++; 1033 1034 return 0; 1035 } 1036 1037 static int rockchip_vop2_cubic_lut_init(struct vop2 *vop2, 1038 struct display_state *state) 1039 { 1040 struct connector_state *conn_state = &state->conn_state; 1041 struct crtc_state *cstate = &state->crtc_state; 1042 int i, cubic_lut_len; 1043 u32 vp_offset = cstate->crtc_id * 0x100; 1044 struct base2_disp_info *disp_info = conn_state->disp_info; 1045 struct base2_cubic_lut_data *lut = &conn_state->disp_info->cubic_lut_data; 1046 u32 *cubic_lut_addr; 1047 1048 if (!disp_info || CONFIG_ROCKCHIP_CUBIC_LUT_SIZE == 0) 1049 return 0; 1050 1051 if (!disp_info->cubic_lut_data.size) 1052 return 0; 1053 1054 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); 1055 cubic_lut_len = disp_info->cubic_lut_data.size; 1056 1057 for (i = 0; i < cubic_lut_len / 2; i++) { 1058 *cubic_lut_addr++ = ((lut->lred[2 * i]) & 0xfff) + 1059 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1060 ((lut->lblue[2 * i] & 0xff) << 24); 1061 *cubic_lut_addr++ = ((lut->lblue[2 * i] & 0xf00) >> 8) + 1062 ((lut->lred[2 * i + 1] & 0xfff) << 4) + 1063 ((lut->lgreen[2 * i + 1] & 0xfff) << 16) + 1064 ((lut->lblue[2 * i + 1] & 0xf) << 28); 1065 *cubic_lut_addr++ = (lut->lblue[2 * i + 1] & 0xff0) >> 4; 1066 *cubic_lut_addr++ = 0; 1067 } 1068 1069 if (cubic_lut_len % 2) { 1070 *cubic_lut_addr++ = (lut->lred[2 * i] & 0xfff) + 1071 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1072 ((lut->lblue[2 * i] & 0xff) << 24); 1073 *cubic_lut_addr++ = (lut->lblue[2 * i] & 0xf00) >> 8; 1074 *cubic_lut_addr++ = 0; 1075 *cubic_lut_addr = 0; 1076 } 1077 1078 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, 1079 get_cubic_lut_buffer(cstate->crtc_id)); 1080 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, 1081 EN_MASK, LUT_DMA_EN_SHIFT, 1, false); 1082 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1083 EN_MASK, VP0_3D_LUT_EN_SHIFT, 1, false); 1084 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1085 EN_MASK, VP0_3D_LUT_UPDATE_SHIFT, 1, false); 1086 1087 return 0; 1088 } 1089 1090 static void vop2_tv_config_update(struct display_state *state, struct vop2 *vop2) 1091 { 1092 struct connector_state *conn_state = &state->conn_state; 1093 struct base_bcsh_info *bcsh_info; 1094 struct crtc_state *cstate = &state->crtc_state; 1095 int brightness, contrast, saturation, hue, sin_hue, cos_hue; 1096 bool bcsh_en = false, post_r2y_en = false, post_y2r_en = false; 1097 u32 vp_offset = (cstate->crtc_id * 0x100); 1098 int post_csc_mode; 1099 1100 if (!conn_state->disp_info) 1101 return; 1102 bcsh_info = &conn_state->disp_info->bcsh_info; 1103 if (!bcsh_info) 1104 return; 1105 1106 if (bcsh_info->brightness != 50 || 1107 bcsh_info->contrast != 50 || 1108 bcsh_info->saturation != 50 || bcsh_info->hue != 50) 1109 bcsh_en = true; 1110 1111 if (bcsh_en) { 1112 if (!cstate->yuv_overlay) 1113 post_r2y_en = 1; 1114 if (!is_yuv_output(conn_state->bus_format)) 1115 post_y2r_en = 1; 1116 } else { 1117 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) 1118 post_r2y_en = 1; 1119 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) 1120 post_y2r_en = 1; 1121 } 1122 1123 post_csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1124 1125 1126 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, 1127 BCSH_CTRL_R2Y_SHIFT, post_r2y_en, false); 1128 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, 1129 BCSH_CTRL_Y2R_SHIFT, post_y2r_en, false); 1130 1131 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, 1132 BCSH_CTRL_R2Y_CSC_MODE_SHIFT, post_csc_mode, false); 1133 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, 1134 BCSH_CTRL_Y2R_CSC_MODE_SHIFT, post_csc_mode, false); 1135 if (!bcsh_en) { 1136 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1137 BCSH_EN_MASK, BCSH_EN_SHIFT, 0, false); 1138 return; 1139 } 1140 1141 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT) 1142 brightness = interpolate(0, -128, 100, 127, 1143 bcsh_info->brightness); 1144 else 1145 brightness = interpolate(0, -32, 100, 31, 1146 bcsh_info->brightness); 1147 contrast = interpolate(0, 0, 100, 511, bcsh_info->contrast); 1148 saturation = interpolate(0, 0, 100, 511, bcsh_info->saturation); 1149 hue = interpolate(0, -30, 100, 30, bcsh_info->hue); 1150 1151 1152 /* 1153 * a:[-30~0): 1154 * sin_hue = 0x100 - sin(a)*256; 1155 * cos_hue = cos(a)*256; 1156 * a:[0~30] 1157 * sin_hue = sin(a)*256; 1158 * cos_hue = cos(a)*256; 1159 */ 1160 sin_hue = fixp_sin32(hue) >> 23; 1161 cos_hue = fixp_cos32(hue) >> 23; 1162 1163 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1164 BCSH_BRIGHTNESS_MASK, BCSH_BRIGHTNESS_SHIFT, 1165 brightness, false); 1166 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1167 BCSH_CONTRAST_MASK, BCSH_CONTRAST_SHIFT, contrast, false); 1168 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1169 BCSH_SATURATION_MASK, BCSH_SATURATION_SHIFT, 1170 saturation * contrast / 0x100, false); 1171 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1172 BCSH_SIN_HUE_MASK, BCSH_SIN_HUE_SHIFT, sin_hue, false); 1173 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1174 BCSH_COS_HUE_MASK, BCSH_COS_HUE_SHIFT, cos_hue, false); 1175 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1176 BCSH_OUT_MODE_MASK, BCSH_OUT_MODE_SHIFT, 1177 BCSH_OUT_MODE_NORMAL_VIDEO, false); 1178 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1179 BCSH_EN_MASK, BCSH_EN_SHIFT, 1, false); 1180 } 1181 1182 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) 1183 { 1184 struct connector_state *conn_state = &state->conn_state; 1185 struct drm_display_mode *mode = &conn_state->mode; 1186 struct crtc_state *cstate = &state->crtc_state; 1187 u32 vp_offset = (cstate->crtc_id * 0x100); 1188 u16 vtotal = mode->crtc_vtotal; 1189 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1190 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1191 u16 hdisplay = mode->crtc_hdisplay; 1192 u16 vdisplay = mode->crtc_vdisplay; 1193 u16 hsize = 1194 hdisplay * (conn_state->overscan.left_margin + 1195 conn_state->overscan.right_margin) / 200; 1196 u16 vsize = 1197 vdisplay * (conn_state->overscan.top_margin + 1198 conn_state->overscan.bottom_margin) / 200; 1199 u16 hact_end, vact_end; 1200 u32 val; 1201 u32 bg_ovl_dly, bg_dly, pre_scan_dly; 1202 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1203 1204 hsize = round_down(hsize, 2); 1205 vsize = round_down(vsize, 2); 1206 1207 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 1208 hact_end = hact_st + hsize; 1209 val = hact_st << 16; 1210 val |= hact_end; 1211 1212 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); 1213 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 1214 vact_end = vact_st + vsize; 1215 val = vact_st << 16; 1216 val |= vact_end; 1217 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); 1218 val = scl_cal_scale2(vdisplay, vsize) << 16; 1219 val |= scl_cal_scale2(hdisplay, hsize); 1220 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); 1221 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 1222 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 1223 vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, 1224 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 1225 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 1226 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1227 u16 vact_st_f1 = vtotal + vact_st + 1; 1228 u16 vact_end_f1 = vact_st_f1 + vsize; 1229 1230 val = vact_st_f1 << 16 | vact_end_f1; 1231 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); 1232 } 1233 1234 bg_ovl_dly = cstate->crtc->vps[cstate->crtc_id].bg_ovl_dly; 1235 bg_dly = vop2->data->vp_data[cstate->crtc_id].pre_scan_max_dly; 1236 bg_dly -= bg_ovl_dly; 1237 pre_scan_dly = bg_dly + (hdisplay >> 1) - 1; 1238 pre_scan_dly = (pre_scan_dly << 16) | hsync_len; 1239 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + cstate->crtc_id * 4, 1240 BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false); 1241 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + vp_offset, pre_scan_dly); 1242 } 1243 1244 static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) 1245 { 1246 struct crtc_state *cstate = &state->crtc_state; 1247 int i, j, port_mux = 0, total_used_layer = 0; 1248 u8 shift = 0; 1249 int layer_phy_id = 0; 1250 u32 layer_nr = 0; 1251 struct vop2_win_data *win_data; 1252 struct vop2_vp_plane_mask *plane_mask; 1253 1254 if (vop2->global_init) 1255 return; 1256 1257 /* OTP must enable at the first time, otherwise mirror layer register is error */ 1258 if (soc_is_rk3566()) 1259 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, 1260 OTP_WIN_EN_SHIFT, 1, false); 1261 1262 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); 1263 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, 1264 OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); 1265 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1266 IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); 1267 1268 if (cstate->crtc->assign_plane) {/* dts assign plane */ 1269 u32 plane_mask; 1270 int primary_plane_id; 1271 1272 for (i = 0; i < vop2->data->nr_vps; i++) { 1273 plane_mask = cstate->crtc->vps[i].plane_mask; 1274 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1275 layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */ 1276 vop2->vp_plane_mask[i].attached_layers_nr = layer_nr; 1277 primary_plane_id = vop2_get_primary_plane(vop2, plane_mask); 1278 vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; 1279 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1280 1281 /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/ 1282 for (j = 0; j < layer_nr; j++) { 1283 vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; 1284 plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); 1285 } 1286 } 1287 } else {/* need soft assign plane mask */ 1288 /* find the first unplug devices and set it as main display */ 1289 int main_vp_index = -1; 1290 int active_vp_num = 0; 1291 1292 for (i = 0; i < vop2->data->nr_vps; i++) { 1293 if (cstate->crtc->vps[i].enable) 1294 active_vp_num++; 1295 } 1296 printf("VOP have %d active VP\n", active_vp_num); 1297 1298 if (soc_is_rk3566() && active_vp_num > 2) 1299 printf("ERROR: rk3566 only support 2 display output!!\n"); 1300 plane_mask = vop2->data->plane_mask; 1301 plane_mask += (active_vp_num - 1) * VOP2_VP_MAX; 1302 1303 for (i = 0; i < vop2->data->nr_vps; i++) { 1304 if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { 1305 vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/ 1306 main_vp_index = i; 1307 break; 1308 } 1309 } 1310 1311 /* if no find unplug devices, use vp0 as main display */ 1312 if (main_vp_index < 0) { 1313 main_vp_index = 0; 1314 vop2->vp_plane_mask[0] = plane_mask[0]; 1315 } 1316 1317 j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */ 1318 1319 /* init other display except main display */ 1320 for (i = 0; i < vop2->data->nr_vps; i++) { 1321 if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */ 1322 continue; 1323 vop2->vp_plane_mask[i] = plane_mask[j++]; 1324 } 1325 1326 /* store plane mask for vop2_fixup_dts */ 1327 for (i = 0; i < vop2->data->nr_vps; i++) { 1328 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1329 /* rk3566 only support 3+3 policy */ 1330 if (soc_is_rk3566() && active_vp_num == 1) { 1331 if (cstate->crtc->vps[i].enable) { 1332 for (j = 0; j < 3; j++) { 1333 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1334 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1335 } 1336 } 1337 } else { 1338 for (j = 0; j < layer_nr; j++) { 1339 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1340 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1341 } 1342 } 1343 } 1344 } 1345 1346 for (i = 0; i < vop2->data->nr_vps; i++) { 1347 printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); 1348 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) 1349 printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]); 1350 printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id); 1351 } 1352 1353 shift = 0; 1354 /* layer sel win id */ 1355 for (i = 0; i < vop2->data->nr_vps; i++) { 1356 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1357 for (j = 0; j < layer_nr; j++) { 1358 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1359 win_data = &vop2->data->win_data[layer_phy_id]; 1360 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, 1361 shift, win_data->layer_sel_win_id, false); 1362 shift += 4; 1363 } 1364 } 1365 1366 /* win sel port */ 1367 for (i = 0; i < vop2->data->nr_vps; i++) { 1368 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1369 for (j = 0; j < layer_nr; j++) { 1370 if (!cstate->crtc->vps[i].enable) 1371 continue; 1372 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1373 win_data = &vop2->data->win_data[layer_phy_id]; 1374 shift = win_data->win_sel_port_offset * 2; 1375 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, 1376 LAYER_SEL_PORT_SHIFT + shift, i, false); 1377 } 1378 } 1379 1380 /** 1381 * port mux config 1382 */ 1383 for (i = 0; i < vop2->data->nr_vps; i++) { 1384 shift = i * 4; 1385 if (cstate->crtc->vps[i].enable) { 1386 total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; 1387 port_mux = total_used_layer - 1; 1388 } else { 1389 port_mux = 8; 1390 } 1391 1392 if (i == vop2->data->nr_vps - 1) 1393 port_mux = vop2->data->nr_mixers; 1394 1395 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; 1396 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, 1397 PORT_MUX_SHIFT + shift, port_mux, false); 1398 } 1399 1400 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); 1401 1402 vop2->global_init = true; 1403 } 1404 1405 static int vop2_initial(struct vop2 *vop2, struct display_state *state) 1406 { 1407 struct crtc_state *cstate = &state->crtc_state; 1408 struct connector_state *conn_state = &state->conn_state; 1409 struct drm_display_mode *mode = &conn_state->mode; 1410 char dclk_name[9]; 1411 struct clk dclk; 1412 int ret; 1413 1414 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1415 ret = clk_set_defaults(cstate->dev); 1416 if (ret) 1417 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1418 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); 1419 ret = clk_get_by_name(cstate->dev, dclk_name, &dclk); 1420 if (!ret) 1421 ret = clk_set_rate(&dclk, mode->clock * 1000); 1422 if (IS_ERR_VALUE(ret)) { 1423 printf("%s: Failed to set vp%d dclk[%d khz]: ret=%d\n", 1424 __func__, cstate->crtc_id, mode->clock, ret); 1425 return ret; 1426 } 1427 1428 rockchip_vop2_gamma_lut_init(vop2, state); 1429 rockchip_vop2_cubic_lut_init(vop2, state); 1430 1431 return 0; 1432 } 1433 1434 /* 1435 * VOP2 have multi video ports. 1436 * video port ------- crtc 1437 */ 1438 static int rockchip_vop2_preinit(struct display_state *state) 1439 { 1440 struct crtc_state *cstate = &state->crtc_state; 1441 const struct vop2_data *vop2_data = cstate->crtc->data; 1442 1443 if (!rockchip_vop2) { 1444 rockchip_vop2 = calloc(1, sizeof(struct vop2)); 1445 if (!rockchip_vop2) 1446 return -ENOMEM; 1447 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); 1448 rockchip_vop2->regsbak = malloc(RK3568_MAX_REG); 1449 rockchip_vop2->reg_len = RK3568_MAX_REG; 1450 rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1451 if (rockchip_vop2->grf <= 0) 1452 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf); 1453 1454 rockchip_vop2->version = vop2_data->version; 1455 rockchip_vop2->data = vop2_data; 1456 } 1457 1458 cstate->private = rockchip_vop2; 1459 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; 1460 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; 1461 1462 vop2_global_initial(rockchip_vop2, state); 1463 1464 return 0; 1465 } 1466 1467 static int rockchip_vop2_init(struct display_state *state) 1468 { 1469 struct crtc_state *cstate = &state->crtc_state; 1470 struct connector_state *conn_state = &state->conn_state; 1471 struct drm_display_mode *mode = &conn_state->mode; 1472 struct vop2 *vop2 = cstate->private; 1473 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1474 u16 hdisplay = mode->crtc_hdisplay; 1475 u16 htotal = mode->crtc_htotal; 1476 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1477 u16 hact_end = hact_st + hdisplay; 1478 u16 vdisplay = mode->crtc_vdisplay; 1479 u16 vtotal = mode->crtc_vtotal; 1480 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 1481 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1482 u16 vact_end = vact_st + vdisplay; 1483 bool yuv_overlay = false; 1484 u32 vp_offset = (cstate->crtc_id * 0x100); 1485 u32 val; 1486 bool dclk_inv; 1487 u8 dither_down_en = 0; 1488 u8 pre_dither_down_en = 0; 1489 char output_type_name[30] = {0}; 1490 1491 printf("VOP update mode to: %dx%d%s%d, type:%s for VP%d\n", 1492 mode->hdisplay, mode->vdisplay, 1493 mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 1494 mode->vscan, 1495 get_output_if_name(conn_state->output_if, output_type_name), 1496 cstate->crtc_id); 1497 1498 vop2_initial(vop2, state); 1499 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 1500 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 1501 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 1502 1503 if (conn_state->output_if & VOP_OUTPUT_IF_RGB) { 1504 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 1505 1, false); 1506 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1507 RGB_MUX_SHIFT, cstate->crtc_id, false); 1508 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1509 GRF_RGB_DCLK_INV_SHIFT, dclk_inv); 1510 } 1511 1512 if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) { 1513 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 1514 1, false); 1515 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, 1516 BT1120_EN_SHIFT, 1, false); 1517 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1518 RGB_MUX_SHIFT, cstate->crtc_id, false); 1519 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1520 GRF_BT1120_CLK_INV_SHIFT, !dclk_inv); 1521 } 1522 1523 if (conn_state->output_if & VOP_OUTPUT_IF_BT656) { 1524 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, 1525 1, false); 1526 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1527 RGB_MUX_SHIFT, cstate->crtc_id, false); 1528 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1529 GRF_BT656_CLK_INV_SHIFT, !dclk_inv); 1530 } 1531 1532 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) { 1533 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, 1534 1, false); 1535 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1536 LVDS0_MUX_SHIFT, cstate->crtc_id, false); 1537 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1538 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 1539 } 1540 1541 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) { 1542 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, 1543 1, false); 1544 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1545 LVDS1_MUX_SHIFT, cstate->crtc_id, false); 1546 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1547 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 1548 } 1549 1550 if (conn_state->output_flags & 1551 (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE | 1552 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) { 1553 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1554 LVDS_DUAL_EN_SHIFT, 1, false); 1555 if (conn_state->output_flags & 1556 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 1557 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1558 LVDS_DUAL_LEFT_RIGHT_EN_SHIFT, 1, 1559 false); 1560 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 1561 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1562 LVDS_DUAL_SWAP_EN_SHIFT, 1, false); 1563 } 1564 1565 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) { 1566 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, 1567 1, false); 1568 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1569 MIPI0_MUX_SHIFT, cstate->crtc_id, false); 1570 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1571 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 1572 } 1573 1574 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI1) { 1575 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, 1576 1, false); 1577 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1578 MIPI1_MUX_SHIFT, cstate->crtc_id, false); 1579 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1580 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 1581 } 1582 1583 if (conn_state->output_flags & 1584 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 1585 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 1586 MIPI_DUAL_EN_SHIFT, 1, false); 1587 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 1588 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1589 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 1590 false); 1591 } 1592 1593 if (conn_state->output_if & VOP_OUTPUT_IF_eDP0) { 1594 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, 1595 1, false); 1596 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1597 EDP0_MUX_SHIFT, cstate->crtc_id, false); 1598 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1599 IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false); 1600 } 1601 1602 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) { 1603 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, 1604 1, false); 1605 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1606 HDMI0_MUX_SHIFT, cstate->crtc_id, false); 1607 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1608 IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false); 1609 vop2_mask_write(vop2, RK3568_DSP_IF_POL, 1610 IF_CRTL_HDMI_PIN_POL_MASK, 1611 IF_CRTL_HDMI_PIN_POL_SHIT, val, false); 1612 } 1613 1614 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1615 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT)) 1616 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1617 1618 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 1619 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1620 DATA_SWAP_MASK, DATA_SWAP_SHIFT, DSP_RB_SWAP, 1621 false); 1622 else 1623 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1624 DATA_SWAP_MASK, DATA_SWAP_SHIFT, 0, 1625 false); 1626 1627 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, 1628 OUT_MODE_SHIFT, conn_state->output_mode, false); 1629 1630 switch (conn_state->bus_format) { 1631 case MEDIA_BUS_FMT_RGB565_1X16: 1632 dither_down_en = 1; 1633 break; 1634 case MEDIA_BUS_FMT_RGB666_1X18: 1635 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 1636 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 1637 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 1638 dither_down_en = 1; 1639 break; 1640 case MEDIA_BUS_FMT_YUV8_1X24: 1641 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1642 dither_down_en = 0; 1643 pre_dither_down_en = 1; 1644 break; 1645 case MEDIA_BUS_FMT_YUV10_1X30: 1646 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1647 case MEDIA_BUS_FMT_RGB888_1X24: 1648 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 1649 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 1650 default: 1651 dither_down_en = 0; 1652 pre_dither_down_en = 0; 1653 break; 1654 } 1655 1656 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 1657 pre_dither_down_en = 0; 1658 else 1659 pre_dither_down_en = 1; 1660 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1661 DITHER_DOWN_EN_SHIFT, dither_down_en, false); 1662 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1663 PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false); 1664 1665 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0; 1666 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, 1667 yuv_overlay, false); 1668 1669 cstate->yuv_overlay = yuv_overlay; 1670 1671 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, 1672 (htotal << 16) | hsync_len); 1673 val = hact_st << 16; 1674 val |= hact_end; 1675 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); 1676 val = vact_st << 16; 1677 val |= vact_end; 1678 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); 1679 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1680 u16 vact_st_f1 = vtotal + vact_st + 1; 1681 u16 vact_end_f1 = vact_st_f1 + vdisplay; 1682 1683 val = vact_st_f1 << 16 | vact_end_f1; 1684 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, 1685 val); 1686 1687 val = vtotal << 16 | (vtotal + vsync_len); 1688 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); 1689 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1690 INTERLACE_EN_SHIFT, 1, false); 1691 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1692 DSP_FILED_POL, 1, false); 1693 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1694 P2I_EN_SHIFT, 1, false); 1695 vtotal += vtotal + 1; 1696 } else { 1697 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1698 INTERLACE_EN_SHIFT, 0, false); 1699 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1700 P2I_EN_SHIFT, 0, false); 1701 } 1702 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, 1703 (vtotal << 16) | vsync_len); 1704 val = !!(mode->flags & DRM_MODE_FLAG_DBLCLK); 1705 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1706 CORE_DCLK_DIV_EN_SHIFT, val, false); 1707 1708 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) 1709 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1710 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0x3, false); 1711 else 1712 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1713 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0, false); 1714 1715 if (yuv_overlay) 1716 val = 0x20010200; 1717 else 1718 val = 0; 1719 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); 1720 1721 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1722 POST_DSP_OUT_R2Y_SHIFT, yuv_overlay, false); 1723 1724 vop2_tv_config_update(state, vop2); 1725 vop2_post_config(state, vop2); 1726 1727 return 0; 1728 } 1729 1730 static void vop2_setup_scale(struct vop2 *vop2, uint32_t win_offset, 1731 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 1732 uint32_t dst_h) 1733 { 1734 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 1735 uint16_t hscl_filter_mode, vscl_filter_mode; 1736 uint8_t gt2 = 0, gt4 = 0; 1737 uint32_t xfac = 0, yfac = 0; 1738 uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC; 1739 uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL; 1740 uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL; 1741 uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL; 1742 1743 if (src_h >= (4 * dst_h)) 1744 gt4 = 1; 1745 else if (src_h >= (2 * dst_h)) 1746 gt2 = 1; 1747 1748 if (gt4) 1749 src_h >>= 2; 1750 else if (gt2) 1751 src_h >>= 1; 1752 1753 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 1754 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 1755 1756 if (yrgb_hor_scl_mode == SCALE_UP) 1757 hscl_filter_mode = hsu_filter_mode; 1758 else 1759 hscl_filter_mode = hsd_filter_mode; 1760 1761 if (yrgb_ver_scl_mode == SCALE_UP) 1762 vscl_filter_mode = vsu_filter_mode; 1763 else 1764 vscl_filter_mode = vsd_filter_mode; 1765 1766 /* 1767 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 1768 * at scale down mode 1769 */ 1770 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 1771 printf("win dst_w[%d] should align as 2 pixel\n", dst_w); 1772 dst_w += 1; 1773 } 1774 1775 xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w); 1776 yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h); 1777 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset, 1778 yfac << 16 | xfac); 1779 1780 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 1781 YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false); 1782 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 1783 YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false); 1784 1785 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1786 YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 1787 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1788 YRGB_YSCL_MODE_MASK, YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 1789 1790 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1791 YRGB_XSCL_FILTER_MODE_MASK, YRGB_XSCL_FILTER_MODE_SHIFT, 1792 hscl_filter_mode, false); 1793 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1794 YRGB_YSCL_FILTER_MODE_MASK, YRGB_YSCL_FILTER_MODE_SHIFT, 1795 vscl_filter_mode, false); 1796 } 1797 1798 static int rockchip_vop2_set_plane(struct display_state *state) 1799 { 1800 struct crtc_state *cstate = &state->crtc_state; 1801 struct connector_state *conn_state = &state->conn_state; 1802 struct drm_display_mode *mode = &conn_state->mode; 1803 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 1804 struct vop2 *vop2 = cstate->private; 1805 int src_w = cstate->src_w; 1806 int src_h = cstate->src_h; 1807 int crtc_x = cstate->crtc_x; 1808 int crtc_y = cstate->crtc_y; 1809 int crtc_w = cstate->crtc_w; 1810 int crtc_h = cstate->crtc_h; 1811 int xvir = cstate->xvir; 1812 int y_mirror = 0; 1813 int csc_mode; 1814 u32 win_offset; 1815 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1816 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 1817 char plane_name[10] = {0}; 1818 1819 win_offset = vop2->data->win_data[primary_plane_id].reg_offset; 1820 if (crtc_w > cstate->max_output.width) { 1821 printf("ERROR: output w[%d] exceeded max width[%d]\n", 1822 crtc_w, cstate->max_output.width); 1823 return -EINVAL; 1824 } 1825 1826 /* 1827 * This is workaround solution for IC design: 1828 * esmart can't support scale down when actual_w % 16 == 1. 1829 */ 1830 if (src_w > crtc_w && (src_w & 0xf) == 1) { 1831 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); 1832 src_w -= 1; 1833 } 1834 1835 act_info = (src_h - 1) << 16; 1836 act_info |= (src_w - 1) & 0xffff; 1837 1838 dsp_info = (crtc_h - 1) << 16; 1839 dsp_info |= (crtc_w - 1) & 0xffff; 1840 1841 dsp_stx = crtc_x; 1842 dsp_sty = crtc_y; 1843 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 1844 1845 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 1846 y_mirror = 1; 1847 else 1848 y_mirror = 0; 1849 1850 vop2_setup_scale(vop2, win_offset, src_w, src_h, crtc_w, crtc_h); 1851 1852 if (y_mirror) 1853 cstate->dma_addr += (src_h - 1) * xvir * 4; 1854 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, 1855 YMIRROR_EN_SHIFT, y_mirror, false); 1856 1857 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 1858 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 1859 false); 1860 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); 1861 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, 1862 cstate->dma_addr); 1863 1864 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, 1865 act_info); 1866 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, 1867 dsp_info); 1868 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); 1869 1870 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, 1871 WIN_EN_SHIFT, 1, false); 1872 1873 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1874 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, 1875 RGB2YUV_EN_SHIFT, 1876 is_yuv_output(conn_state->bus_format), false); 1877 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, 1878 CSC_MODE_SHIFT, csc_mode, false); 1879 1880 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1881 1882 printf("VOP VP%d enable %s[%dx%d->%dx%d@%dx%d] fmt[%d] addr[0x%x]\n", 1883 cstate->crtc_id, get_plane_name(primary_plane_id, plane_name), 1884 src_w, src_h, crtc_w, crtc_h, crtc_x, crtc_y, cstate->format, 1885 cstate->dma_addr); 1886 1887 return 0; 1888 } 1889 1890 static int rockchip_vop2_prepare(struct display_state *state) 1891 { 1892 return 0; 1893 } 1894 1895 static int rockchip_vop2_enable(struct display_state *state) 1896 { 1897 struct crtc_state *cstate = &state->crtc_state; 1898 struct vop2 *vop2 = cstate->private; 1899 u32 vp_offset = (cstate->crtc_id * 0x100); 1900 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1901 1902 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1903 STANDBY_EN_SHIFT, 0, false); 1904 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1905 1906 return 0; 1907 } 1908 1909 static int rockchip_vop2_disable(struct display_state *state) 1910 { 1911 struct crtc_state *cstate = &state->crtc_state; 1912 struct vop2 *vop2 = cstate->private; 1913 u32 vp_offset = (cstate->crtc_id * 0x100); 1914 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1915 1916 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1917 STANDBY_EN_SHIFT, 1, false); 1918 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1919 1920 return 0; 1921 } 1922 1923 static int rockchip_vop2_get_cursor_plane(struct display_state *state, u32 plane_mask, int cursor_plane) 1924 { 1925 struct crtc_state *cstate = &state->crtc_state; 1926 struct vop2 *vop2 = cstate->private; 1927 int i = 0; 1928 int correct_cursor_plane = -1; 1929 int plane_type = -1; 1930 1931 if (cursor_plane < 0) 1932 return -1; 1933 1934 if (plane_mask & (1 << cursor_plane)) 1935 return cursor_plane; 1936 1937 /* Get current cursor plane type */ 1938 for (i = 0; i < vop2->data->nr_layers; i++) { 1939 if (vop2->data->plane_table[i].plane_id == cursor_plane) { 1940 plane_type = vop2->data->plane_table[i].plane_type; 1941 break; 1942 } 1943 } 1944 1945 /* Get the other same plane type plane id */ 1946 for (i = 0; i < vop2->data->nr_layers; i++) { 1947 if (vop2->data->plane_table[i].plane_type == plane_type && 1948 vop2->data->plane_table[i].plane_id != cursor_plane) { 1949 correct_cursor_plane = vop2->data->plane_table[i].plane_id; 1950 break; 1951 } 1952 } 1953 1954 /* To check whether the new correct_cursor_plane is attach to current vp */ 1955 if (correct_cursor_plane < 0 || !(plane_mask & (1 << correct_cursor_plane))) { 1956 printf("error: faild to find correct plane as cursor plane\n"); 1957 return -1; 1958 } 1959 1960 printf("vp%d adjust cursor plane from %d to %d\n", 1961 cstate->crtc_id, cursor_plane, correct_cursor_plane); 1962 1963 return correct_cursor_plane; 1964 } 1965 1966 static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) 1967 { 1968 struct crtc_state *cstate = &state->crtc_state; 1969 struct vop2 *vop2 = cstate->private; 1970 ofnode vp_node; 1971 struct device_node *port_parent_node = cstate->ports_node; 1972 static bool vop_fix_dts; 1973 const char *path; 1974 u32 plane_mask = 0; 1975 int vp_id = 0; 1976 int cursor_plane_id = -1; 1977 1978 if (vop_fix_dts) 1979 return 0; 1980 1981 ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) { 1982 path = vp_node.np->full_name; 1983 plane_mask = vop2->vp_plane_mask[vp_id].plane_mask; 1984 1985 if (cstate->crtc->assign_plane) 1986 continue; 1987 cursor_plane_id = rockchip_vop2_get_cursor_plane(state, plane_mask, 1988 cstate->crtc->vps[vp_id].cursor_plane); 1989 printf("vp%d, plane_mask:0x%x, primary-id:%d, curser-id:%d\n", 1990 vp_id, plane_mask, 1991 vop2->vp_plane_mask[vp_id].primary_plane_id, 1992 cursor_plane_id); 1993 1994 do_fixup_by_path_u32(blob, path, "rockchip,plane-mask", 1995 plane_mask, 1); 1996 do_fixup_by_path_u32(blob, path, "rockchip,primary-plane", 1997 vop2->vp_plane_mask[vp_id].primary_plane_id, 1); 1998 if (cursor_plane_id >= 0) 1999 do_fixup_by_path_u32(blob, path, "cursor-win-id", 2000 cursor_plane_id, 1); 2001 vp_id++; 2002 } 2003 2004 vop_fix_dts = true; 2005 2006 return 0; 2007 } 2008 2009 static struct vop2_plane_table rk356x_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { 2010 {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, 2011 {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, 2012 {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, 2013 {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, 2014 {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, 2015 {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, 2016 }; 2017 2018 static struct vop2_vp_plane_mask rk356x_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 2019 { /* one display policy */ 2020 {/* main display */ 2021 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 2022 .attached_layers_nr = 6, 2023 .attached_layers = { 2024 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0, 2025 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 2026 }, 2027 }, 2028 {/* second display */}, 2029 {/* third display */}, 2030 {/* fourth display */}, 2031 }, 2032 2033 { /* two display policy */ 2034 {/* main display */ 2035 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 2036 .attached_layers_nr = 3, 2037 .attached_layers = { 2038 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 2039 }, 2040 }, 2041 2042 {/* second display */ 2043 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 2044 .attached_layers_nr = 3, 2045 .attached_layers = { 2046 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 2047 }, 2048 }, 2049 {/* third display */}, 2050 {/* fourth display */}, 2051 }, 2052 2053 { /* three display policy */ 2054 {/* main display */ 2055 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 2056 .attached_layers_nr = 3, 2057 .attached_layers = { 2058 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 2059 }, 2060 }, 2061 2062 {/* second display */ 2063 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 2064 .attached_layers_nr = 2, 2065 .attached_layers = { 2066 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_SMART1 2067 }, 2068 }, 2069 2070 {/* third display */ 2071 .primary_plane_id = ROCKCHIP_VOP2_ESMART1, 2072 .attached_layers_nr = 1, 2073 .attached_layers = { ROCKCHIP_VOP2_ESMART1 }, 2074 }, 2075 2076 {/* fourth display */}, 2077 }, 2078 2079 {/* reserved for four display policy */}, 2080 }; 2081 2082 static struct vop2_win_data rk3568_win_data[6] = { 2083 { 2084 .name = "Cluster0", 2085 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 2086 .win_sel_port_offset = 0, 2087 .layer_sel_win_id = 0, 2088 .reg_offset = 0, 2089 }, 2090 2091 { 2092 .name = "Cluster1", 2093 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 2094 .win_sel_port_offset = 1, 2095 .layer_sel_win_id = 1, 2096 .reg_offset = 0x200, 2097 }, 2098 2099 { 2100 .name = "Esmart0", 2101 .phys_id = ROCKCHIP_VOP2_ESMART0, 2102 .win_sel_port_offset = 4, 2103 .layer_sel_win_id = 2, 2104 .reg_offset = 0, 2105 }, 2106 2107 { 2108 .name = "Esmart1", 2109 .phys_id = ROCKCHIP_VOP2_ESMART1, 2110 .win_sel_port_offset = 5, 2111 .layer_sel_win_id = 6, 2112 .reg_offset = 0x200, 2113 }, 2114 2115 { 2116 .name = "Smart0", 2117 .phys_id = ROCKCHIP_VOP2_SMART0, 2118 .win_sel_port_offset = 6, 2119 .layer_sel_win_id = 3, 2120 .reg_offset = 0x400, 2121 }, 2122 2123 { 2124 .name = "Smart1", 2125 .phys_id = ROCKCHIP_VOP2_SMART1, 2126 .win_sel_port_offset = 7, 2127 .layer_sel_win_id = 7, 2128 .reg_offset = 0x600, 2129 }, 2130 }; 2131 2132 static struct vop2_vp_data rk3568_vp_data[3] = { 2133 { 2134 .feature = VOP_FEATURE_OUTPUT_10BIT, 2135 .pre_scan_max_dly = 42, 2136 .max_output = {4096, 2304}, 2137 }, 2138 { 2139 .feature = 0, 2140 .pre_scan_max_dly = 40, 2141 .max_output = {2048, 1536}, 2142 }, 2143 { 2144 .feature = 0, 2145 .pre_scan_max_dly = 40, 2146 .max_output = {1920, 1080}, 2147 }, 2148 }; 2149 2150 const struct vop2_data rk3568_vop = { 2151 .nr_vps = 3, 2152 .vp_data = rk3568_vp_data, 2153 .win_data = rk3568_win_data, 2154 .plane_mask = rk356x_vp_plane_mask[0], 2155 .plane_table = rk356x_plane_table, 2156 .nr_layers = 6, 2157 .nr_mixers = 5, 2158 .nr_gammas = 1, 2159 }; 2160 2161 const struct rockchip_crtc_funcs rockchip_vop2_funcs = { 2162 .preinit = rockchip_vop2_preinit, 2163 .prepare = rockchip_vop2_prepare, 2164 .init = rockchip_vop2_init, 2165 .set_plane = rockchip_vop2_set_plane, 2166 .enable = rockchip_vop2_enable, 2167 .disable = rockchip_vop2_disable, 2168 .fixup_dts = rockchip_vop2_fixup_dts, 2169 }; 2170