1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <linux/list.h> 17 #include <linux/media-bus-format.h> 18 #include <clk.h> 19 #include <asm/arch/clock.h> 20 #include <linux/err.h> 21 #include <dm/device.h> 22 #include <dm/read.h> 23 #include <syscon.h> 24 25 #include "rockchip_display.h" 26 #include "rockchip_crtc.h" 27 #include "rockchip_connector.h" 28 29 /* System registers definition */ 30 #define RK3568_REG_CFG_DONE 0x000 31 #define CFG_DONE_EN BIT(15) 32 33 #define RK3568_VERSION_INFO 0x004 34 35 #define EN_MASK 1 36 37 #define RK3568_DSP_IF_EN 0x028 38 #define RGB_EN_SHIFT 0 39 #define HDMI0_EN_SHIFT 1 40 #define EDP0_EN_SHIFT 3 41 #define MIPI0_EN_SHIFT 4 42 #define MIPI1_EN_SHIFT 20 43 #define LVDS0_EN_SHIFT 5 44 #define LVDS1_EN_SHIFT 24 45 #define BT1120_EN_SHIFT 6 46 #define BT656_EN_SHIFT 7 47 #define IF_MUX_MASK 3 48 #define RGB_MUX_SHIFT 8 49 #define HDMI0_MUX_SHIFT 10 50 #define EDP0_MUX_SHIFT 14 51 #define MIPI0_MUX_SHIFT 16 52 #define MIPI1_MUX_SHIFT 21 53 #define LVDS0_MUX_SHIFT 18 54 #define LVDS1_MUX_SHIFT 25 55 56 #define RK3568_DSP_IF_CTRL 0x02c 57 #define LVDS_DUAL_EN_SHIFT 0 58 #define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1 59 #define LVDS_DUAL_SWAP_EN_SHIFT 2 60 #define RK3568_DSP_IF_POL 0x030 61 #define IF_CTRL_REG_DONE_IMD_MASK 1 62 #define IF_CTRL_REG_DONE_IMD_SHIFT 28 63 #define IF_CRTL_MIPI_DCLK_POL_SHIT 19 64 #define IF_CRTL_EDP_DCLK_POL_SHIT 15 65 #define IF_CRTL_HDMI_DCLK_POL_SHIT 7 66 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7 67 #define IF_CRTL_HDMI_PIN_POL_SHIT 4 68 #define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3 69 #define RK3568_SYS_OTP_WIN_EN 0x50 70 #define OTP_WIN_EN_SHIFT 0 71 #define RK3568_VP0_LINE_FLAG 0x70 72 #define RK3568_VP1_LINE_FLAG 0x74 73 #define RK3568_VP2_LINE_FLAG 0x78 74 #define RK3568_SYS0_INT_EN 0x80 75 #define RK3568_SYS0_INT_CLR 0x84 76 #define RK3568_SYS0_INT_STATUS 0x88 77 #define RK3568_SYS1_INT_EN 0x90 78 #define RK3568_SYS1_INT_CLR 0x94 79 #define RK3568_SYS1_INT_STATUS 0x98 80 #define RK3568_VP0_INT_EN 0xA0 81 #define RK3568_VP0_INT_CLR 0xA4 82 #define RK3568_VP0_INT_STATUS 0xA8 83 #define RK3568_VP1_INT_EN 0xB0 84 #define RK3568_VP1_INT_CLR 0xB4 85 #define RK3568_VP1_INT_STATUS 0xB8 86 #define RK3568_VP2_INT_EN 0xC0 87 #define RK3568_VP2_INT_CLR 0xC4 88 #define RK3568_VP2_INT_STATUS 0xC8 89 90 /* Video Port registers definition */ 91 #define RK3568_VP0_DSP_CTRL 0xC00 92 #define OUT_MODE_MASK 0xf 93 #define OUT_MODE_SHIFT 0 94 #define DATA_SWAP_MASK 0x1f 95 #define DATA_SWAP_SHIFT 8 96 #define DSP_RB_SWAP 2 97 #define CORE_DCLK_DIV_EN_SHIFT 4 98 #define P2I_EN_SHIFT 5 99 #define INTERLACE_EN_SHIFT 7 100 #define POST_DSP_OUT_R2Y_SHIFT 15 101 #define PRE_DITHER_DOWN_EN_SHIFT 16 102 #define DITHER_DOWN_EN_SHIFT 17 103 #define STANDBY_EN_SHIFT 31 104 105 #define RK3568_VP0_MIPI_CTRL 0xC04 106 #define DCLK_DIV2_SHIFT 4 107 #define DCLK_DIV2_MASK 0x3 108 #define MIPI_DUAL_EN_SHIFT 20 109 #define MIPI_DUAL_SWAP_EN_SHIFT 21 110 111 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 112 #define RK3568_VP0_DSP_BG 0xC2C 113 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 114 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 115 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 116 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C 117 #define RK3568_VP0_POST_SCL_CTRL 0xC40 118 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 119 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 120 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C 121 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 122 #define RK3568_VP0_DSP_VACT_ST_END 0xC54 123 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 124 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C 125 126 #define RK3568_VP1_DSP_CTRL 0xD00 127 #define RK3568_VP1_MIPI_CTRL 0xD04 128 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 129 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 130 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 131 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 132 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C 133 #define RK3568_VP1_POST_SCL_CTRL 0xD40 134 #define RK3568_VP1_DSP_HACT_INFO 0xD34 135 #define RK3568_VP1_DSP_VACT_INFO 0xD38 136 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 137 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 138 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C 139 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 140 #define RK3568_VP1_DSP_VACT_ST_END 0xD54 141 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 142 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C 143 144 #define RK3568_VP2_DSP_CTRL 0xE00 145 #define RK3568_VP2_MIPI_CTRL 0xE04 146 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 147 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 148 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 149 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 150 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C 151 #define RK3568_VP2_POST_SCL_CTRL 0xE40 152 #define RK3568_VP2_DSP_HACT_INFO 0xE34 153 #define RK3568_VP2_DSP_VACT_INFO 0xE38 154 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 155 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 156 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C 157 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 158 #define RK3568_VP2_DSP_VACT_ST_END 0xE54 159 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 160 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C 161 162 /* Overlay registers definition */ 163 #define RK3568_OVL_CTRL 0x600 164 #define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28 165 #define RK3568_OVL_LAYER_SEL 0x604 166 #define LAYER_SEL_MASK 0xf 167 168 #define RK3568_OVL_PORT_SEL 0x608 169 #define PORT_MUX_MASK 0xf 170 #define PORT_MUX_SHIFT 0 171 #define LAYER_SEL_PORT_MASK 0x3 172 #define LAYER_SEL_PORT_SHIFT 24 173 174 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 175 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 176 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 177 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 178 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 179 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 180 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 181 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 182 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 183 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 184 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 185 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 186 #define RK3568_VP0_BG_MIX_CTRL 0x6E0 187 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 188 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 189 #define RK3568_CLUSTER_DLY_NUM 0x6F0 190 #define RK3568_SMART_DLY_NUM 0x6F8 191 192 /* Cluster0 register definition */ 193 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 194 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 195 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 196 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 197 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 198 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 199 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 200 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 201 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 202 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 203 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 204 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C 205 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 206 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 207 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 208 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C 209 210 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 211 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 212 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 213 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 214 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 215 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 216 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 217 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 218 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 219 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 220 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 221 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC 222 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 223 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 224 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 225 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC 226 227 #define RK3568_CLUSTER0_CTRL 0x1100 228 229 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 230 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 231 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 232 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 233 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 234 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 235 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 236 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 237 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 238 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 239 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 240 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C 241 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 242 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 243 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 244 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C 245 246 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 247 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 248 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 249 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 250 #define RK3568_CLUSTER1_WIN1_VIR 0x1298 251 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 252 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 253 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 254 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 255 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 256 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 257 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC 258 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 259 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 260 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 261 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC 262 263 #define RK3568_CLUSTER1_CTRL 0x1300 264 265 /* Esmart register definition */ 266 #define RK3568_ESMART0_CTRL0 0x1800 267 #define RGB2YUV_EN_SHIFT 1 268 #define CSC_MODE_SHIFT 2 269 #define CSC_MODE_MASK 0x3 270 271 #define RK3568_ESMART0_CTRL1 0x1804 272 #define YMIRROR_EN_SHIFT 31 273 #define RK3568_ESMART0_REGION0_CTRL 0x1810 274 #define REGION0_RB_SWAP_SHIFT 14 275 #define WIN_EN_SHIFT 0 276 #define WIN_FORMAT_MASK 0x1f 277 #define WIN_FORMAT_SHIFT 1 278 279 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 280 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 281 #define RK3568_ESMART0_REGION0_VIR 0x181C 282 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 283 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 284 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828 285 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 286 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 287 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 288 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C 289 #define RK3568_ESMART0_REGION1_CTRL 0x1840 290 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 291 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848 292 #define RK3568_ESMART0_REGION1_VIR 0x184C 293 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 294 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 295 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858 296 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 297 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 298 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 299 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C 300 #define RK3568_ESMART0_REGION2_CTRL 0x1870 301 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 302 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878 303 #define RK3568_ESMART0_REGION2_VIR 0x187C 304 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 305 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 306 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888 307 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 308 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 309 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 310 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C 311 #define RK3568_ESMART0_REGION3_CTRL 0x18A0 312 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 313 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 314 #define RK3568_ESMART0_REGION3_VIR 0x18AC 315 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 316 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 317 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 318 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 319 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 320 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 321 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC 322 323 #define RK3568_ESMART1_CTRL0 0x1A00 324 #define RK3568_ESMART1_CTRL1 0x1A04 325 #define RK3568_ESMART1_REGION0_CTRL 0x1A10 326 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 327 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 328 #define RK3568_ESMART1_REGION0_VIR 0x1A1C 329 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 330 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 331 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 332 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 333 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 334 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 335 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C 336 #define RK3568_ESMART1_REGION1_CTRL 0x1A40 337 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 338 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 339 #define RK3568_ESMART1_REGION1_VIR 0x1A4C 340 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 341 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 342 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 343 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 344 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 345 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 346 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C 347 #define RK3568_ESMART1_REGION2_CTRL 0x1A70 348 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 349 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 350 #define RK3568_ESMART1_REGION2_VIR 0x1A7C 351 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 352 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 353 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 354 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 355 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 356 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 357 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C 358 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0 359 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 360 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 361 #define RK3568_ESMART1_REGION3_VIR 0x1AAC 362 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 363 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 364 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 365 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 366 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 367 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 368 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC 369 370 #define RK3568_SMART0_CTRL0 0x1C00 371 #define RK3568_SMART0_CTRL1 0x1C04 372 #define RK3568_SMART0_REGION0_CTRL 0x1C10 373 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 374 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18 375 #define RK3568_SMART0_REGION0_VIR 0x1C1C 376 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 377 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 378 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28 379 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 380 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 381 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 382 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C 383 #define RK3568_SMART0_REGION1_CTRL 0x1C40 384 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 385 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48 386 #define RK3568_SMART0_REGION1_VIR 0x1C4C 387 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 388 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 389 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58 390 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 391 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 392 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 393 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C 394 #define RK3568_SMART0_REGION2_CTRL 0x1C70 395 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 396 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78 397 #define RK3568_SMART0_REGION2_VIR 0x1C7C 398 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 399 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 400 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88 401 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 402 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 403 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 404 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C 405 #define RK3568_SMART0_REGION3_CTRL 0x1CA0 406 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 407 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 408 #define RK3568_SMART0_REGION3_VIR 0x1CAC 409 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 410 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 411 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 412 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 413 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 414 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 415 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC 416 417 #define RK3568_SMART1_CTRL0 0x1E00 418 #define RK3568_SMART1_CTRL1 0x1E04 419 #define RK3568_SMART1_REGION0_CTRL 0x1E10 420 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 421 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18 422 #define RK3568_SMART1_REGION0_VIR 0x1E1C 423 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 424 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 425 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28 426 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 427 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 428 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 429 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C 430 #define RK3568_SMART1_REGION1_CTRL 0x1E40 431 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 432 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48 433 #define RK3568_SMART1_REGION1_VIR 0x1E4C 434 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 435 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 436 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58 437 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 438 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 439 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 440 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C 441 #define RK3568_SMART1_REGION2_CTRL 0x1E70 442 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 443 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78 444 #define RK3568_SMART1_REGION2_VIR 0x1E7C 445 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 446 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 447 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88 448 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 449 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 450 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 451 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C 452 #define RK3568_SMART1_REGION3_CTRL 0x1EA0 453 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 454 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 455 #define RK3568_SMART1_REGION3_VIR 0x1EAC 456 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 457 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 458 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 459 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 460 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 461 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 462 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC 463 464 #define RK3568_MAX_REG 0x1ED0 465 466 #define RK3568_GRF_VO_CON1 0x0364 467 #define GRF_BT656_CLK_INV_SHIFT 1 468 #define GRF_BT1120_CLK_INV_SHIFT 2 469 #define GRF_RGB_DCLK_INV_SHIFT 3 470 471 #define VOP2_LAYER_MAX 8 472 #define VOP2_MAX_VP 4 473 474 enum vop2_csc_format { 475 CSC_BT601L, 476 CSC_BT709L, 477 CSC_BT601F, 478 CSC_BT2020, 479 }; 480 481 enum vop2_pol { 482 HSYNC_POSITIVE = 0, 483 VSYNC_POSITIVE = 1, 484 DEN_NEGATIVE = 2, 485 DCLK_INVERT = 3 486 }; 487 488 #define _VOP_REG(off, _mask, _shift, _write_mask) \ 489 { \ 490 .offset = off, \ 491 .mask = _mask, \ 492 .shift = _shift, \ 493 .write_mask = _write_mask, \ 494 } 495 496 #define VOP_REG(off, _mask, _shift) \ 497 _VOP_REG(off, _mask, _shift, false) 498 enum dither_down_mode { 499 RGB888_TO_RGB565 = 0x0, 500 RGB888_TO_RGB666 = 0x1 501 }; 502 503 enum vop2_video_ports_id { 504 VOP2_VP0, 505 VOP2_VP1, 506 VOP2_VP2, 507 VOP2_VP3, 508 VOP2_VP_MAX, 509 }; 510 511 struct vop2_layer { 512 uint8_t id; 513 /** 514 * @win_phys_id: window id of the layer selected. 515 * Every layer must make sure to select different 516 * windows of others. 517 */ 518 uint8_t win_phys_id; 519 }; 520 521 struct vop2_win { 522 uint8_t id; 523 uint8_t layer_id; 524 uint8_t phys_id; 525 }; 526 527 struct vop2_data { 528 u32 version; 529 struct vop_rect max_output[VOP2_MAX_VP]; 530 /** 531 * win_id: id of window attach to VP0,VP1,VP2,VP3, 532 * Only support one window for one VP in u-boot. 533 * 534 */ 535 uint8_t win_id[VOP2_MAX_VP]; 536 uint8_t nr_vps; 537 uint8_t nr_layers; 538 /** 539 * win_sel_id: from register LAYER_SEL 540 * 541 */ 542 uint8_t win_sel_id[VOP2_LAYER_MAX]; 543 }; 544 545 struct vop2 { 546 u32 *regsbak; 547 void *regs; 548 void *grf; 549 u32 reg_len; 550 u32 version; 551 const struct vop2_data *data; 552 /** 553 * @nr_wins: active wins attached to the video port 554 */ 555 uint8_t nr_wins[VOP2_VP_MAX]; 556 struct vop2_win win[VOP2_LAYER_MAX]; 557 struct vop2_layer layer[VOP2_LAYER_MAX]; 558 }; 559 560 static struct vop2 *rockchip_vop2; 561 static void vop2_setup_win_for_vp(struct display_state *state); 562 563 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 564 { 565 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 566 } 567 568 static inline uint16_t scl_cal_scale2(int src, int dst) 569 { 570 return ((src - 1) << 12) / (dst - 1); 571 } 572 573 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 574 { 575 writel(v, vop2->regs + offset); 576 vop2->regsbak[offset >> 2] = v; 577 } 578 579 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) 580 { 581 return readl(vop2->regs + offset); 582 } 583 584 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, 585 u32 mask, u32 shift, u32 v, 586 bool write_mask) 587 { 588 if (!mask) 589 return; 590 591 if (write_mask) { 592 v = ((v & mask) << shift) | (mask << (shift + 16)); 593 } else { 594 u32 cached_val = vop2->regsbak[offset >> 2]; 595 596 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 597 vop2->regsbak[offset >> 2] = v; 598 } 599 600 writel(v, vop2->regs + offset); 601 } 602 603 static inline void vop2_grf_writel(struct vop2 *vop, u32 offset, 604 u32 mask, u32 shift, u32 v) 605 { 606 u32 val = 0; 607 608 val = (v << shift) | (mask << (shift + 16)); 609 writel(val, vop->grf + offset); 610 } 611 612 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 613 { 614 return us * mode->clock / mode->htotal / 1000; 615 } 616 617 static bool is_yuv_output(u32 bus_format) 618 { 619 switch (bus_format) { 620 case MEDIA_BUS_FMT_YUV8_1X24: 621 case MEDIA_BUS_FMT_YUV10_1X30: 622 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 623 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 624 return true; 625 default: 626 return false; 627 } 628 } 629 630 static int vop2_convert_csc_mode(int csc_mode) 631 { 632 switch (csc_mode) { 633 case V4L2_COLORSPACE_SMPTE170M: 634 case V4L2_COLORSPACE_470_SYSTEM_M: 635 case V4L2_COLORSPACE_470_SYSTEM_BG: 636 return CSC_BT601L; 637 case V4L2_COLORSPACE_REC709: 638 case V4L2_COLORSPACE_SMPTE240M: 639 case V4L2_COLORSPACE_DEFAULT: 640 return CSC_BT709L; 641 case V4L2_COLORSPACE_JPEG: 642 return CSC_BT601F; 643 case V4L2_COLORSPACE_BT2020: 644 return CSC_BT2020; 645 default: 646 return CSC_BT709L; 647 } 648 } 649 650 static __maybe_unused bool is_uv_swap(u32 bus_format, u32 output_mode) 651 { 652 /* 653 * FIXME: 654 * 655 * There is no media type for YUV444 output, 656 * so when out_mode is AAAA or P888, assume output is YUV444 on 657 * yuv format. 658 * 659 * From H/W testing, YUV444 mode need a rb swap. 660 */ 661 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 662 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 663 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 664 output_mode == ROCKCHIP_OUT_MODE_P888)) 665 return true; 666 else 667 return false; 668 } 669 670 static int rockchip_vop2_init_gamma(struct vop2 *vop2, 671 struct display_state *state) 672 { 673 return 0; 674 } 675 676 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) 677 { 678 struct connector_state *conn_state = &state->conn_state; 679 struct drm_display_mode *mode = &conn_state->mode; 680 struct crtc_state *cstate = &state->crtc_state; 681 u32 vp_offset = (cstate->crtc_id * 0x100); 682 u16 vtotal = mode->crtc_vtotal; 683 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 684 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 685 u16 hdisplay = mode->crtc_hdisplay; 686 u16 vdisplay = mode->crtc_vdisplay; 687 u16 hsize = 688 hdisplay * (conn_state->overscan.left_margin + 689 conn_state->overscan.right_margin) / 200; 690 u16 vsize = 691 vdisplay * (conn_state->overscan.top_margin + 692 conn_state->overscan.bottom_margin) / 200; 693 u16 hact_end, vact_end; 694 u32 val; 695 u16 nr_mixers = 5, used_layer = 2, pre_scan_max_dly; 696 u32 bg_ovl_dly, bg_dly, pre_scan_dly; 697 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 698 699 if (cstate->crtc_id == 0) 700 pre_scan_max_dly = 69; 701 else 702 pre_scan_max_dly = 40; 703 704 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 705 vsize = round_down(vsize, 2); 706 707 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 708 hact_end = hact_st + hsize; 709 val = hact_st << 16; 710 val |= hact_end; 711 712 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); 713 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 714 vact_end = vact_st + vsize; 715 val = vact_st << 16; 716 val |= vact_end; 717 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); 718 val = scl_cal_scale2(vdisplay, vsize) << 16; 719 val |= scl_cal_scale2(hdisplay, hsize); 720 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); 721 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 722 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 723 vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, 724 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 725 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 726 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 727 u16 vact_st_f1 = vtotal + vact_st + 1; 728 u16 vact_end_f1 = vact_st_f1 + vsize; 729 730 val = vact_st_f1 << 16 | vact_end_f1; 731 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); 732 } 733 734 bg_ovl_dly = (nr_mixers - used_layer) << 1; 735 bg_dly = pre_scan_max_dly - bg_ovl_dly; 736 pre_scan_dly = bg_dly + (hdisplay >> 1) - 1; 737 pre_scan_dly = (pre_scan_dly << 16) | hsync_len; 738 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + vp_offset, pre_scan_dly); 739 } 740 741 static void vop2_layer_map_initial(struct vop2 *vop2) 742 { 743 struct vop2_layer *layer; 744 struct vop2_win *win; 745 u32 layer_map, sel; 746 int i, j; 747 748 layer_map = vop2_readl(vop2, RK3568_OVL_LAYER_SEL); 749 750 for (i = 0; i < vop2->data->nr_layers; i++) { 751 sel = (layer_map >> (4 * i)) & 0xf; 752 layer = &vop2->layer[i]; 753 win = NULL; 754 for (j = 0; j < vop2->data->nr_layers; j++) { 755 if (sel == vop2->data->win_sel_id[j]) { 756 win = &vop2->win[j]; 757 break; 758 } 759 } 760 761 if (!win) { 762 printf("invalid layer map :0x%x\n", layer_map); 763 return; 764 } 765 766 layer->win_phys_id = j; 767 win->layer_id = i; 768 debug("layer%d select %d\n", i, j); 769 } 770 } 771 772 static int vop2_initial(struct vop2 *vop2, struct display_state *state) 773 { 774 struct crtc_state *cstate = &state->crtc_state; 775 struct connector_state *conn_state = &state->conn_state; 776 struct drm_display_mode *mode = &conn_state->mode; 777 char dclk_name[9]; 778 struct clk dclk; 779 uint8_t shift = 0; 780 int i, ret; 781 782 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 783 ret = clk_set_defaults(cstate->dev); 784 if (ret) 785 debug("%s clk_set_defaults failed %d\n", __func__, ret); 786 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); 787 ret = clk_get_by_name(cstate->dev, dclk_name, &dclk); 788 if (!ret) 789 ret = clk_set_rate(&dclk, mode->clock * 1000); 790 791 if (IS_ERR_VALUE(ret)) { 792 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 793 return ret; 794 } 795 796 if (soc_is_rk3566()) 797 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, 798 OTP_WIN_EN_SHIFT, 1, false); 799 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); 800 801 rockchip_vop2_init_gamma(vop2, state); 802 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, 803 OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); 804 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 805 IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); 806 for (i = 0; i < vop2->data->nr_vps - 1; i++) { 807 shift = i * 4; 808 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, PORT_MUX_SHIFT + shift, 8, false); //todo 809 } 810 811 vop2_layer_map_initial(vop2); 812 813 return 0; 814 } 815 816 /* 817 * VOP2 have multi video ports. 818 * video port ------- crtc 819 */ 820 static int rockchip_vop2_preinit(struct display_state *state) 821 { 822 struct crtc_state *cstate = &state->crtc_state; 823 const struct vop2_data *vop2_data = cstate->crtc->data; 824 825 if (!rockchip_vop2) { 826 rockchip_vop2 = malloc(sizeof(struct vop2)); 827 if (!rockchip_vop2) 828 return -ENOMEM; 829 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); 830 rockchip_vop2->regsbak = malloc(RK3568_MAX_REG); 831 rockchip_vop2->reg_len = RK3568_MAX_REG; 832 rockchip_vop2->grf = 833 syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 834 if (rockchip_vop2->grf <= 0) 835 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, 836 rockchip_vop2->grf); 837 838 rockchip_vop2->version = vop2_data->version; 839 rockchip_vop2->data = vop2_data; 840 } 841 842 cstate->private = rockchip_vop2; 843 cstate->max_output = vop2_data->max_output[cstate->crtc_id]; 844 845 return 0; 846 } 847 848 static int rockchip_vop2_init(struct display_state *state) 849 { 850 struct crtc_state *cstate = &state->crtc_state; 851 struct connector_state *conn_state = &state->conn_state; 852 struct drm_display_mode *mode = &conn_state->mode; 853 //const struct rockchip_crtc *crtc = cstate->crtc; 854 //const struct vop2_data *vop2_data = crtc->data; 855 struct vop2 *vop2 = cstate->private; 856 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 857 u16 hdisplay = mode->crtc_hdisplay; 858 u16 htotal = mode->crtc_htotal; 859 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 860 u16 hact_end = hact_st + hdisplay; 861 u16 vdisplay = mode->crtc_vdisplay; 862 u16 vtotal = mode->crtc_vtotal; 863 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 864 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 865 u16 vact_end = vact_st + vdisplay; 866 bool yuv_overlay = false; 867 //bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 868 u32 vp_offset = (cstate->crtc_id * 0x100); 869 //struct clk dclk; 870 //fdt_size_t len; 871 u32 val; 872 //int ret; 873 bool dclk_inv; 874 uint8_t dither_down_en = 0; 875 uint8_t pre_dither_down_en = 0; 876 //uint8_t dither_down_mode = RGB888_TO_RGB666; 877 878 vop2_initial(vop2, state); 879 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 880 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 881 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 882 883 if (conn_state->output_if & VOP_OUTPUT_IF_RGB) { 884 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 885 1, false); 886 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 887 RGB_MUX_SHIFT, cstate->crtc_id, false); 888 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 889 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, !!dclk_inv, 890 false); 891 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 892 GRF_RGB_DCLK_INV_SHIFT, !dclk_inv); 893 } 894 895 if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) { 896 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 897 1, false); 898 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, 899 BT1120_EN_SHIFT, 1, false); 900 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 901 RGB_MUX_SHIFT, cstate->crtc_id, false); 902 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 903 GRF_BT1120_CLK_INV_SHIFT, !dclk_inv); 904 } 905 906 if (conn_state->output_if & VOP_OUTPUT_IF_BT656) { 907 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, 908 1, false); 909 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 910 RGB_MUX_SHIFT, cstate->crtc_id, false); 911 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 912 GRF_BT656_CLK_INV_SHIFT, !dclk_inv); 913 } 914 915 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) { 916 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, 917 1, false); 918 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 919 LVDS0_MUX_SHIFT, cstate->crtc_id, false); 920 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 921 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 922 } 923 924 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) { 925 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, 926 1, false); 927 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 928 LVDS1_MUX_SHIFT, cstate->crtc_id, false); 929 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 930 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 931 } 932 933 if (conn_state->output_flags & 934 (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE | 935 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) { 936 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 937 LVDS_DUAL_EN_SHIFT, 1, false); 938 if (conn_state->output_flags & 939 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 940 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 941 LVDS_DUAL_LEFT_RIGHT_EN_SHIFT, 1, 942 false); 943 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 944 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 945 LVDS_DUAL_SWAP_EN_SHIFT, 1, false); 946 } 947 948 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) { 949 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, 950 1, false); 951 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 952 MIPI0_MUX_SHIFT, cstate->crtc_id, false); 953 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 954 IF_CRTL_MIPI_DCLK_POL_SHIT, ! !dclk_inv, false); 955 } 956 957 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI1) { 958 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, 959 1, false); 960 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 961 MIPI1_MUX_SHIFT, cstate->crtc_id, false); 962 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 963 IF_CRTL_MIPI_DCLK_POL_SHIT, ! !dclk_inv, false); 964 } 965 966 if (conn_state->output_flags & 967 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 968 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 969 MIPI_DUAL_EN_SHIFT, 1, false); 970 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 971 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 972 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 973 false); 974 } 975 976 if (conn_state->output_if & VOP_OUTPUT_IF_eDP0) { 977 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, 978 1, false); 979 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 980 EDP0_MUX_SHIFT, cstate->crtc_id, false); 981 } 982 983 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) { 984 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, 985 1, false); 986 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 987 HDMI0_MUX_SHIFT, cstate->crtc_id, false); 988 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 989 IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false); 990 vop2_mask_write(vop2, RK3568_DSP_IF_POL, 991 IF_CRTL_HDMI_PIN_POL_MASK, 992 IF_CRTL_HDMI_PIN_POL_SHIT, val, false); 993 } 994 995 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && cstate->crtc_id != 0) 996 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 997 998 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 999 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1000 DATA_SWAP_MASK, DATA_SWAP_SHIFT, DSP_RB_SWAP, 1001 false); 1002 else 1003 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1004 DATA_SWAP_MASK, DATA_SWAP_SHIFT, 0, 1005 false); 1006 1007 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, 1008 OUT_MODE_SHIFT, conn_state->output_mode, false); 1009 1010 switch (conn_state->bus_format) { 1011 case MEDIA_BUS_FMT_RGB565_1X16: 1012 dither_down_en = 1; 1013 break; 1014 case MEDIA_BUS_FMT_RGB666_1X18: 1015 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 1016 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 1017 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 1018 dither_down_en = 1; 1019 break; 1020 case MEDIA_BUS_FMT_YUV8_1X24: 1021 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1022 dither_down_en = 0; 1023 pre_dither_down_en = 1; 1024 break; 1025 case MEDIA_BUS_FMT_YUV10_1X30: 1026 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1027 case MEDIA_BUS_FMT_RGB888_1X24: 1028 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 1029 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 1030 default: 1031 dither_down_en = 0; 1032 pre_dither_down_en = 0; 1033 break; 1034 } 1035 1036 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 1037 pre_dither_down_en = 0; 1038 else 1039 pre_dither_down_en = 1; 1040 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1041 DITHER_DOWN_EN_SHIFT, dither_down_en, false); 1042 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1043 PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false); 1044 1045 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0; 1046 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, 1047 yuv_overlay, false); 1048 1049 cstate->yuv_overlay = yuv_overlay; 1050 1051 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, 1052 (htotal << 16) | hsync_len); 1053 val = hact_st << 16; 1054 val |= hact_end; 1055 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); 1056 val = vact_st << 16; 1057 val |= vact_end; 1058 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); 1059 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1060 u16 vact_st_f1 = vtotal + vact_st + 1; 1061 u16 vact_end_f1 = vact_st_f1 + vdisplay; 1062 1063 val = vact_st_f1 << 16 | vact_end_f1; 1064 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, 1065 val); 1066 1067 val = vtotal << 16 | (vtotal + vsync_len); 1068 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); 1069 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1070 INTERLACE_EN_SHIFT, 1, false); 1071 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1072 P2I_EN_SHIFT, 1, false); 1073 vtotal += vtotal + 1; 1074 } else { 1075 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1076 INTERLACE_EN_SHIFT, 0, false); 1077 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1078 P2I_EN_SHIFT, 0, false); 1079 } 1080 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, 1081 (vtotal << 16) | vsync_len); 1082 val = ! !(mode->flags & DRM_MODE_FLAG_DBLCLK); 1083 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1084 CORE_DCLK_DIV_EN_SHIFT, val, false); 1085 1086 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) 1087 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, DCLK_DIV2_MASK, 1088 DCLK_DIV2_SHIFT, 0x3, false); 1089 else 1090 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, DCLK_DIV2_MASK, 1091 DCLK_DIV2_SHIFT, 0, false); 1092 1093 if (yuv_overlay) 1094 val = 0x20010200; 1095 else 1096 val = 0; 1097 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); 1098 1099 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1100 POST_DSP_OUT_R2Y_SHIFT, yuv_overlay, false); 1101 1102 vop2_post_config(state, vop2); 1103 vop2_setup_win_for_vp(state); 1104 1105 return 0; 1106 } 1107 1108 static void vop2_setup_win_for_vp(struct display_state *state) 1109 { 1110 struct crtc_state *cstate = &state->crtc_state; 1111 const struct rockchip_crtc *crtc = cstate->crtc; 1112 const struct vop2_data *vop2_data = crtc->data; 1113 struct vop2 *vop2 = cstate->private; 1114 u8 port_id = cstate->crtc_id; 1115 struct vop2_win *win; 1116 struct vop2_layer *layer; 1117 u8 used_layers = 0; 1118 u8 layer_id, win_phys_id, win_sel_id; 1119 u8 shift; 1120 int i; 1121 1122 for (i = 0; i < port_id; i++) 1123 used_layers += vop2->nr_wins[i]; 1124 1125 vop2->nr_wins[port_id]++; 1126 /* 1127 * Win and layer must map one by one, if a win is selected 1128 * by two layers, unexpected error may happen. 1129 * So when we attach a new win to a layer, we also move the 1130 * old win of the layer to the layer where the new win comes from. 1131 * 1132 */ 1133 layer = &vop2->layer[used_layers]; 1134 win = &vop2->win[port_id]; 1135 shift = port_id * 2; 1136 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, 1137 LAYER_SEL_PORT_SHIFT + shift, port_id, false); 1138 shift = used_layers * 4; 1139 win_phys_id = vop2->data->win_id[port_id]; 1140 win_sel_id = vop2->data->win_sel_id[win_phys_id]; 1141 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_PORT_MASK, shift, 1142 win_sel_id, false); 1143 layer_id = win->layer_id; 1144 win_phys_id = layer->win_phys_id; 1145 win->layer_id = layer->id; 1146 layer->win_phys_id = win->phys_id; 1147 layer = &vop2->layer[layer_id]; 1148 win = &vop2->win[win_phys_id]; 1149 shift = layer_id * 4; 1150 win_sel_id = vop2->data->win_sel_id[win_phys_id]; 1151 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_PORT_MASK, shift, 1152 win_sel_id, false); 1153 win->layer_id = layer_id; 1154 layer->win_phys_id = win_phys_id; 1155 1156 if (port_id == (vop2_data->nr_vps - 1)) 1157 used_layers = vop2_data->nr_layers; 1158 shift = port_id * 4; 1159 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, shift, 1160 used_layers, false); 1161 1162 if (port_id == 0) { 1163 vop2_writel(vop2, 0x604, 0x54760123); 1164 vop2_writel(vop2, 0x608, 0x00000755); 1165 vop2_writel(vop2, 0x6e0, 0x2a000000); 1166 } else { 1167 vop2_writel(vop2, 0x604, 0x54760312); 1168 vop2_writel(vop2, 0x608, 0x55050728); 1169 vop2_writel(vop2, 0x6e4, 0x1e000000); 1170 } 1171 } 1172 1173 static int rockchip_vop2_set_plane(struct display_state *state) 1174 { 1175 struct crtc_state *cstate = &state->crtc_state; 1176 struct connector_state *conn_state = &state->conn_state; 1177 struct drm_display_mode *mode = &conn_state->mode; 1178 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 1179 struct vop2 *vop2 = cstate->private; 1180 int src_w = cstate->src_w; 1181 int src_h = cstate->src_h; 1182 int crtc_x = cstate->crtc_x; 1183 int crtc_y = cstate->crtc_y; 1184 int crtc_w = cstate->crtc_w; 1185 int crtc_h = cstate->crtc_h; 1186 int xvir = cstate->xvir; 1187 int y_mirror = 0; 1188 int csc_mode; 1189 u32 win_offset; 1190 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1191 1192 if (cstate->crtc_id == 1) 1193 win_offset = 0x400; /* port 1 use smart0*/ 1194 else 1195 win_offset = 0; /* port 0 use esmart0*/ 1196 1197 if (crtc_w > cstate->max_output.width) { 1198 printf("ERROR: output w[%d] exceeded max width[%d]\n", 1199 crtc_w, cstate->max_output.width); 1200 return -EINVAL; 1201 } 1202 1203 act_info = (src_h - 1) << 16; 1204 act_info |= (src_w - 1) & 0xffff; 1205 1206 dsp_info = (crtc_h - 1) << 16; 1207 dsp_info |= (crtc_w - 1) & 0xffff; 1208 1209 dsp_stx = crtc_x; 1210 dsp_sty = crtc_y; 1211 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 1212 1213 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 1214 y_mirror = 1; 1215 else 1216 y_mirror = 0; 1217 1218 if (y_mirror) 1219 cstate->dma_addr += (src_h - 1) * xvir * 4; 1220 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, 1221 YMIRROR_EN_SHIFT, y_mirror, false); 1222 1223 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 1224 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 1225 false); 1226 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); 1227 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, 1228 cstate->dma_addr); 1229 1230 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, 1231 act_info); 1232 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, 1233 dsp_info); 1234 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); 1235 1236 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, 1237 WIN_EN_SHIFT, 1, false); 1238 1239 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1240 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, 1241 RGB2YUV_EN_SHIFT, 1242 is_yuv_output(conn_state->bus_format), false); 1243 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, 1244 CSC_MODE_SHIFT, csc_mode, false); 1245 1246 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1247 return 0; 1248 } 1249 1250 static int rockchip_vop2_prepare(struct display_state *state) 1251 { 1252 return 0; 1253 } 1254 1255 static int rockchip_vop2_enable(struct display_state *state) 1256 { 1257 struct crtc_state *cstate = &state->crtc_state; 1258 struct vop2 *vop2 = cstate->private; 1259 u32 vp_offset = (cstate->crtc_id * 0x100); 1260 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1261 1262 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1263 STANDBY_EN_SHIFT, 0, false); 1264 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1265 1266 return 0; 1267 } 1268 1269 static int rockchip_vop2_disable(struct display_state *state) 1270 { 1271 struct crtc_state *cstate = &state->crtc_state; 1272 struct vop2 *vop2 = cstate->private; 1273 u32 vp_offset = (cstate->crtc_id * 0x100); 1274 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1275 1276 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1277 STANDBY_EN_SHIFT, 1, false); 1278 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1279 1280 return 0; 1281 } 1282 1283 const struct vop2_data rk3568_vop = { 1284 .nr_vps = 3, 1285 .max_output = { 1286 [VOP2_VP0] = {4096, 2304}, 1287 [VOP2_VP1] = {2048, 1536}, 1288 [VOP2_VP2] = {1920, 1080}, 1289 }, 1290 1291 /* 1292 * Cluster0-Win0: 0 1293 * Cluster1-Win0: 1 1294 * Esmart0-Win0: 2 1295 * Esmart1-Win0: 3 1296 * Smart0-Win0: 4 1297 * Smart1-Win0: 5 1298 */ 1299 .win_id = { 1300 [VOP2_VP0] = 2, 1301 [VOP2_VP1] = 3, 1302 [VOP2_VP2] = 4, 1303 }, 1304 1305 /** 1306 * Win select id: from register LAYER_SEL 1307 * 1308 * Cluster0-Win0: 0 1309 * Cluster1-Win0: 1 1310 * Esmart0-Win0: 2 1311 * Esmart1-Win0: 6 1312 * Smart0-Win0: 3 1313 * Smart1-Win0: 7 1314 */ 1315 .win_sel_id = {0, 1, 2, 6, 3, 7}, 1316 .nr_layers = 6, 1317 }; 1318 1319 const struct rockchip_crtc_funcs rockchip_vop2_funcs = { 1320 .preinit = rockchip_vop2_preinit, 1321 .prepare = rockchip_vop2_prepare, 1322 .init = rockchip_vop2_init, 1323 .set_plane = rockchip_vop2_set_plane, 1324 .enable = rockchip_vop2_enable, 1325 .disable = rockchip_vop2_disable, 1326 }; 1327