1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <regmap.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/unaligned.h> 16 #include <asm/io.h> 17 #include <linux/list.h> 18 #include <linux/log2.h> 19 #include <linux/media-bus-format.h> 20 #include <clk.h> 21 #include <asm/arch/clock.h> 22 #include <linux/err.h> 23 #include <linux/ioport.h> 24 #include <dm/device.h> 25 #include <dm/read.h> 26 #include <fixp-arith.h> 27 #include <syscon.h> 28 #include <linux/iopoll.h> 29 #include <dm/uclass-internal.h> 30 31 #include "rockchip_display.h" 32 #include "rockchip_crtc.h" 33 #include "rockchip_connector.h" 34 35 /* System registers definition */ 36 #define RK3568_REG_CFG_DONE 0x000 37 #define CFG_DONE_EN BIT(15) 38 39 #define RK3568_VERSION_INFO 0x004 40 #define EN_MASK 1 41 42 #define RK3568_AUTO_GATING_CTRL 0x008 43 44 #define RK3568_SYS_AXI_LUT_CTRL 0x024 45 #define LUT_DMA_EN_SHIFT 0 46 47 #define RK3568_DSP_IF_EN 0x028 48 #define RGB_EN_SHIFT 0 49 #define RK3588_DP0_EN_SHIFT 0 50 #define RK3588_DP1_EN_SHIFT 1 51 #define RK3588_RGB_EN_SHIFT 8 52 #define HDMI0_EN_SHIFT 1 53 #define EDP0_EN_SHIFT 3 54 #define RK3588_EDP0_EN_SHIFT 2 55 #define RK3588_HDMI0_EN_SHIFT 3 56 #define MIPI0_EN_SHIFT 4 57 #define RK3588_EDP1_EN_SHIFT 4 58 #define RK3588_HDMI1_EN_SHIFT 5 59 #define RK3588_MIPI0_EN_SHIFT 6 60 #define MIPI1_EN_SHIFT 20 61 #define RK3588_MIPI1_EN_SHIFT 7 62 #define LVDS0_EN_SHIFT 5 63 #define LVDS1_EN_SHIFT 24 64 #define BT1120_EN_SHIFT 6 65 #define BT656_EN_SHIFT 7 66 #define IF_MUX_MASK 3 67 #define RGB_MUX_SHIFT 8 68 #define HDMI0_MUX_SHIFT 10 69 #define RK3588_DP0_MUX_SHIFT 12 70 #define RK3588_DP1_MUX_SHIFT 14 71 #define EDP0_MUX_SHIFT 14 72 #define RK3588_HDMI_EDP0_MUX_SHIFT 16 73 #define RK3588_HDMI_EDP1_MUX_SHIFT 18 74 #define MIPI0_MUX_SHIFT 16 75 #define RK3588_MIPI0_MUX_SHIFT 20 76 #define MIPI1_MUX_SHIFT 21 77 #define LVDS0_MUX_SHIFT 18 78 #define LVDS1_MUX_SHIFT 25 79 80 #define RK3568_DSP_IF_CTRL 0x02c 81 #define LVDS_DUAL_EN_SHIFT 0 82 #define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1 83 #define LVDS_DUAL_SWAP_EN_SHIFT 2 84 #define RK3588_HDMI_DUAL_EN_SHIFT 8 85 #define RK3588_EDP_DUAL_EN_SHIFT 8 86 #define RK3588_DP_DUAL_EN_SHIFT 9 87 #define RK3568_MIPI_DUAL_EN_SHIFT 10 88 #define RK3588_MIPI_DSI0_MODE_SEL_SHIFT 11 89 #define RK3588_MIPI_DSI1_MODE_SEL_SHIFT 12 90 91 #define RK3568_DSP_IF_POL 0x030 92 #define IF_CTRL_REG_DONE_IMD_MASK 1 93 #define IF_CTRL_REG_DONE_IMD_SHIFT 28 94 #define IF_CRTL_MIPI_DCLK_POL_SHIT 19 95 #define IF_CRTL_EDP_DCLK_POL_SHIT 15 96 #define IF_CRTL_HDMI_DCLK_POL_SHIT 7 97 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7 98 #define IF_CRTL_HDMI_PIN_POL_SHIT 4 99 100 #define RK3588_DP0_PIN_POL_SHIFT 8 101 #define RK3588_DP1_PIN_POL_SHIFT 12 102 #define RK3588_IF_PIN_POL_MASK 0x7 103 104 #define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3 105 106 #define HDMI_EDP0_DCLK_DIV_SHIFT 16 107 #define HDMI_EDP0_PIXCLK_DIV_SHIFT 18 108 #define HDMI_EDP1_DCLK_DIV_SHIFT 20 109 #define HDMI_EDP1_PIXCLK_DIV_SHIFT 22 110 #define MIPI0_PIXCLK_DIV_SHIFT 24 111 #define MIPI1_PIXCLK_DIV_SHIFT 26 112 113 #define RK3568_SYS_OTP_WIN_EN 0x50 114 #define OTP_WIN_EN_SHIFT 0 115 #define RK3568_SYS_LUT_PORT_SEL 0x58 116 #define GAMMA_PORT_SEL_MASK 0x3 117 #define GAMMA_PORT_SEL_SHIFT 0 118 #define PORT_MERGE_EN_SHIFT 16 119 120 #define RK3568_SYS_PD_CTRL 0x034 121 #define RK3568_VP0_LINE_FLAG 0x70 122 #define RK3568_VP1_LINE_FLAG 0x74 123 #define RK3568_VP2_LINE_FLAG 0x78 124 #define RK3568_SYS0_INT_EN 0x80 125 #define RK3568_SYS0_INT_CLR 0x84 126 #define RK3568_SYS0_INT_STATUS 0x88 127 #define RK3568_SYS1_INT_EN 0x90 128 #define RK3568_SYS1_INT_CLR 0x94 129 #define RK3568_SYS1_INT_STATUS 0x98 130 #define RK3568_VP0_INT_EN 0xA0 131 #define RK3568_VP0_INT_CLR 0xA4 132 #define RK3568_VP0_INT_STATUS 0xA8 133 #define RK3568_VP1_INT_EN 0xB0 134 #define RK3568_VP1_INT_CLR 0xB4 135 #define RK3568_VP1_INT_STATUS 0xB8 136 #define RK3568_VP2_INT_EN 0xC0 137 #define RK3568_VP2_INT_CLR 0xC4 138 #define RK3568_VP2_INT_STATUS 0xC8 139 #define RK3588_CLUSTER0_PD_EN_SHIFT 0 140 #define RK3588_CLUSTER1_PD_EN_SHIFT 1 141 #define RK3588_CLUSTER2_PD_EN_SHIFT 2 142 #define RK3588_CLUSTER3_PD_EN_SHIFT 3 143 #define RK3588_DSC_8K_PD_EN_SHIFT 5 144 #define RK3588_DSC_4K_PD_EN_SHIFT 6 145 #define RK3588_ESMART_PD_EN_SHIFT 7 146 147 #define RK3568_SYS_STATUS0 0x60 148 #define RK3588_CLUSTER0_PD_STATUS_SHIFT 8 149 #define RK3588_CLUSTER1_PD_STATUS_SHIFT 9 150 #define RK3588_CLUSTER2_PD_STATUS_SHIFT 10 151 #define RK3588_CLUSTER3_PD_STATUS_SHIFT 11 152 #define RK3588_DSC_8K_PD_STATUS_SHIFT 13 153 #define RK3588_DSC_4K_PD_STATUS_SHIFT 14 154 #define RK3588_ESMART_PD_STATUS_SHIFT 15 155 156 #define RK3568_SYS_CTRL_LINE_FLAG0 0x70 157 #define LINE_FLAG_NUM_MASK 0x1fff 158 #define RK3568_DSP_LINE_FLAG_NUM0_SHIFT 0 159 #define RK3568_DSP_LINE_FLAG_NUM1_SHIFT 16 160 161 /* DSC CTRL registers definition */ 162 #define RK3588_DSC_8K_SYS_CTRL 0x200 163 #define DSC_PORT_SEL_MASK 0x3 164 #define DSC_PORT_SEL_SHIFT 0 165 #define DSC_MAN_MODE_MASK 0x1 166 #define DSC_MAN_MODE_SHIFT 2 167 #define DSC_INTERFACE_MODE_MASK 0x3 168 #define DSC_INTERFACE_MODE_SHIFT 4 169 #define DSC_PIXEL_NUM_MASK 0x3 170 #define DSC_PIXEL_NUM_SHIFT 6 171 #define DSC_PXL_CLK_DIV_MASK 0x1 172 #define DSC_PXL_CLK_DIV_SHIFT 8 173 #define DSC_CDS_CLK_DIV_MASK 0x3 174 #define DSC_CDS_CLK_DIV_SHIFT 12 175 #define DSC_TXP_CLK_DIV_MASK 0x3 176 #define DSC_TXP_CLK_DIV_SHIFT 14 177 #define DSC_INIT_DLY_MODE_MASK 0x1 178 #define DSC_INIT_DLY_MODE_SHIFT 16 179 #define DSC_SCAN_EN_SHIFT 17 180 #define DSC_HALT_EN_SHIFT 18 181 182 #define RK3588_DSC_8K_RST 0x204 183 #define RST_DEASSERT_MASK 0x1 184 #define RST_DEASSERT_SHIFT 0 185 186 #define RK3588_DSC_8K_CFG_DONE 0x208 187 #define DSC_CFG_DONE_SHIFT 0 188 189 #define RK3588_DSC_8K_INIT_DLY 0x20C 190 #define DSC_INIT_DLY_NUM_MASK 0xffff 191 #define DSC_INIT_DLY_NUM_SHIFT 0 192 #define SCAN_TIMING_PARA_IMD_EN_SHIFT 16 193 194 #define RK3588_DSC_8K_HTOTAL_HS_END 0x210 195 #define DSC_HTOTAL_PW_MASK 0xffffffff 196 #define DSC_HTOTAL_PW_SHIFT 0 197 198 #define RK3588_DSC_8K_HACT_ST_END 0x214 199 #define DSC_HACT_ST_END_MASK 0xffffffff 200 #define DSC_HACT_ST_END_SHIFT 0 201 202 #define RK3588_DSC_8K_VTOTAL_VS_END 0x218 203 #define DSC_VTOTAL_PW_MASK 0xffffffff 204 #define DSC_VTOTAL_PW_SHIFT 0 205 206 #define RK3588_DSC_8K_VACT_ST_END 0x21C 207 #define DSC_VACT_ST_END_MASK 0xffffffff 208 #define DSC_VACT_ST_END_SHIFT 0 209 210 #define RK3588_DSC_8K_STATUS 0x220 211 212 /* Overlay registers definition */ 213 #define RK3568_OVL_CTRL 0x600 214 #define OVL_MODE_SEL_MASK 0x1 215 #define OVL_MODE_SEL_SHIFT 0 216 #define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28 217 #define RK3568_OVL_LAYER_SEL 0x604 218 #define LAYER_SEL_MASK 0xf 219 220 #define RK3568_OVL_PORT_SEL 0x608 221 #define PORT_MUX_MASK 0xf 222 #define PORT_MUX_SHIFT 0 223 #define LAYER_SEL_PORT_MASK 0x3 224 #define LAYER_SEL_PORT_SHIFT 16 225 226 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 227 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 228 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 229 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 230 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 231 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 232 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 233 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 234 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 235 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 236 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 237 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 238 #define RK3568_VP0_BG_MIX_CTRL 0x6E0 239 #define BG_MIX_CTRL_MASK 0xff 240 #define BG_MIX_CTRL_SHIFT 24 241 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 242 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 243 #define RK3568_CLUSTER_DLY_NUM 0x6F0 244 #define RK3568_SMART_DLY_NUM 0x6F8 245 246 /* Video Port registers definition */ 247 #define RK3568_VP0_DSP_CTRL 0xC00 248 #define OUT_MODE_MASK 0xf 249 #define OUT_MODE_SHIFT 0 250 #define DATA_SWAP_MASK 0x1f 251 #define DATA_SWAP_SHIFT 8 252 #define DSP_BG_SWAP 0x1 253 #define DSP_RB_SWAP 0x2 254 #define DSP_RG_SWAP 0x4 255 #define DSP_DELTA_SWAP 0x8 256 #define CORE_DCLK_DIV_EN_SHIFT 4 257 #define P2I_EN_SHIFT 5 258 #define DSP_FILED_POL 6 259 #define INTERLACE_EN_SHIFT 7 260 #define DSP_X_MIR_EN_SHIFT 13 261 #define POST_DSP_OUT_R2Y_SHIFT 15 262 #define PRE_DITHER_DOWN_EN_SHIFT 16 263 #define DITHER_DOWN_EN_SHIFT 17 264 #define DSP_LUT_EN_SHIFT 28 265 266 #define STANDBY_EN_SHIFT 31 267 268 #define RK3568_VP0_MIPI_CTRL 0xC04 269 #define DCLK_DIV2_SHIFT 4 270 #define DCLK_DIV2_MASK 0x3 271 #define MIPI_DUAL_EN_SHIFT 20 272 #define MIPI_DUAL_SWAP_EN_SHIFT 21 273 #define EDPI_TE_EN 28 274 #define EDPI_WMS_HOLD_EN 30 275 #define EDPI_WMS_FS 31 276 277 278 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 279 #define RK3568_VP0_3D_LUT_CTRL 0xC10 280 #define VP0_3D_LUT_EN_SHIFT 0 281 #define VP0_3D_LUT_UPDATE_SHIFT 2 282 283 #define RK3588_VP0_CLK_CTRL 0xC0C 284 #define DCLK_CORE_DIV_SHIFT 0 285 #define DCLK_OUT_DIV_SHIFT 2 286 287 #define RK3568_VP0_3D_LUT_MST 0xC20 288 289 #define RK3568_VP0_DSP_BG 0xC2C 290 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 291 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 292 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 293 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C 294 #define RK3568_VP0_POST_SCL_CTRL 0xC40 295 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 296 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 297 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C 298 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 299 #define RK3568_VP0_DSP_VACT_ST_END 0xC54 300 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 301 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C 302 303 #define RK3568_VP0_BCSH_CTRL 0xC60 304 #define BCSH_CTRL_Y2R_SHIFT 0 305 #define BCSH_CTRL_Y2R_MASK 0x1 306 #define BCSH_CTRL_Y2R_CSC_MODE_SHIFT 2 307 #define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3 308 #define BCSH_CTRL_R2Y_SHIFT 4 309 #define BCSH_CTRL_R2Y_MASK 0x1 310 #define BCSH_CTRL_R2Y_CSC_MODE_SHIFT 6 311 #define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3 312 313 #define RK3568_VP0_BCSH_BCS 0xC64 314 #define BCSH_BRIGHTNESS_SHIFT 0 315 #define BCSH_BRIGHTNESS_MASK 0xFF 316 #define BCSH_CONTRAST_SHIFT 8 317 #define BCSH_CONTRAST_MASK 0x1FF 318 #define BCSH_SATURATION_SHIFT 20 319 #define BCSH_SATURATION_MASK 0x3FF 320 #define BCSH_OUT_MODE_SHIFT 30 321 #define BCSH_OUT_MODE_MASK 0x3 322 323 #define RK3568_VP0_BCSH_H 0xC68 324 #define BCSH_SIN_HUE_SHIFT 0 325 #define BCSH_SIN_HUE_MASK 0x1FF 326 #define BCSH_COS_HUE_SHIFT 16 327 #define BCSH_COS_HUE_MASK 0x1FF 328 329 #define RK3568_VP0_BCSH_COLOR 0xC6C 330 #define BCSH_EN_SHIFT 31 331 #define BCSH_EN_MASK 1 332 333 #define RK3568_VP1_DSP_CTRL 0xD00 334 #define RK3568_VP1_MIPI_CTRL 0xD04 335 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 336 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 337 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 338 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 339 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C 340 #define RK3568_VP1_POST_SCL_CTRL 0xD40 341 #define RK3568_VP1_DSP_HACT_INFO 0xD34 342 #define RK3568_VP1_DSP_VACT_INFO 0xD38 343 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 344 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 345 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C 346 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 347 #define RK3568_VP1_DSP_VACT_ST_END 0xD54 348 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 349 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C 350 351 #define RK3568_VP2_DSP_CTRL 0xE00 352 #define RK3568_VP2_MIPI_CTRL 0xE04 353 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 354 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 355 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 356 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 357 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C 358 #define RK3568_VP2_POST_SCL_CTRL 0xE40 359 #define RK3568_VP2_DSP_HACT_INFO 0xE34 360 #define RK3568_VP2_DSP_VACT_INFO 0xE38 361 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 362 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 363 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C 364 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 365 #define RK3568_VP2_DSP_VACT_ST_END 0xE54 366 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 367 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C 368 369 /* Cluster0 register definition */ 370 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 371 #define CLUSTER_YUV2RGB_EN_SHIFT 8 372 #define CLUSTER_RGB2YUV_EN_SHIFT 9 373 #define CLUSTER_CSC_MODE_SHIFT 10 374 #define CLUSTER_YRGB_XSCL_MODE_SHIFT 12 375 #define CLUSTER_YRGB_YSCL_MODE_SHIFT 14 376 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 377 #define CLUSTER_YRGB_GT2_SHIFT 28 378 #define CLUSTER_YRGB_GT4_SHIFT 29 379 #define RK3568_CLUSTER0_WIN0_CTRL2 0x1008 380 #define CLUSTER_AXI_YRGB_ID_MASK 0x1f 381 #define CLUSTER_AXI_YRGB_ID_SHIFT 0 382 #define CLUSTER_AXI_UV_ID_MASK 0x1f 383 #define CLUSTER_AXI_UV_ID_SHIFT 5 384 385 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 386 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 387 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 388 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 389 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 390 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 391 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 392 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 393 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 394 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C 395 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 396 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 397 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 398 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C 399 400 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 401 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 402 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 403 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 404 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 405 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 406 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 407 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 408 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 409 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 410 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 411 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC 412 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 413 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 414 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 415 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC 416 417 #define RK3568_CLUSTER0_CTRL 0x1100 418 #define CLUSTER_EN_SHIFT 0 419 #define CLUSTER_AXI_ID_MASK 0x1 420 #define CLUSTER_AXI_ID_SHIFT 13 421 422 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 423 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 424 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 425 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 426 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 427 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 428 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 429 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 430 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 431 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 432 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 433 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C 434 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 435 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 436 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 437 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C 438 439 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 440 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 441 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 442 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 443 #define RK3568_CLUSTER1_WIN1_VIR 0x1298 444 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 445 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 446 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 447 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 448 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 449 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 450 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC 451 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 452 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 453 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 454 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC 455 456 #define RK3568_CLUSTER1_CTRL 0x1300 457 458 /* Esmart register definition */ 459 #define RK3568_ESMART0_CTRL0 0x1800 460 #define RGB2YUV_EN_SHIFT 1 461 #define CSC_MODE_SHIFT 2 462 #define CSC_MODE_MASK 0x3 463 464 #define RK3568_ESMART0_CTRL1 0x1804 465 #define ESMART_AXI_YRGB_ID_MASK 0x1f 466 #define ESMART_AXI_YRGB_ID_SHIFT 4 467 #define ESMART_AXI_UV_ID_MASK 0x1f 468 #define ESMART_AXI_UV_ID_SHIFT 12 469 #define YMIRROR_EN_SHIFT 31 470 471 #define RK3568_ESMART0_AXI_CTRL 0x1808 472 #define ESMART_AXI_ID_MASK 0x1 473 #define ESMART_AXI_ID_SHIFT 1 474 475 #define RK3568_ESMART0_REGION0_CTRL 0x1810 476 #define REGION0_RB_SWAP_SHIFT 14 477 #define WIN_EN_SHIFT 0 478 #define WIN_FORMAT_MASK 0x1f 479 #define WIN_FORMAT_SHIFT 1 480 481 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 482 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 483 #define RK3568_ESMART0_REGION0_VIR 0x181C 484 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 485 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 486 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828 487 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 488 #define YRGB_XSCL_MODE_MASK 0x3 489 #define YRGB_XSCL_MODE_SHIFT 0 490 #define YRGB_XSCL_FILTER_MODE_MASK 0x3 491 #define YRGB_XSCL_FILTER_MODE_SHIFT 2 492 #define YRGB_YSCL_MODE_MASK 0x3 493 #define YRGB_YSCL_MODE_SHIFT 4 494 #define YRGB_YSCL_FILTER_MODE_MASK 0x3 495 #define YRGB_YSCL_FILTER_MODE_SHIFT 6 496 497 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 498 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 499 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C 500 #define RK3568_ESMART0_REGION1_CTRL 0x1840 501 #define YRGB_GT2_MASK 0x1 502 #define YRGB_GT2_SHIFT 8 503 #define YRGB_GT4_MASK 0x1 504 #define YRGB_GT4_SHIFT 9 505 506 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 507 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848 508 #define RK3568_ESMART0_REGION1_VIR 0x184C 509 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 510 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 511 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858 512 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 513 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 514 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 515 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C 516 #define RK3568_ESMART0_REGION2_CTRL 0x1870 517 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 518 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878 519 #define RK3568_ESMART0_REGION2_VIR 0x187C 520 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 521 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 522 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888 523 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 524 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 525 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 526 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C 527 #define RK3568_ESMART0_REGION3_CTRL 0x18A0 528 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 529 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 530 #define RK3568_ESMART0_REGION3_VIR 0x18AC 531 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 532 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 533 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 534 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 535 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 536 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 537 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC 538 539 #define RK3568_ESMART1_CTRL0 0x1A00 540 #define RK3568_ESMART1_CTRL1 0x1A04 541 #define RK3568_ESMART1_REGION0_CTRL 0x1A10 542 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 543 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 544 #define RK3568_ESMART1_REGION0_VIR 0x1A1C 545 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 546 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 547 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 548 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 549 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 550 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 551 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C 552 #define RK3568_ESMART1_REGION1_CTRL 0x1A40 553 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 554 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 555 #define RK3568_ESMART1_REGION1_VIR 0x1A4C 556 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 557 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 558 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 559 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 560 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 561 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 562 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C 563 #define RK3568_ESMART1_REGION2_CTRL 0x1A70 564 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 565 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 566 #define RK3568_ESMART1_REGION2_VIR 0x1A7C 567 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 568 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 569 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 570 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 571 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 572 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 573 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C 574 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0 575 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 576 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 577 #define RK3568_ESMART1_REGION3_VIR 0x1AAC 578 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 579 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 580 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 581 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 582 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 583 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 584 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC 585 586 #define RK3568_SMART0_CTRL0 0x1C00 587 #define RK3568_SMART0_CTRL1 0x1C04 588 #define RK3568_SMART0_REGION0_CTRL 0x1C10 589 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 590 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18 591 #define RK3568_SMART0_REGION0_VIR 0x1C1C 592 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 593 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 594 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28 595 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 596 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 597 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 598 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C 599 #define RK3568_SMART0_REGION1_CTRL 0x1C40 600 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 601 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48 602 #define RK3568_SMART0_REGION1_VIR 0x1C4C 603 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 604 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 605 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58 606 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 607 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 608 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 609 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C 610 #define RK3568_SMART0_REGION2_CTRL 0x1C70 611 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 612 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78 613 #define RK3568_SMART0_REGION2_VIR 0x1C7C 614 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 615 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 616 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88 617 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 618 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 619 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 620 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C 621 #define RK3568_SMART0_REGION3_CTRL 0x1CA0 622 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 623 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 624 #define RK3568_SMART0_REGION3_VIR 0x1CAC 625 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 626 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 627 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 628 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 629 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 630 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 631 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC 632 633 #define RK3568_SMART1_CTRL0 0x1E00 634 #define RK3568_SMART1_CTRL1 0x1E04 635 #define RK3568_SMART1_REGION0_CTRL 0x1E10 636 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 637 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18 638 #define RK3568_SMART1_REGION0_VIR 0x1E1C 639 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 640 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 641 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28 642 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 643 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 644 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 645 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C 646 #define RK3568_SMART1_REGION1_CTRL 0x1E40 647 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 648 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48 649 #define RK3568_SMART1_REGION1_VIR 0x1E4C 650 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 651 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 652 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58 653 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 654 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 655 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 656 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C 657 #define RK3568_SMART1_REGION2_CTRL 0x1E70 658 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 659 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78 660 #define RK3568_SMART1_REGION2_VIR 0x1E7C 661 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 662 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 663 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88 664 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 665 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 666 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 667 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C 668 #define RK3568_SMART1_REGION3_CTRL 0x1EA0 669 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 670 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 671 #define RK3568_SMART1_REGION3_VIR 0x1EAC 672 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 673 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 674 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 675 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 676 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 677 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 678 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC 679 680 /* DSC 8K/4K register definition */ 681 #define RK3588_DSC_8K_PPS0_3 0x4000 682 #define RK3588_DSC_8K_CTRL0 0x40A0 683 #define DSC_EN_SHIFT 0 684 #define DSC_RBIT_SHIFT 2 685 #define DSC_RBYT_SHIFT 3 686 #define DSC_FLAL_SHIFT 4 687 #define DSC_MER_SHIFT 5 688 #define DSC_EPB_SHIFT 6 689 #define DSC_EPL_SHIFT 7 690 #define DSC_NSLC_SHIFT 16 691 #define DSC_SBO_SHIFT 28 692 #define DSC_IFEP_SHIFT 29 693 #define DSC_PPS_UPD_SHIFT 31 694 695 #define RK3588_DSC_8K_CTRL1 0x40A4 696 #define RK3588_DSC_8K_STS0 0x40A8 697 #define RK3588_DSC_8K_ERS 0x40C4 698 699 #define RK3588_DSC_4K_PPS0_3 0x4100 700 #define RK3588_DSC_4K_CTRL0 0x41A0 701 #define RK3588_DSC_4K_CTRL1 0x41A4 702 #define RK3588_DSC_4K_STS0 0x41A8 703 #define RK3588_DSC_4K_ERS 0x41C4 704 705 #define RK3568_MAX_REG 0x1ED0 706 707 #define RK3568_GRF_VO_CON1 0x0364 708 #define GRF_BT656_CLK_INV_SHIFT 1 709 #define GRF_BT1120_CLK_INV_SHIFT 2 710 #define GRF_RGB_DCLK_INV_SHIFT 3 711 712 #define RK3588_GRF_VOP_CON2 0x0008 713 #define RK3588_GRF_EDP0_ENABLE_SHIFT 0 714 #define RK3588_GRF_HDMITX0_ENABLE_SHIFT 1 715 #define RK3588_GRF_EDP1_ENABLE_SHIFT 3 716 #define RK3588_GRF_HDMITX1_ENABLE_SHIFT 4 717 718 #define RK3588_GRF_VO1_CON0 0x0000 719 #define HDMI_SYNC_POL_MASK 0x3 720 #define HDMI0_SYNC_POL_SHIFT 5 721 #define HDMI1_SYNC_POL_SHIFT 7 722 723 #define RK3588_PMU_BISR_CON3 0x20C 724 #define RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT 9 725 #define RK3588_PD_CLUSTER1_REPAIR_EN_SHIFT 10 726 #define RK3588_PD_CLUSTER2_REPAIR_EN_SHIFT 11 727 #define RK3588_PD_CLUSTER3_REPAIR_EN_SHIFT 12 728 #define RK3588_PD_DSC_8K_REPAIR_EN_SHIFT 13 729 #define RK3588_PD_DSC_4K_REPAIR_EN_SHIFT 14 730 #define RK3588_PD_ESMART_REPAIR_EN_SHIFT 15 731 732 #define RK3588_PMU_BISR_STATUS5 0x294 733 #define RK3588_PD_CLUSTER0_PWR_STAT_SHIFI 9 734 #define RK3588_PD_CLUSTER1_PWR_STAT_SHIFI 10 735 #define RK3588_PD_CLUSTER2_PWR_STAT_SHIFI 11 736 #define RK3588_PD_CLUSTER3_PWR_STAT_SHIFI 12 737 #define RK3588_PD_DSC_8K_PWR_STAT_SHIFI 13 738 #define RK3588_PD_DSC_4K_PWR_STAT_SHIFI 14 739 #define RK3588_PD_ESMART_PWR_STAT_SHIFI 15 740 741 #define VOP2_LAYER_MAX 8 742 743 #define VOP2_MAX_VP_OUTPUT_WIDTH 4096 744 745 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 746 747 /* KHz */ 748 #define VOP2_MAX_DCLK_RATE 600000 749 750 /* 751 * vop2 dsc id 752 */ 753 #define ROCKCHIP_VOP2_DSC_8K 0 754 #define ROCKCHIP_VOP2_DSC_4K 1 755 756 /* 757 * vop2 internal power domain id, 758 * should be all none zero, 0 will be 759 * treat as invalid; 760 */ 761 #define VOP2_PD_CLUSTER0 BIT(0) 762 #define VOP2_PD_CLUSTER1 BIT(1) 763 #define VOP2_PD_CLUSTER2 BIT(2) 764 #define VOP2_PD_CLUSTER3 BIT(3) 765 #define VOP2_PD_DSC_8K BIT(5) 766 #define VOP2_PD_DSC_4K BIT(6) 767 #define VOP2_PD_ESMART BIT(7) 768 769 #define VOP2_PLANE_NO_SCALING BIT(16) 770 771 enum vop2_csc_format { 772 CSC_BT601L, 773 CSC_BT709L, 774 CSC_BT601F, 775 CSC_BT2020, 776 }; 777 778 enum vop2_pol { 779 HSYNC_POSITIVE = 0, 780 VSYNC_POSITIVE = 1, 781 DEN_NEGATIVE = 2, 782 DCLK_INVERT = 3 783 }; 784 785 enum vop2_bcsh_out_mode { 786 BCSH_OUT_MODE_BLACK, 787 BCSH_OUT_MODE_BLUE, 788 BCSH_OUT_MODE_COLOR_BAR, 789 BCSH_OUT_MODE_NORMAL_VIDEO, 790 }; 791 792 #define _VOP_REG(off, _mask, _shift, _write_mask) \ 793 { \ 794 .offset = off, \ 795 .mask = _mask, \ 796 .shift = _shift, \ 797 .write_mask = _write_mask, \ 798 } 799 800 #define VOP_REG(off, _mask, _shift) \ 801 _VOP_REG(off, _mask, _shift, false) 802 enum dither_down_mode { 803 RGB888_TO_RGB565 = 0x0, 804 RGB888_TO_RGB666 = 0x1 805 }; 806 807 enum vop2_video_ports_id { 808 VOP2_VP0, 809 VOP2_VP1, 810 VOP2_VP2, 811 VOP2_VP3, 812 VOP2_VP_MAX, 813 }; 814 815 enum vop2_layer_type { 816 CLUSTER_LAYER = 0, 817 ESMART_LAYER = 1, 818 SMART_LAYER = 2, 819 }; 820 821 /* This define must same with kernel win phy id */ 822 enum vop2_layer_phy_id { 823 ROCKCHIP_VOP2_CLUSTER0 = 0, 824 ROCKCHIP_VOP2_CLUSTER1, 825 ROCKCHIP_VOP2_ESMART0, 826 ROCKCHIP_VOP2_ESMART1, 827 ROCKCHIP_VOP2_SMART0, 828 ROCKCHIP_VOP2_SMART1, 829 ROCKCHIP_VOP2_CLUSTER2, 830 ROCKCHIP_VOP2_CLUSTER3, 831 ROCKCHIP_VOP2_ESMART2, 832 ROCKCHIP_VOP2_ESMART3, 833 ROCKCHIP_VOP2_LAYER_MAX, 834 }; 835 836 enum vop2_scale_up_mode { 837 VOP2_SCALE_UP_NRST_NBOR, 838 VOP2_SCALE_UP_BIL, 839 VOP2_SCALE_UP_BIC, 840 }; 841 842 enum vop2_scale_down_mode { 843 VOP2_SCALE_DOWN_NRST_NBOR, 844 VOP2_SCALE_DOWN_BIL, 845 VOP2_SCALE_DOWN_AVG, 846 }; 847 848 enum scale_mode { 849 SCALE_NONE = 0x0, 850 SCALE_UP = 0x1, 851 SCALE_DOWN = 0x2 852 }; 853 854 enum vop_dsc_interface_mode { 855 VOP_DSC_IF_DISABLE = 0, 856 VOP_DSC_IF_HDMI = 1, 857 VOP_DSC_IF_MIPI_DS_MODE = 2, 858 VOP_DSC_IF_MIPI_VIDEO_MODE = 3, 859 }; 860 861 struct vop2_layer { 862 u8 id; 863 /** 864 * @win_phys_id: window id of the layer selected. 865 * Every layer must make sure to select different 866 * windows of others. 867 */ 868 u8 win_phys_id; 869 }; 870 871 struct vop2_power_domain_data { 872 u8 id; 873 u8 parent_id; 874 /* 875 * @module_id_mask: module id of which module this power domain is belongs to. 876 * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3 877 */ 878 u32 module_id_mask; 879 }; 880 881 struct vop2_win_data { 882 char *name; 883 u8 phys_id; 884 enum vop2_layer_type type; 885 u8 win_sel_port_offset; 886 u8 layer_sel_win_id; 887 u8 axi_id; 888 u8 axi_uv_id; 889 u8 axi_yrgb_id; 890 u8 splice_win_id; 891 u8 pd_id; 892 u32 reg_offset; 893 u32 max_upscale_factor; 894 u32 max_downscale_factor; 895 bool splice_mode_right; 896 }; 897 898 struct vop2_vp_data { 899 u32 feature; 900 u8 pre_scan_max_dly; 901 u8 splice_vp_id; 902 struct vop_rect max_output; 903 u32 max_dclk; 904 }; 905 906 struct vop2_plane_table { 907 enum vop2_layer_phy_id plane_id; 908 enum vop2_layer_type plane_type; 909 }; 910 911 struct vop2_vp_plane_mask { 912 u8 primary_plane_id; /* use this win to show logo */ 913 u8 attached_layers_nr; /* number layers attach to this vp */ 914 u8 attached_layers[VOP2_LAYER_MAX]; /* the layers attached to this vp */ 915 u32 plane_mask; 916 int cursor_plane_id; 917 }; 918 919 struct vop2_dsc_data { 920 u8 id; 921 u8 pd_id; 922 u8 max_slice_num; 923 u8 max_linebuf_depth; /* used to generate the bitstream */ 924 u8 min_bits_per_pixel; /* bit num after encoder compress */ 925 const char *dsc_txp_clk_src_name; 926 const char *dsc_txp_clk_name; 927 const char *dsc_pxl_clk_name; 928 const char *dsc_cds_clk_name; 929 }; 930 931 struct dsc_error_info { 932 u32 dsc_error_val; 933 char dsc_error_info[50]; 934 }; 935 936 struct vop2_data { 937 u32 version; 938 struct vop2_vp_data *vp_data; 939 struct vop2_win_data *win_data; 940 struct vop2_vp_plane_mask *plane_mask; 941 struct vop2_plane_table *plane_table; 942 struct vop2_power_domain_data *pd; 943 struct vop2_dsc_data *dsc; 944 struct dsc_error_info *dsc_error_ecw; 945 struct dsc_error_info *dsc_error_buffer_flow; 946 u8 nr_vps; 947 u8 nr_layers; 948 u8 nr_mixers; 949 u8 nr_gammas; 950 u8 nr_pd; 951 u8 nr_dscs; 952 u8 nr_dsc_ecw; 953 u8 nr_dsc_buffer_flow; 954 u32 reg_len; 955 }; 956 957 struct vop2 { 958 u32 *regsbak; 959 void *regs; 960 void *grf; 961 void *vop_grf; 962 void *vo1_grf; 963 void *sys_pmu; 964 u32 reg_len; 965 u32 version; 966 bool global_init; 967 const struct vop2_data *data; 968 struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX]; 969 }; 970 971 static struct vop2 *rockchip_vop2; 972 /* 973 * bli_sd_factor = (src - 1) / (dst - 1) << 12; 974 * avg_sd_factor: 975 * bli_su_factor: 976 * bic_su_factor: 977 * = (src - 1) / (dst - 1) << 16; 978 * 979 * gt2 enable: dst get one line from two line of the src 980 * gt4 enable: dst get one line from four line of the src. 981 * 982 */ 983 #define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1)) 984 #define VOP2_COMMON_SCL(src, dst) (((src - 1) << 16) / (dst - 1)) 985 986 #define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \ 987 (fac * (dst - 1) >> 12 < (src - 1)) 988 #define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \ 989 (fac * (dst - 1) >> 16 < (src - 1)) 990 991 static uint16_t vop2_scale_factor(enum scale_mode mode, 992 int32_t filter_mode, 993 uint32_t src, uint32_t dst) 994 { 995 uint32_t fac = 0; 996 int i = 0; 997 998 if (mode == SCALE_NONE) 999 return 0; 1000 1001 /* 1002 * A workaround to avoid zero div. 1003 */ 1004 if ((dst == 1) || (src == 1)) { 1005 dst = dst + 1; 1006 src = src + 1; 1007 } 1008 1009 if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) { 1010 fac = VOP2_BILI_SCL_DN(src, dst); 1011 for (i = 0; i < 100; i++) { 1012 if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac)) 1013 break; 1014 fac -= 1; 1015 printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 1016 } 1017 } else { 1018 fac = VOP2_COMMON_SCL(src, dst); 1019 for (i = 0; i < 100; i++) { 1020 if (VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac)) 1021 break; 1022 fac -= 1; 1023 printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 1024 } 1025 } 1026 1027 return fac; 1028 } 1029 1030 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 1031 { 1032 if (src < dst) 1033 return SCALE_UP; 1034 else if (src > dst) 1035 return SCALE_DOWN; 1036 1037 return SCALE_NONE; 1038 } 1039 1040 static u8 rk3588_vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 1041 ROCKCHIP_VOP2_ESMART0, 1042 ROCKCHIP_VOP2_ESMART1, 1043 ROCKCHIP_VOP2_ESMART2, 1044 ROCKCHIP_VOP2_ESMART3, 1045 }; 1046 1047 static u8 rk3568_vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 1048 ROCKCHIP_VOP2_SMART0, 1049 ROCKCHIP_VOP2_SMART1, 1050 ROCKCHIP_VOP2_ESMART1, 1051 }; 1052 1053 static inline int interpolate(int x1, int y1, int x2, int y2, int x) 1054 { 1055 return y1 + (y2 - y1) * (x - x1) / (x2 - x1); 1056 } 1057 1058 static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask) 1059 { 1060 int i = 0; 1061 u8 *vop2_vp_primary_plane_order; 1062 u8 default_primary_plane; 1063 1064 if (vop2->version == VOP_VERSION_RK3588) { 1065 vop2_vp_primary_plane_order = rk3588_vop2_vp_primary_plane_order; 1066 default_primary_plane = ROCKCHIP_VOP2_ESMART0; 1067 } else { 1068 vop2_vp_primary_plane_order = rk3568_vop2_vp_primary_plane_order; 1069 default_primary_plane = ROCKCHIP_VOP2_SMART0; 1070 } 1071 1072 for (i = 0; i < vop2->data->nr_vps; i++) { 1073 if (plane_mask & BIT(vop2_vp_primary_plane_order[i])) 1074 return vop2_vp_primary_plane_order[i]; 1075 } 1076 1077 return default_primary_plane; 1078 } 1079 1080 static inline u16 scl_cal_scale(int src, int dst, int shift) 1081 { 1082 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 1083 } 1084 1085 static inline u16 scl_cal_scale2(int src, int dst) 1086 { 1087 return ((src - 1) << 12) / (dst - 1); 1088 } 1089 1090 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 1091 { 1092 writel(v, vop2->regs + offset); 1093 vop2->regsbak[offset >> 2] = v; 1094 } 1095 1096 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) 1097 { 1098 return readl(vop2->regs + offset); 1099 } 1100 1101 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, 1102 u32 mask, u32 shift, u32 v, 1103 bool write_mask) 1104 { 1105 if (!mask) 1106 return; 1107 1108 if (write_mask) { 1109 v = ((v & mask) << shift) | (mask << (shift + 16)); 1110 } else { 1111 u32 cached_val = vop2->regsbak[offset >> 2]; 1112 1113 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 1114 vop2->regsbak[offset >> 2] = v; 1115 } 1116 1117 writel(v, vop2->regs + offset); 1118 } 1119 1120 static inline void vop2_grf_writel(struct vop2 *vop, void *grf_base, u32 offset, 1121 u32 mask, u32 shift, u32 v) 1122 { 1123 u32 val = 0; 1124 1125 val = (v << shift) | (mask << (shift + 16)); 1126 writel(val, grf_base + offset); 1127 } 1128 1129 static inline u32 vop2_grf_readl(struct vop2 *vop, void *grf_base, u32 offset, 1130 u32 mask, u32 shift) 1131 { 1132 return (readl(grf_base + offset) >> shift) & mask; 1133 } 1134 1135 static char* get_output_if_name(u32 output_if, char *name) 1136 { 1137 if (output_if & VOP_OUTPUT_IF_RGB) 1138 strcat(name, " RGB"); 1139 if (output_if & VOP_OUTPUT_IF_BT1120) 1140 strcat(name, " BT1120"); 1141 if (output_if & VOP_OUTPUT_IF_BT656) 1142 strcat(name, " BT656"); 1143 if (output_if & VOP_OUTPUT_IF_LVDS0) 1144 strcat(name, " LVDS0"); 1145 if (output_if & VOP_OUTPUT_IF_LVDS1) 1146 strcat(name, " LVDS1"); 1147 if (output_if & VOP_OUTPUT_IF_MIPI0) 1148 strcat(name, " MIPI0"); 1149 if (output_if & VOP_OUTPUT_IF_MIPI1) 1150 strcat(name, " MIPI1"); 1151 if (output_if & VOP_OUTPUT_IF_eDP0) 1152 strcat(name, " eDP0"); 1153 if (output_if & VOP_OUTPUT_IF_eDP1) 1154 strcat(name, " eDP1"); 1155 if (output_if & VOP_OUTPUT_IF_DP0) 1156 strcat(name, " DP0"); 1157 if (output_if & VOP_OUTPUT_IF_DP1) 1158 strcat(name, " DP1"); 1159 if (output_if & VOP_OUTPUT_IF_HDMI0) 1160 strcat(name, " HDMI0"); 1161 if (output_if & VOP_OUTPUT_IF_HDMI1) 1162 strcat(name, " HDMI1"); 1163 1164 return name; 1165 } 1166 1167 static char *get_plane_name(int plane_id, char *name) 1168 { 1169 switch (plane_id) { 1170 case ROCKCHIP_VOP2_CLUSTER0: 1171 strcat(name, "Cluster0"); 1172 break; 1173 case ROCKCHIP_VOP2_CLUSTER1: 1174 strcat(name, "Cluster1"); 1175 break; 1176 case ROCKCHIP_VOP2_ESMART0: 1177 strcat(name, "Esmart0"); 1178 break; 1179 case ROCKCHIP_VOP2_ESMART1: 1180 strcat(name, "Esmart1"); 1181 break; 1182 case ROCKCHIP_VOP2_SMART0: 1183 strcat(name, "Smart0"); 1184 break; 1185 case ROCKCHIP_VOP2_SMART1: 1186 strcat(name, "Smart1"); 1187 break; 1188 case ROCKCHIP_VOP2_CLUSTER2: 1189 strcat(name, "Cluster2"); 1190 break; 1191 case ROCKCHIP_VOP2_CLUSTER3: 1192 strcat(name, "Cluster3"); 1193 break; 1194 case ROCKCHIP_VOP2_ESMART2: 1195 strcat(name, "Esmart2"); 1196 break; 1197 case ROCKCHIP_VOP2_ESMART3: 1198 strcat(name, "Esmart3"); 1199 break; 1200 } 1201 1202 return name; 1203 } 1204 1205 static bool is_yuv_output(u32 bus_format) 1206 { 1207 switch (bus_format) { 1208 case MEDIA_BUS_FMT_YUV8_1X24: 1209 case MEDIA_BUS_FMT_YUV10_1X30: 1210 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1211 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1212 case MEDIA_BUS_FMT_YUYV8_2X8: 1213 case MEDIA_BUS_FMT_YVYU8_2X8: 1214 case MEDIA_BUS_FMT_UYVY8_2X8: 1215 case MEDIA_BUS_FMT_VYUY8_2X8: 1216 case MEDIA_BUS_FMT_YUYV8_1X16: 1217 case MEDIA_BUS_FMT_YVYU8_1X16: 1218 case MEDIA_BUS_FMT_UYVY8_1X16: 1219 case MEDIA_BUS_FMT_VYUY8_1X16: 1220 return true; 1221 default: 1222 return false; 1223 } 1224 } 1225 1226 static int vop2_convert_csc_mode(int csc_mode) 1227 { 1228 switch (csc_mode) { 1229 case V4L2_COLORSPACE_SMPTE170M: 1230 case V4L2_COLORSPACE_470_SYSTEM_M: 1231 case V4L2_COLORSPACE_470_SYSTEM_BG: 1232 return CSC_BT601L; 1233 case V4L2_COLORSPACE_REC709: 1234 case V4L2_COLORSPACE_SMPTE240M: 1235 case V4L2_COLORSPACE_DEFAULT: 1236 return CSC_BT709L; 1237 case V4L2_COLORSPACE_JPEG: 1238 return CSC_BT601F; 1239 case V4L2_COLORSPACE_BT2020: 1240 return CSC_BT2020; 1241 default: 1242 return CSC_BT709L; 1243 } 1244 } 1245 1246 static bool is_uv_swap(u32 bus_format, u32 output_mode) 1247 { 1248 /* 1249 * FIXME: 1250 * 1251 * There is no media type for YUV444 output, 1252 * so when out_mode is AAAA or P888, assume output is YUV444 on 1253 * yuv format. 1254 * 1255 * From H/W testing, YUV444 mode need a rb swap. 1256 */ 1257 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || 1258 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || 1259 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || 1260 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || 1261 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 1262 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 1263 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 1264 output_mode == ROCKCHIP_OUT_MODE_P888))) 1265 return true; 1266 else 1267 return false; 1268 } 1269 1270 static inline bool is_hot_plug_devices(int output_type) 1271 { 1272 switch (output_type) { 1273 case DRM_MODE_CONNECTOR_HDMIA: 1274 case DRM_MODE_CONNECTOR_HDMIB: 1275 case DRM_MODE_CONNECTOR_TV: 1276 case DRM_MODE_CONNECTOR_DisplayPort: 1277 case DRM_MODE_CONNECTOR_VGA: 1278 case DRM_MODE_CONNECTOR_Unknown: 1279 return true; 1280 default: 1281 return false; 1282 } 1283 } 1284 1285 static struct vop2_win_data *vop2_find_win_by_phys_id(struct vop2 *vop2, int phys_id) 1286 { 1287 int i = 0; 1288 1289 for (i = 0; i < vop2->data->nr_layers; i++) { 1290 if (vop2->data->win_data[i].phys_id == phys_id) 1291 return &vop2->data->win_data[i]; 1292 } 1293 1294 return NULL; 1295 } 1296 1297 static struct vop2_power_domain_data *vop2_find_pd_data_by_id(struct vop2 *vop2, int pd_id) 1298 { 1299 int i = 0; 1300 1301 for (i = 0; i < vop2->data->nr_pd; i++) { 1302 if (vop2->data->pd[i].id == pd_id) 1303 return &vop2->data->pd[i]; 1304 } 1305 1306 return NULL; 1307 } 1308 1309 static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, 1310 struct display_state *state) 1311 { 1312 struct connector_state *conn_state = &state->conn_state; 1313 struct crtc_state *cstate = &state->crtc_state; 1314 struct resource gamma_res; 1315 fdt_size_t lut_size; 1316 int i, lut_len, ret = 0; 1317 u32 *lut_regs; 1318 u32 *lut_val; 1319 u32 r, g, b; 1320 u32 vp_offset = cstate->crtc_id * 0x100; 1321 struct base2_disp_info *disp_info = conn_state->disp_info; 1322 static int gamma_lut_en_num = 1; 1323 1324 if (gamma_lut_en_num > vop2->data->nr_gammas) { 1325 printf("warn: only %d vp support gamma\n", vop2->data->nr_gammas); 1326 return 0; 1327 } 1328 1329 if (!disp_info) 1330 return 0; 1331 1332 if (!disp_info->gamma_lut_data.size) 1333 return 0; 1334 1335 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); 1336 if (ret) 1337 printf("failed to get gamma lut res\n"); 1338 lut_regs = (u32 *)gamma_res.start; 1339 lut_size = gamma_res.end - gamma_res.start + 1; 1340 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 1341 printf("failed to get gamma lut register\n"); 1342 return 0; 1343 } 1344 lut_len = lut_size / 4; 1345 if (lut_len != 256 && lut_len != 1024) { 1346 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 1347 return 0; 1348 } 1349 lut_val = (u32 *)calloc(1, lut_size); 1350 for (i = 0; i < lut_len; i++) { 1351 r = disp_info->gamma_lut_data.lred[i] * (lut_len - 1) / 0xffff; 1352 g = disp_info->gamma_lut_data.lgreen[i] * (lut_len - 1) / 0xffff; 1353 b = disp_info->gamma_lut_data.lblue[i] * (lut_len - 1) / 0xffff; 1354 1355 lut_val[i] = b * lut_len * lut_len + g * lut_len + r; 1356 } 1357 1358 for (i = 0; i < lut_len; i++) 1359 writel(lut_val[i], lut_regs + i); 1360 1361 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, 1362 GAMMA_PORT_SEL_MASK, GAMMA_PORT_SEL_SHIFT, 1363 cstate->crtc_id , false); 1364 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1365 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); 1366 gamma_lut_en_num++; 1367 1368 return 0; 1369 } 1370 1371 static int rockchip_vop2_cubic_lut_init(struct vop2 *vop2, 1372 struct display_state *state) 1373 { 1374 struct connector_state *conn_state = &state->conn_state; 1375 struct crtc_state *cstate = &state->crtc_state; 1376 int i, cubic_lut_len; 1377 u32 vp_offset = cstate->crtc_id * 0x100; 1378 struct base2_disp_info *disp_info = conn_state->disp_info; 1379 struct base2_cubic_lut_data *lut = &conn_state->disp_info->cubic_lut_data; 1380 u32 *cubic_lut_addr; 1381 1382 if (!disp_info || CONFIG_ROCKCHIP_CUBIC_LUT_SIZE == 0) 1383 return 0; 1384 1385 if (!disp_info->cubic_lut_data.size) 1386 return 0; 1387 1388 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); 1389 cubic_lut_len = disp_info->cubic_lut_data.size; 1390 1391 for (i = 0; i < cubic_lut_len / 2; i++) { 1392 *cubic_lut_addr++ = ((lut->lred[2 * i]) & 0xfff) + 1393 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1394 ((lut->lblue[2 * i] & 0xff) << 24); 1395 *cubic_lut_addr++ = ((lut->lblue[2 * i] & 0xf00) >> 8) + 1396 ((lut->lred[2 * i + 1] & 0xfff) << 4) + 1397 ((lut->lgreen[2 * i + 1] & 0xfff) << 16) + 1398 ((lut->lblue[2 * i + 1] & 0xf) << 28); 1399 *cubic_lut_addr++ = (lut->lblue[2 * i + 1] & 0xff0) >> 4; 1400 *cubic_lut_addr++ = 0; 1401 } 1402 1403 if (cubic_lut_len % 2) { 1404 *cubic_lut_addr++ = (lut->lred[2 * i] & 0xfff) + 1405 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1406 ((lut->lblue[2 * i] & 0xff) << 24); 1407 *cubic_lut_addr++ = (lut->lblue[2 * i] & 0xf00) >> 8; 1408 *cubic_lut_addr++ = 0; 1409 *cubic_lut_addr = 0; 1410 } 1411 1412 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, 1413 get_cubic_lut_buffer(cstate->crtc_id)); 1414 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, 1415 EN_MASK, LUT_DMA_EN_SHIFT, 1, false); 1416 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1417 EN_MASK, VP0_3D_LUT_EN_SHIFT, 1, false); 1418 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1419 EN_MASK, VP0_3D_LUT_UPDATE_SHIFT, 1, false); 1420 1421 return 0; 1422 } 1423 1424 static void vop2_bcsh_reg_update(struct display_state *state, struct vop2 *vop2, 1425 struct bcsh_state *bcsh_state, int crtc_id) 1426 { 1427 struct crtc_state *cstate = &state->crtc_state; 1428 u32 vp_offset = crtc_id * 0x100; 1429 1430 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, 1431 BCSH_CTRL_R2Y_SHIFT, cstate->post_r2y_en, false); 1432 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, 1433 BCSH_CTRL_Y2R_SHIFT, cstate->post_y2r_en, false); 1434 1435 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, 1436 BCSH_CTRL_R2Y_CSC_MODE_SHIFT, cstate->post_csc_mode, false); 1437 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, 1438 BCSH_CTRL_Y2R_CSC_MODE_SHIFT, cstate->post_csc_mode, false); 1439 1440 if (!cstate->bcsh_en) { 1441 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1442 BCSH_EN_MASK, BCSH_EN_SHIFT, 0, false); 1443 return; 1444 } 1445 1446 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1447 BCSH_BRIGHTNESS_MASK, BCSH_BRIGHTNESS_SHIFT, 1448 bcsh_state->brightness, false); 1449 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1450 BCSH_CONTRAST_MASK, BCSH_CONTRAST_SHIFT, bcsh_state->contrast, false); 1451 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1452 BCSH_SATURATION_MASK, BCSH_SATURATION_SHIFT, 1453 bcsh_state->saturation * bcsh_state->contrast / 0x100, false); 1454 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1455 BCSH_SIN_HUE_MASK, BCSH_SIN_HUE_SHIFT, bcsh_state->sin_hue, false); 1456 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1457 BCSH_COS_HUE_MASK, BCSH_COS_HUE_SHIFT, bcsh_state->cos_hue, false); 1458 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1459 BCSH_OUT_MODE_MASK, BCSH_OUT_MODE_SHIFT, 1460 BCSH_OUT_MODE_NORMAL_VIDEO, false); 1461 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1462 BCSH_EN_MASK, BCSH_EN_SHIFT, 1, false); 1463 } 1464 1465 static void vop2_tv_config_update(struct display_state *state, struct vop2 *vop2) 1466 { 1467 struct connector_state *conn_state = &state->conn_state; 1468 struct base_bcsh_info *bcsh_info; 1469 struct crtc_state *cstate = &state->crtc_state; 1470 struct bcsh_state bcsh_state; 1471 int brightness, contrast, saturation, hue, sin_hue, cos_hue; 1472 1473 if (!conn_state->disp_info) 1474 return; 1475 bcsh_info = &conn_state->disp_info->bcsh_info; 1476 if (!bcsh_info) 1477 return; 1478 1479 if (bcsh_info->brightness != 50 || 1480 bcsh_info->contrast != 50 || 1481 bcsh_info->saturation != 50 || bcsh_info->hue != 50) 1482 cstate->bcsh_en = true; 1483 1484 if (cstate->bcsh_en) { 1485 if (!cstate->yuv_overlay) 1486 cstate->post_r2y_en = 1; 1487 if (!is_yuv_output(conn_state->bus_format)) 1488 cstate->post_y2r_en = 1; 1489 } else { 1490 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) 1491 cstate->post_r2y_en = 1; 1492 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) 1493 cstate->post_y2r_en = 1; 1494 } 1495 1496 cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1497 1498 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT) 1499 brightness = interpolate(0, -128, 100, 127, 1500 bcsh_info->brightness); 1501 else 1502 brightness = interpolate(0, -32, 100, 31, 1503 bcsh_info->brightness); 1504 contrast = interpolate(0, 0, 100, 511, bcsh_info->contrast); 1505 saturation = interpolate(0, 0, 100, 511, bcsh_info->saturation); 1506 hue = interpolate(0, -30, 100, 30, bcsh_info->hue); 1507 1508 1509 /* 1510 * a:[-30~0): 1511 * sin_hue = 0x100 - sin(a)*256; 1512 * cos_hue = cos(a)*256; 1513 * a:[0~30] 1514 * sin_hue = sin(a)*256; 1515 * cos_hue = cos(a)*256; 1516 */ 1517 sin_hue = fixp_sin32(hue) >> 23; 1518 cos_hue = fixp_cos32(hue) >> 23; 1519 1520 bcsh_state.brightness = brightness; 1521 bcsh_state.contrast = contrast; 1522 bcsh_state.saturation = saturation; 1523 bcsh_state.sin_hue = sin_hue; 1524 bcsh_state.cos_hue = cos_hue; 1525 1526 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->crtc_id); 1527 if (cstate->splice_mode) 1528 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->splice_crtc_id); 1529 } 1530 1531 static void vop2_setup_dly_for_vp(struct display_state *state, struct vop2 *vop2, int crtc_id) 1532 { 1533 struct connector_state *conn_state = &state->conn_state; 1534 struct drm_display_mode *mode = &conn_state->mode; 1535 struct crtc_state *cstate = &state->crtc_state; 1536 u32 bg_ovl_dly, bg_dly, pre_scan_dly; 1537 u16 hdisplay = mode->crtc_hdisplay; 1538 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1539 1540 bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly; 1541 bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly; 1542 bg_dly -= bg_ovl_dly; 1543 1544 if (cstate->splice_mode) 1545 pre_scan_dly = bg_dly + (hdisplay >> 2) - 1; 1546 else 1547 pre_scan_dly = bg_dly + (hdisplay >> 1) - 1; 1548 1549 if (vop2->version == VOP_VERSION_RK3588 && hsync_len < 8) 1550 hsync_len = 8; 1551 pre_scan_dly = (pre_scan_dly << 16) | hsync_len; 1552 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4, 1553 BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false); 1554 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); 1555 } 1556 1557 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) 1558 { 1559 struct connector_state *conn_state = &state->conn_state; 1560 struct drm_display_mode *mode = &conn_state->mode; 1561 struct crtc_state *cstate = &state->crtc_state; 1562 u32 vp_offset = (cstate->crtc_id * 0x100); 1563 u16 vtotal = mode->crtc_vtotal; 1564 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1565 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1566 u16 hdisplay = mode->crtc_hdisplay; 1567 u16 vdisplay = mode->crtc_vdisplay; 1568 u16 hsize = 1569 hdisplay * (conn_state->overscan.left_margin + 1570 conn_state->overscan.right_margin) / 200; 1571 u16 vsize = 1572 vdisplay * (conn_state->overscan.top_margin + 1573 conn_state->overscan.bottom_margin) / 200; 1574 u16 hact_end, vact_end; 1575 u32 val; 1576 1577 hsize = round_down(hsize, 2); 1578 vsize = round_down(vsize, 2); 1579 1580 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 1581 hact_end = hact_st + hsize; 1582 val = hact_st << 16; 1583 val |= hact_end; 1584 1585 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); 1586 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 1587 vact_end = vact_st + vsize; 1588 val = vact_st << 16; 1589 val |= vact_end; 1590 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); 1591 val = scl_cal_scale2(vdisplay, vsize) << 16; 1592 val |= scl_cal_scale2(hdisplay, hsize); 1593 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); 1594 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 1595 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 1596 vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, 1597 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 1598 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 1599 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1600 u16 vact_st_f1 = vtotal + vact_st + 1; 1601 u16 vact_end_f1 = vact_st_f1 + vsize; 1602 1603 val = vact_st_f1 << 16 | vact_end_f1; 1604 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); 1605 } 1606 1607 vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); 1608 if (cstate->splice_mode) 1609 vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id); 1610 } 1611 1612 /* 1613 * Read VOP internal power domain on/off status. 1614 * We should query BISR_STS register in PMU for 1615 * power up/down status when memory repair is enabled. 1616 * Return value: 1 for power on, 0 for power off; 1617 */ 1618 static int vop2_wait_power_domain_on(struct vop2 *vop2, struct vop2_power_domain_data *pd_data) 1619 { 1620 int val = 0; 1621 int shift = 0; 1622 int shift_factor = 0; 1623 bool is_bisr_en = false; 1624 1625 /* 1626 * The order of pd status bits in BISR_STS register 1627 * is different from that in VOP SYS_STS register. 1628 */ 1629 if (pd_data->id == VOP2_PD_DSC_8K || 1630 pd_data->id == VOP2_PD_DSC_4K || 1631 pd_data->id == VOP2_PD_ESMART) 1632 shift_factor = 1; 1633 1634 shift = RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT + generic_ffs(pd_data->id) - 1 - shift_factor; 1635 is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3588_PMU_BISR_CON3, EN_MASK, shift); 1636 if (is_bisr_en) { 1637 shift = RK3588_PD_CLUSTER0_PWR_STAT_SHIFI + generic_ffs(pd_data->id) - 1 - shift_factor; 1638 1639 return readl_poll_timeout(vop2->sys_pmu + RK3588_PMU_BISR_STATUS5, val, 1640 ((val >> shift) & 0x1), 50 * 1000); 1641 } else { 1642 shift = RK3588_CLUSTER0_PD_STATUS_SHIFT + generic_ffs(pd_data->id) - 1; 1643 1644 return readl_poll_timeout(vop2->regs + RK3568_SYS_STATUS0, val, 1645 !((val >> shift) & 0x1), 50 * 1000); 1646 } 1647 } 1648 1649 static int vop2_power_domain_on(struct vop2 *vop2, int pd_id) 1650 { 1651 struct vop2_power_domain_data *pd_data; 1652 int ret = 0; 1653 1654 if (!pd_id) 1655 return 0; 1656 1657 pd_data = vop2_find_pd_data_by_id(vop2, pd_id); 1658 if (!pd_data) { 1659 printf("can't find pd_data by id\n"); 1660 return -EINVAL; 1661 } 1662 1663 if (pd_data->parent_id) { 1664 ret = vop2_power_domain_on(vop2, pd_data->parent_id); 1665 if (ret) { 1666 printf("can't open parent power domain\n"); 1667 return -EINVAL; 1668 } 1669 } 1670 1671 vop2_mask_write(vop2, RK3568_SYS_PD_CTRL, EN_MASK, 1672 RK3588_CLUSTER0_PD_EN_SHIFT + generic_ffs(pd_id) - 1, 0, false); 1673 ret = vop2_wait_power_domain_on(vop2, pd_data); 1674 if (ret) { 1675 printf("wait vop2 power domain timeout\n"); 1676 return ret; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static void rk3588_vop2_regsbak(struct vop2 *vop2) 1683 { 1684 u32 *base = vop2->regs; 1685 int i = 0; 1686 1687 /* 1688 * No need to backup HDR/DSC/GAMMA_LUT/BPP_LUT/MMU 1689 */ 1690 for (i = 0; i < (vop2->reg_len >> 2); i++) 1691 vop2->regsbak[i] = base[i]; 1692 } 1693 1694 static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) 1695 { 1696 struct crtc_state *cstate = &state->crtc_state; 1697 int i, j, port_mux = 0, total_used_layer = 0; 1698 u8 shift = 0; 1699 int layer_phy_id = 0; 1700 u32 layer_nr = 0; 1701 struct vop2_win_data *win_data; 1702 struct vop2_vp_plane_mask *plane_mask; 1703 1704 if (vop2->global_init) 1705 return; 1706 1707 /* OTP must enable at the first time, otherwise mirror layer register is error */ 1708 if (soc_is_rk3566()) 1709 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, 1710 OTP_WIN_EN_SHIFT, 1, false); 1711 1712 if (cstate->crtc->assign_plane) {/* dts assign plane */ 1713 u32 plane_mask; 1714 int primary_plane_id; 1715 1716 for (i = 0; i < vop2->data->nr_vps; i++) { 1717 plane_mask = cstate->crtc->vps[i].plane_mask; 1718 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1719 layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */ 1720 vop2->vp_plane_mask[i].attached_layers_nr = layer_nr; 1721 primary_plane_id = cstate->crtc->vps[i].primary_plane_id; 1722 if (primary_plane_id < 0) 1723 primary_plane_id = vop2_get_primary_plane(vop2, plane_mask); 1724 vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; 1725 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1726 1727 /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/ 1728 for (j = 0; j < layer_nr; j++) { 1729 vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; 1730 plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); 1731 } 1732 } 1733 } else {/* need soft assign plane mask */ 1734 /* find the first unplug devices and set it as main display */ 1735 int main_vp_index = -1; 1736 int active_vp_num = 0; 1737 1738 for (i = 0; i < vop2->data->nr_vps; i++) { 1739 if (cstate->crtc->vps[i].enable) 1740 active_vp_num++; 1741 } 1742 printf("VOP have %d active VP\n", active_vp_num); 1743 1744 if (soc_is_rk3566() && active_vp_num > 2) 1745 printf("ERROR: rk3566 only support 2 display output!!\n"); 1746 plane_mask = vop2->data->plane_mask; 1747 plane_mask += (active_vp_num - 1) * VOP2_VP_MAX; 1748 1749 for (i = 0; i < vop2->data->nr_vps; i++) { 1750 if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { 1751 vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/ 1752 main_vp_index = i; 1753 break; 1754 } 1755 } 1756 1757 /* if no find unplug devices, use vp0 as main display */ 1758 if (main_vp_index < 0) { 1759 main_vp_index = 0; 1760 vop2->vp_plane_mask[0] = plane_mask[0]; 1761 } 1762 1763 j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */ 1764 1765 /* init other display except main display */ 1766 for (i = 0; i < vop2->data->nr_vps; i++) { 1767 if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */ 1768 continue; 1769 vop2->vp_plane_mask[i] = plane_mask[j++]; 1770 } 1771 1772 /* store plane mask for vop2_fixup_dts */ 1773 for (i = 0; i < vop2->data->nr_vps; i++) { 1774 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1775 for (j = 0; j < layer_nr; j++) { 1776 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1777 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1778 } 1779 } 1780 } 1781 1782 if (vop2->version == VOP_VERSION_RK3588) 1783 rk3588_vop2_regsbak(vop2); 1784 else 1785 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); 1786 1787 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, 1788 OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); 1789 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1790 IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); 1791 1792 for (i = 0; i < vop2->data->nr_vps; i++) { 1793 printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); 1794 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) 1795 printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]); 1796 printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id); 1797 } 1798 1799 shift = 0; 1800 /* layer sel win id */ 1801 for (i = 0; i < vop2->data->nr_vps; i++) { 1802 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1803 for (j = 0; j < layer_nr; j++) { 1804 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1805 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); 1806 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, 1807 shift, win_data->layer_sel_win_id, false); 1808 shift += 4; 1809 } 1810 } 1811 1812 /* win sel port */ 1813 for (i = 0; i < vop2->data->nr_vps; i++) { 1814 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1815 for (j = 0; j < layer_nr; j++) { 1816 if (!vop2->vp_plane_mask[i].attached_layers[j]) 1817 continue; 1818 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1819 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); 1820 shift = win_data->win_sel_port_offset * 2; 1821 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, 1822 LAYER_SEL_PORT_SHIFT + shift, i, false); 1823 } 1824 } 1825 1826 /** 1827 * port mux config 1828 */ 1829 for (i = 0; i < vop2->data->nr_vps; i++) { 1830 shift = i * 4; 1831 if (vop2->vp_plane_mask[i].attached_layers_nr) { 1832 total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; 1833 port_mux = total_used_layer - 1; 1834 } else { 1835 port_mux = 8; 1836 } 1837 1838 if (i == vop2->data->nr_vps - 1) 1839 port_mux = vop2->data->nr_mixers; 1840 1841 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; 1842 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, 1843 PORT_MUX_SHIFT + shift, port_mux, false); 1844 } 1845 1846 if (vop2->version == VOP_VERSION_RK3568) 1847 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); 1848 1849 vop2->global_init = true; 1850 } 1851 1852 static int vop2_initial(struct vop2 *vop2, struct display_state *state) 1853 { 1854 struct crtc_state *cstate = &state->crtc_state; 1855 int ret; 1856 1857 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1858 ret = clk_set_defaults(cstate->dev); 1859 if (ret) 1860 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1861 1862 rockchip_vop2_gamma_lut_init(vop2, state); 1863 rockchip_vop2_cubic_lut_init(vop2, state); 1864 1865 return 0; 1866 } 1867 1868 /* 1869 * VOP2 have multi video ports. 1870 * video port ------- crtc 1871 */ 1872 static int rockchip_vop2_preinit(struct display_state *state) 1873 { 1874 struct crtc_state *cstate = &state->crtc_state; 1875 const struct vop2_data *vop2_data = cstate->crtc->data; 1876 1877 if (!rockchip_vop2) { 1878 rockchip_vop2 = calloc(1, sizeof(struct vop2)); 1879 if (!rockchip_vop2) 1880 return -ENOMEM; 1881 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); 1882 rockchip_vop2->regsbak = malloc(RK3568_MAX_REG); 1883 rockchip_vop2->reg_len = RK3568_MAX_REG; 1884 rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1885 if (rockchip_vop2->grf <= 0) 1886 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf); 1887 rockchip_vop2->version = vop2_data->version; 1888 rockchip_vop2->data = vop2_data; 1889 if (rockchip_vop2->version == VOP_VERSION_RK3588) { 1890 struct regmap *map; 1891 1892 rockchip_vop2->vop_grf = syscon_get_first_range(ROCKCHIP_SYSCON_VOP_GRF); 1893 if (rockchip_vop2->vop_grf <= 0) 1894 printf("%s: Get syscon vop_grf failed (ret=%p)\n", __func__, rockchip_vop2->vop_grf); 1895 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,vo1-grf"); 1896 rockchip_vop2->vo1_grf = regmap_get_range(map, 0); 1897 if (rockchip_vop2->vo1_grf <= 0) 1898 printf("%s: Get syscon vo1_grf failed (ret=%p)\n", __func__, rockchip_vop2->vo1_grf); 1899 rockchip_vop2->sys_pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); 1900 if (rockchip_vop2->sys_pmu <= 0) 1901 printf("%s: Get syscon sys_pmu failed (ret=%p)\n", __func__, rockchip_vop2->sys_pmu); 1902 } 1903 } 1904 1905 cstate->private = rockchip_vop2; 1906 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; 1907 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; 1908 1909 vop2_global_initial(rockchip_vop2, state); 1910 1911 return 0; 1912 } 1913 1914 /* 1915 * calc the dclk on rk3588 1916 * the available div of dclk is 1, 2, 4 1917 * 1918 */ 1919 static unsigned long vop2_calc_dclk(unsigned long child_clk, unsigned long max_dclk) 1920 { 1921 if (child_clk * 4 <= max_dclk) 1922 return child_clk * 4; 1923 else if (child_clk * 2 <= max_dclk) 1924 return child_clk * 2; 1925 else if (child_clk <= max_dclk) 1926 return child_clk; 1927 else 1928 return 0; 1929 } 1930 1931 /* 1932 * 4 pixclk/cycle on rk3588 1933 * RGB/eDP/HDMI: if_pixclk >= dclk_core 1934 * DP: dp_pixclk = dclk_out <= dclk_core 1935 * DSI: mipi_pixclk <= dclk_out <= dclk_core 1936 */ 1937 static unsigned long vop2_calc_cru_cfg(struct display_state *state, 1938 int *dclk_core_div, int *dclk_out_div, 1939 int *if_pixclk_div, int *if_dclk_div) 1940 { 1941 struct crtc_state *cstate = &state->crtc_state; 1942 struct connector_state *conn_state = &state->conn_state; 1943 struct drm_display_mode *mode = &conn_state->mode; 1944 struct vop2 *vop2 = cstate->private; 1945 unsigned long v_pixclk = mode->crtc_clock; 1946 unsigned long dclk_core_rate = v_pixclk >> 2; 1947 unsigned long dclk_rate = v_pixclk; 1948 unsigned long dclk_out_rate; 1949 u64 if_dclk_rate; 1950 u64 if_pixclk_rate; 1951 int output_type = conn_state->type; 1952 int output_mode = conn_state->output_mode; 1953 int K = 1; 1954 1955 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE && 1956 output_mode == ROCKCHIP_OUT_MODE_YUV420) { 1957 printf("Dual channel and YUV420 can't work together\n"); 1958 return -EINVAL; 1959 } 1960 1961 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE || 1962 output_mode == ROCKCHIP_OUT_MODE_YUV420) 1963 K = 2; 1964 1965 if (output_type == DRM_MODE_CONNECTOR_HDMIA) { 1966 /* 1967 * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate 1968 * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate 1969 */ 1970 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE || 1971 output_mode == ROCKCHIP_OUT_MODE_YUV420) { 1972 dclk_rate = dclk_rate >> 1; 1973 K = 2; 1974 } 1975 if (cstate->dsc_enable) { 1976 if_pixclk_rate = cstate->dsc_cds_clk_rate << 1; 1977 if_dclk_rate = cstate->dsc_cds_clk_rate; 1978 } else { 1979 if_pixclk_rate = (dclk_core_rate << 1) / K; 1980 if_dclk_rate = dclk_core_rate / K; 1981 } 1982 1983 if (v_pixclk > VOP2_MAX_DCLK_RATE) 1984 dclk_rate = vop2_calc_dclk(dclk_core_rate, vop2->data->vp_data->max_dclk); 1985 1986 if (!dclk_rate) { 1987 printf("DP if_pixclk_rate out of range(max_dclk: %d KHZ, dclk_core: %lld KHZ)\n", 1988 vop2->data->vp_data->max_dclk, if_pixclk_rate); 1989 return -EINVAL; 1990 } 1991 *if_pixclk_div = dclk_rate / if_pixclk_rate; 1992 *if_dclk_div = dclk_rate / if_dclk_rate; 1993 *dclk_core_div = dclk_rate / dclk_core_rate; 1994 printf("dclk:%lu,if_pixclk_div;%d,if_dclk_div:%d\n", 1995 dclk_rate, *if_pixclk_div, *if_dclk_div); 1996 } else if (output_type == DRM_MODE_CONNECTOR_eDP) { 1997 /* edp_pixclk = edp_dclk > dclk_core */ 1998 if_pixclk_rate = v_pixclk / K; 1999 if_dclk_rate = v_pixclk / K; 2000 dclk_rate = if_pixclk_rate * K; 2001 *dclk_core_div = dclk_rate / dclk_core_rate; 2002 *if_pixclk_div = dclk_rate / if_pixclk_rate; 2003 *if_dclk_div = *if_pixclk_div; 2004 } else if (output_type == DRM_MODE_CONNECTOR_DisplayPort) { 2005 dclk_out_rate = v_pixclk >> 2; 2006 dclk_out_rate = dclk_out_rate / K; 2007 2008 dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk); 2009 if (!dclk_rate) { 2010 printf("DP dclk_core out of range(max_dclk: %d KHZ, dclk_core: %ld KHZ)\n", 2011 vop2->data->vp_data->max_dclk, dclk_core_rate); 2012 return -EINVAL; 2013 } 2014 *dclk_out_div = dclk_rate / dclk_out_rate; 2015 *dclk_core_div = dclk_rate / dclk_core_rate; 2016 } else if (output_type == DRM_MODE_CONNECTOR_DSI) { 2017 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2018 K = 2; 2019 if (cstate->dsc_enable) 2020 /* dsc output is 96bit, dsi input is 192 bit */ 2021 if_pixclk_rate = cstate->dsc_cds_clk_rate >> 1; 2022 else 2023 if_pixclk_rate = dclk_core_rate / K; 2024 /* dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4 */ 2025 dclk_out_rate = dclk_core_rate / K; 2026 /* dclk_rate = N * dclk_core_rate N = (1,2,4 ), we get a little factor here */ 2027 dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk); 2028 if (!dclk_rate) { 2029 printf("MIPI dclk out of range(max_dclk: %d KHZ, dclk_rate: %ld KHZ)\n", 2030 vop2->data->vp_data->max_dclk, dclk_rate); 2031 return -EINVAL; 2032 } 2033 2034 if (cstate->dsc_enable) 2035 dclk_rate = dclk_rate >> 1; 2036 2037 *dclk_out_div = dclk_rate / dclk_out_rate; 2038 *dclk_core_div = dclk_rate / dclk_core_rate; 2039 *if_pixclk_div = 1; /*mipi pixclk == dclk_out*/ 2040 if (cstate->dsc_enable) 2041 *if_pixclk_div = dclk_out_rate / if_pixclk_rate; 2042 2043 } else if (output_type == DRM_MODE_CONNECTOR_DPI) { 2044 dclk_rate = v_pixclk; 2045 *dclk_core_div = dclk_rate / dclk_core_rate; 2046 } 2047 2048 *if_pixclk_div = ilog2(*if_pixclk_div); 2049 *if_dclk_div = ilog2(*if_dclk_div); 2050 *dclk_core_div = ilog2(*dclk_core_div); 2051 *dclk_out_div = ilog2(*dclk_out_div); 2052 2053 return dclk_rate; 2054 } 2055 2056 static int vop2_calc_dsc_clk(struct display_state *state) 2057 { 2058 struct connector_state *conn_state = &state->conn_state; 2059 struct drm_display_mode *mode = &conn_state->mode; 2060 struct crtc_state *cstate = &state->crtc_state; 2061 u64 v_pixclk = mode->clock; /* video timing pixclk */ 2062 u8 k = 1; 2063 2064 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2065 k = 2; 2066 2067 cstate->dsc_txp_clk_rate = v_pixclk; 2068 do_div(cstate->dsc_txp_clk_rate, (cstate->dsc_pixel_num * k)); 2069 2070 cstate->dsc_pxl_clk_rate = v_pixclk; 2071 do_div(cstate->dsc_pxl_clk_rate, (cstate->dsc_slice_num * k)); 2072 2073 /* dsc_cds = crtc_clock / (cds_dat_width / bits_per_pixel) 2074 * cds_dat_width = 96; 2075 * bits_per_pixel = [8-12]; 2076 * As cds clk is div from txp clk and only support 1/2/4 div, 2077 * so when txp_clk is equal to v_pixclk, we set dsc_cds = crtc_clock / 4, 2078 * otherwise dsc_cds = crtc_clock / 8; 2079 */ 2080 cstate->dsc_cds_clk_rate = v_pixclk / (cstate->dsc_txp_clk_rate == v_pixclk ? 4 : 8); 2081 2082 return 0; 2083 } 2084 2085 static unsigned long rk3588_vop2_if_cfg(struct display_state *state) 2086 { 2087 struct crtc_state *cstate = &state->crtc_state; 2088 struct connector_state *conn_state = &state->conn_state; 2089 struct drm_display_mode *mode = &conn_state->mode; 2090 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; 2091 struct vop2 *vop2 = cstate->private; 2092 u32 vp_offset = (cstate->crtc_id * 0x100); 2093 u16 hdisplay = mode->crtc_hdisplay; 2094 int output_if = conn_state->output_if; 2095 int if_pixclk_div = 0; 2096 int if_dclk_div = 0; 2097 unsigned long dclk_rate; 2098 u32 val; 2099 2100 if (output_if & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) { 2101 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0; 2102 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0; 2103 } else { 2104 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 2105 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 2106 } 2107 2108 if (cstate->dsc_enable) { 2109 int k = 1; 2110 2111 if (!vop2->data->nr_dscs) { 2112 printf("Unsupported DSC\n"); 2113 return 0; 2114 } 2115 2116 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2117 k = 2; 2118 2119 cstate->dsc_id = output_if & (VOP_OUTPUT_IF_MIPI0 | VOP_OUTPUT_IF_HDMI0) ? 0 : 1; 2120 cstate->dsc_slice_num = hdisplay / dsc_sink_cap->slice_width / k; 2121 cstate->dsc_pixel_num = cstate->dsc_slice_num > 4 ? 4 : cstate->dsc_slice_num; 2122 2123 vop2_calc_dsc_clk(state); 2124 printf("Enable DSC%d slice:%dx%d, slice num:%d\n", 2125 cstate->dsc_id, dsc_sink_cap->slice_width, 2126 dsc_sink_cap->slice_height, cstate->dsc_slice_num); 2127 } 2128 2129 dclk_rate = vop2_calc_cru_cfg(state, &cstate->dclk_core_div, &cstate->dclk_out_div, &if_pixclk_div, &if_dclk_div); 2130 2131 if (output_if & VOP_OUTPUT_IF_RGB) { 2132 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2133 4, false); 2134 } 2135 2136 if (output_if & VOP_OUTPUT_IF_BT1120) { 2137 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2138 3, false); 2139 } 2140 2141 if (output_if & VOP_OUTPUT_IF_BT656) { 2142 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2143 2, false); 2144 } 2145 2146 if (output_if & VOP_OUTPUT_IF_MIPI0) { 2147 if (cstate->crtc_id == 2) 2148 val = 0; 2149 else 2150 val = 1; 2151 2152 if (conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE) 2153 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2154 RK3588_MIPI_DSI0_MODE_SEL_SHIFT, 1, false); 2155 2156 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT, 2157 1, false); 2158 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 1, RK3588_MIPI0_MUX_SHIFT, val, false); 2159 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI0_PIXCLK_DIV_SHIFT, 2160 if_pixclk_div, false); 2161 2162 if (conn_state->hold_mode) { 2163 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2164 EN_MASK, EDPI_TE_EN, 1, false); 2165 2166 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2167 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); 2168 } 2169 } 2170 2171 if (output_if & VOP_OUTPUT_IF_MIPI1) { 2172 if (cstate->crtc_id == 2) 2173 val = 0; 2174 else if (cstate->crtc_id == 3) 2175 val = 1; 2176 else 2177 val = 3; /*VP1*/ 2178 if (conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE) 2179 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2180 RK3588_MIPI_DSI1_MODE_SEL_SHIFT, 1, false); 2181 2182 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT, 2183 1, false); 2184 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, MIPI1_MUX_SHIFT, 2185 val, false); 2186 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI1_PIXCLK_DIV_SHIFT, 2187 if_pixclk_div, false); 2188 2189 if (conn_state->hold_mode) { 2190 /* UNDO: RK3588 VP1->DSC1->DSI1 only can support soft TE mode */ 2191 if (vop2->version == VOP_VERSION_RK3588 && val == 3) 2192 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2193 EN_MASK, EDPI_TE_EN, 0, false); 2194 else 2195 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2196 EN_MASK, EDPI_TE_EN, 1, false); 2197 2198 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2199 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); 2200 } 2201 } 2202 2203 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2204 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 2205 MIPI_DUAL_EN_SHIFT, 1, false); 2206 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2207 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2208 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 2209 false); 2210 switch (conn_state->type) { 2211 case DRM_MODE_CONNECTOR_DisplayPort: 2212 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2213 RK3588_DP_DUAL_EN_SHIFT, 1, false); 2214 break; 2215 case DRM_MODE_CONNECTOR_eDP: 2216 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2217 RK3588_EDP_DUAL_EN_SHIFT, 1, false); 2218 break; 2219 case DRM_MODE_CONNECTOR_HDMIA: 2220 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2221 RK3588_HDMI_DUAL_EN_SHIFT, 1, false); 2222 break; 2223 case DRM_MODE_CONNECTOR_DSI: 2224 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2225 RK3568_MIPI_DUAL_EN_SHIFT, 1, false); 2226 break; 2227 default: 2228 break; 2229 } 2230 } 2231 2232 if (output_if & VOP_OUTPUT_IF_eDP0) { 2233 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP0_EN_SHIFT, 2234 1, false); 2235 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, 2236 cstate->crtc_id, false); 2237 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, 2238 if_dclk_div, false); 2239 2240 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, 2241 if_pixclk_div, false); 2242 2243 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2244 RK3588_GRF_EDP0_ENABLE_SHIFT, 1); 2245 } 2246 2247 if (output_if & VOP_OUTPUT_IF_eDP1) { 2248 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP1_EN_SHIFT, 2249 1, false); 2250 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, 2251 cstate->crtc_id, false); 2252 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, 2253 if_dclk_div, false); 2254 2255 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, 2256 if_pixclk_div, false); 2257 2258 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2259 RK3588_GRF_EDP1_ENABLE_SHIFT, 1); 2260 } 2261 2262 if (output_if & VOP_OUTPUT_IF_HDMI0) { 2263 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI0_EN_SHIFT, 2264 1, false); 2265 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, 2266 cstate->crtc_id, false); 2267 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, 2268 if_dclk_div, false); 2269 2270 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, 2271 if_pixclk_div, false); 2272 2273 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2274 RK3588_GRF_HDMITX0_ENABLE_SHIFT, 1); 2275 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, 2276 HDMI_SYNC_POL_MASK, 2277 HDMI0_SYNC_POL_SHIFT, val); 2278 } 2279 2280 if (output_if & VOP_OUTPUT_IF_HDMI1) { 2281 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI1_EN_SHIFT, 2282 1, false); 2283 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, 2284 cstate->crtc_id, false); 2285 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, 2286 if_dclk_div, false); 2287 2288 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, 2289 if_pixclk_div, false); 2290 2291 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2292 RK3588_GRF_HDMITX1_ENABLE_SHIFT, 1); 2293 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, 2294 HDMI_SYNC_POL_MASK, 2295 HDMI1_SYNC_POL_SHIFT, val); 2296 } 2297 2298 if (output_if & VOP_OUTPUT_IF_DP0) { 2299 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT, 2300 1, false); 2301 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP0_MUX_SHIFT, 2302 cstate->crtc_id, false); 2303 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, 2304 RK3588_DP0_PIN_POL_SHIFT, val, false); 2305 } 2306 2307 if (output_if & VOP_OUTPUT_IF_DP1) { 2308 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT, 2309 1, false); 2310 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP1_MUX_SHIFT, 2311 cstate->crtc_id, false); 2312 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, 2313 RK3588_DP1_PIN_POL_SHIFT, val, false); 2314 } 2315 2316 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, 2317 DCLK_CORE_DIV_SHIFT, cstate->dclk_core_div, false); 2318 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, 2319 DCLK_OUT_DIV_SHIFT, cstate->dclk_out_div, false); 2320 2321 return dclk_rate; 2322 } 2323 2324 static unsigned long rk3568_vop2_if_cfg(struct display_state *state) 2325 { 2326 struct crtc_state *cstate = &state->crtc_state; 2327 struct connector_state *conn_state = &state->conn_state; 2328 struct drm_display_mode *mode = &conn_state->mode; 2329 struct vop2 *vop2 = cstate->private; 2330 u32 vp_offset = (cstate->crtc_id * 0x100); 2331 bool dclk_inv; 2332 u32 val; 2333 2334 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 2335 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 2336 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 2337 2338 if (conn_state->output_if & VOP_OUTPUT_IF_RGB) { 2339 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 2340 1, false); 2341 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2342 RGB_MUX_SHIFT, cstate->crtc_id, false); 2343 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2344 GRF_RGB_DCLK_INV_SHIFT, dclk_inv); 2345 } 2346 2347 if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) { 2348 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 2349 1, false); 2350 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, 2351 BT1120_EN_SHIFT, 1, false); 2352 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2353 RGB_MUX_SHIFT, cstate->crtc_id, false); 2354 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2355 GRF_BT1120_CLK_INV_SHIFT, !dclk_inv); 2356 } 2357 2358 if (conn_state->output_if & VOP_OUTPUT_IF_BT656) { 2359 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, 2360 1, false); 2361 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2362 RGB_MUX_SHIFT, cstate->crtc_id, false); 2363 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2364 GRF_BT656_CLK_INV_SHIFT, !dclk_inv); 2365 } 2366 2367 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) { 2368 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, 2369 1, false); 2370 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2371 LVDS0_MUX_SHIFT, cstate->crtc_id, false); 2372 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2373 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 2374 } 2375 2376 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) { 2377 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, 2378 1, false); 2379 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2380 LVDS1_MUX_SHIFT, cstate->crtc_id, false); 2381 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2382 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 2383 } 2384 2385 if (conn_state->output_flags & 2386 (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE | 2387 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) { 2388 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2389 LVDS_DUAL_EN_SHIFT, 1, false); 2390 if (conn_state->output_flags & 2391 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2392 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2393 LVDS_DUAL_LEFT_RIGHT_EN_SHIFT, 1, 2394 false); 2395 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2396 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2397 LVDS_DUAL_SWAP_EN_SHIFT, 1, false); 2398 } 2399 2400 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) { 2401 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, 2402 1, false); 2403 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2404 MIPI0_MUX_SHIFT, cstate->crtc_id, false); 2405 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2406 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 2407 } 2408 2409 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI1) { 2410 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, 2411 1, false); 2412 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2413 MIPI1_MUX_SHIFT, cstate->crtc_id, false); 2414 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2415 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 2416 } 2417 2418 if (conn_state->output_flags & 2419 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2420 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 2421 MIPI_DUAL_EN_SHIFT, 1, false); 2422 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2423 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2424 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 2425 false); 2426 } 2427 2428 if (conn_state->output_if & VOP_OUTPUT_IF_eDP0) { 2429 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, 2430 1, false); 2431 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2432 EDP0_MUX_SHIFT, cstate->crtc_id, false); 2433 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2434 IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false); 2435 } 2436 2437 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) { 2438 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, 2439 1, false); 2440 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2441 HDMI0_MUX_SHIFT, cstate->crtc_id, false); 2442 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2443 IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false); 2444 vop2_mask_write(vop2, RK3568_DSP_IF_POL, 2445 IF_CRTL_HDMI_PIN_POL_MASK, 2446 IF_CRTL_HDMI_PIN_POL_SHIT, val, false); 2447 } 2448 2449 return mode->clock; 2450 } 2451 2452 static void vop2_post_color_swap(struct display_state *state) 2453 { 2454 struct crtc_state *cstate = &state->crtc_state; 2455 struct connector_state *conn_state = &state->conn_state; 2456 struct vop2 *vop2 = cstate->private; 2457 u32 vp_offset = (cstate->crtc_id * 0x100); 2458 u32 output_type = conn_state->type; 2459 u32 data_swap = 0; 2460 2461 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 2462 data_swap = DSP_RB_SWAP; 2463 2464 if (vop2->version == VOP_VERSION_RK3588 && 2465 (output_type == DRM_MODE_CONNECTOR_HDMIA || 2466 output_type == DRM_MODE_CONNECTOR_eDP) && 2467 (conn_state->bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 2468 conn_state->bus_format == MEDIA_BUS_FMT_YUV10_1X30)) 2469 data_swap |= DSP_RG_SWAP; 2470 2471 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 2472 DATA_SWAP_MASK, DATA_SWAP_SHIFT, data_swap, false); 2473 } 2474 2475 static void vop2_clk_set_parent(struct clk *clk, struct clk *parent) 2476 { 2477 int ret = 0; 2478 2479 if (parent->dev) 2480 ret = clk_set_parent(clk, parent); 2481 if (ret < 0) 2482 debug("failed to set %s as parent for %s\n", 2483 parent->dev->name, clk->dev->name); 2484 } 2485 2486 static ulong vop2_clk_set_rate(struct clk *clk, ulong rate) 2487 { 2488 int ret = 0; 2489 2490 if (clk->dev) 2491 ret = clk_set_rate(clk, rate); 2492 if (ret < 0) 2493 debug("failed to set %s rate %lu \n", clk->dev->name, rate); 2494 2495 return ret; 2496 } 2497 2498 static void vop2_calc_dsc_cru_cfg(struct display_state *state, 2499 int *dsc_txp_clk_div, int *dsc_pxl_clk_div, 2500 int *dsc_cds_clk_div, u64 dclk_rate) 2501 { 2502 struct crtc_state *cstate = &state->crtc_state; 2503 2504 *dsc_txp_clk_div = dclk_rate / cstate->dsc_txp_clk_rate; 2505 *dsc_pxl_clk_div = dclk_rate / cstate->dsc_pxl_clk_rate; 2506 *dsc_cds_clk_div = dclk_rate / cstate->dsc_cds_clk_rate; 2507 2508 *dsc_txp_clk_div = ilog2(*dsc_txp_clk_div); 2509 *dsc_pxl_clk_div = ilog2(*dsc_pxl_clk_div); 2510 *dsc_cds_clk_div = ilog2(*dsc_cds_clk_div); 2511 } 2512 2513 static void vop2_load_pps(struct display_state *state, struct vop2 *vop2, u8 dsc_id) 2514 { 2515 struct crtc_state *cstate = &state->crtc_state; 2516 struct drm_dsc_picture_parameter_set *pps = &cstate->pps; 2517 struct drm_dsc_picture_parameter_set config_pps; 2518 const struct vop2_data *vop2_data = vop2->data; 2519 const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id]; 2520 u32 *pps_val = (u32 *)&config_pps; 2521 u32 decoder_regs_offset = (dsc_id * 0x100); 2522 int i = 0; 2523 2524 memcpy(&config_pps, pps, sizeof(config_pps)); 2525 2526 if ((config_pps.pps_3 & 0xf) > dsc_data->max_linebuf_depth) { 2527 config_pps.pps_3 &= 0xf0; 2528 config_pps.pps_3 |= dsc_data->max_linebuf_depth; 2529 printf("DSC%d max_linebuf_depth is: %d, current set value is: %d\n", 2530 dsc_id, dsc_data->max_linebuf_depth, config_pps.pps_3 & 0xf); 2531 } 2532 2533 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 2534 config_pps.rc_range_parameters[i] = 2535 (pps->rc_range_parameters[i] >> 3 & 0x1f) | 2536 ((pps->rc_range_parameters[i] >> 14 & 0x3) << 5) | 2537 ((pps->rc_range_parameters[i] >> 0 & 0x7) << 7) | 2538 ((pps->rc_range_parameters[i] >> 8 & 0x3f) << 10); 2539 } 2540 2541 for (i = 0; i < ROCKCHIP_DSC_PPS_SIZE_BYTE / 4; i++) 2542 vop2_writel(vop2, RK3588_DSC_8K_PPS0_3 + decoder_regs_offset + i * 4, *pps_val++); 2543 } 2544 2545 static void vop2_dsc_enable(struct display_state *state, struct vop2 *vop2, u8 dsc_id, u64 dclk_rate) 2546 { 2547 struct connector_state *conn_state = &state->conn_state; 2548 struct drm_display_mode *mode = &conn_state->mode; 2549 struct crtc_state *cstate = &state->crtc_state; 2550 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; 2551 const struct vop2_data *vop2_data = vop2->data; 2552 const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id]; 2553 bool mipi_ds_mode = false; 2554 u8 dsc_interface_mode = 0; 2555 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 2556 u16 hdisplay = mode->crtc_hdisplay; 2557 u16 htotal = mode->crtc_htotal; 2558 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 2559 u16 vdisplay = mode->crtc_vdisplay; 2560 u16 vtotal = mode->crtc_vtotal; 2561 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 2562 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 2563 u16 vact_end = vact_st + vdisplay; 2564 u32 ctrl_regs_offset = (dsc_id * 0x30); 2565 u32 decoder_regs_offset = (dsc_id * 0x100); 2566 u32 backup_regs_offset = 0; 2567 int dsc_txp_clk_div = 0; 2568 int dsc_pxl_clk_div = 0; 2569 int dsc_cds_clk_div = 0; 2570 2571 if (!vop2->data->nr_dscs) { 2572 printf("Unsupported DSC\n"); 2573 return; 2574 } 2575 2576 if (cstate->dsc_slice_num > dsc_data->max_slice_num) 2577 printf("DSC%d supported max slice is: %d, current is: %d\n", 2578 dsc_data->id, dsc_data->max_slice_num, cstate->dsc_slice_num); 2579 2580 if (dsc_data->pd_id) { 2581 if (vop2_power_domain_on(vop2, dsc_data->pd_id)) 2582 printf("open dsc%d pd fail\n", dsc_id); 2583 } 2584 2585 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, EN_MASK, 2586 SCAN_TIMING_PARA_IMD_EN_SHIFT, 1, false); 2587 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PORT_SEL_MASK, 2588 DSC_PORT_SEL_SHIFT, cstate->crtc_id, false); 2589 if (conn_state->output_if & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) { 2590 dsc_interface_mode = VOP_DSC_IF_HDMI; 2591 } else { 2592 mipi_ds_mode = !!(conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE); 2593 if (mipi_ds_mode) 2594 dsc_interface_mode = VOP_DSC_IF_MIPI_DS_MODE; 2595 else 2596 dsc_interface_mode = VOP_DSC_IF_MIPI_VIDEO_MODE; 2597 } 2598 2599 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2600 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, 2601 DSC_MAN_MODE_SHIFT, 0, false); 2602 else 2603 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, 2604 DSC_MAN_MODE_SHIFT, 1, false); 2605 2606 vop2_calc_dsc_cru_cfg(state, &dsc_txp_clk_div, &dsc_pxl_clk_div, &dsc_cds_clk_div, dclk_rate); 2607 2608 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_INTERFACE_MODE_MASK, 2609 DSC_INTERFACE_MODE_SHIFT, dsc_interface_mode, false); 2610 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PIXEL_NUM_MASK, 2611 DSC_PIXEL_NUM_SHIFT, cstate->dsc_pixel_num >> 1, false); 2612 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_TXP_CLK_DIV_MASK, 2613 DSC_TXP_CLK_DIV_SHIFT, dsc_txp_clk_div, false); 2614 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PXL_CLK_DIV_MASK, 2615 DSC_PXL_CLK_DIV_SHIFT, dsc_pxl_clk_div, false); 2616 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, 2617 DSC_CDS_CLK_DIV_SHIFT, dsc_cds_clk_div, false); 2618 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, EN_MASK, 2619 DSC_SCAN_EN_SHIFT, !mipi_ds_mode, false); 2620 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, 2621 DSC_HALT_EN_SHIFT, mipi_ds_mode, false); 2622 2623 if (!mipi_ds_mode) { 2624 u16 dsc_hsync, dsc_htotal, dsc_hact_st, dsc_hact_end; 2625 u32 target_bpp = dsc_sink_cap->target_bits_per_pixel_x16; 2626 u64 dsc_cds_rate = cstate->dsc_cds_clk_rate; 2627 u32 v_pixclk_mhz = mode->crtc_clock / 1000; /* video timing pixclk */ 2628 u32 dly_num, dsc_cds_rate_mhz, val = 0; 2629 int k = 1; 2630 2631 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2632 k = 2; 2633 2634 if (target_bpp >> 4 < dsc_data->min_bits_per_pixel) 2635 printf("Unsupported bpp less than: %d\n", dsc_data->min_bits_per_pixel); 2636 2637 /* 2638 * dly_num = delay_line_num * T(one-line) / T (dsc_cds) 2639 * T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz 2640 * T (dsc_cds) = 1 / dsc_cds_rate_mhz 2641 * delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay 2642 * delay_line_num = 4 - BPP / 8 2643 * = (64 - target_bpp / 8) / 16 2644 * 2645 * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16; 2646 */ 2647 do_div(dsc_cds_rate, 1000000); /* hz to Mhz */ 2648 dsc_cds_rate_mhz = dsc_cds_rate; 2649 dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16; 2650 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK, 2651 DSC_INIT_DLY_MODE_SHIFT, 0, false); 2652 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK, 2653 DSC_INIT_DLY_NUM_SHIFT, dly_num, false); 2654 2655 dsc_hsync = hsync_len / 2; 2656 /* 2657 * htotal / dclk_core = dsc_htotal /cds_clk 2658 * 2659 * dclk_core = DCLK / (1 << dclk_core->div_val) 2660 * cds_clk = txp_clk / (1 << dsc_cds_clk->div_val) 2661 * txp_clk = DCLK / (1 << dsc_txp_clk->div_val) 2662 * 2663 * dsc_htotal = htotal * (1 << dclk_core->div_val) / 2664 * ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val)) 2665 */ 2666 dsc_htotal = htotal * (1 << cstate->dclk_core_div) / 2667 ((1 << dsc_txp_clk_div) * (1 << dsc_cds_clk_div)); 2668 val = dsc_htotal << 16 | dsc_hsync; 2669 vop2_mask_write(vop2, RK3588_DSC_8K_HTOTAL_HS_END + ctrl_regs_offset, DSC_HTOTAL_PW_MASK, 2670 DSC_HTOTAL_PW_SHIFT, val, false); 2671 2672 dsc_hact_st = hact_st / 2; 2673 dsc_hact_end = (hdisplay / k * target_bpp >> 4) / 24 + dsc_hact_st; 2674 val = dsc_hact_end << 16 | dsc_hact_st; 2675 vop2_mask_write(vop2, RK3588_DSC_8K_HACT_ST_END + ctrl_regs_offset, DSC_HACT_ST_END_MASK, 2676 DSC_HACT_ST_END_SHIFT, val, false); 2677 2678 vop2_mask_write(vop2, RK3588_DSC_8K_VTOTAL_VS_END + ctrl_regs_offset, DSC_VTOTAL_PW_MASK, 2679 DSC_VTOTAL_PW_SHIFT, vtotal << 16 | vsync_len, false); 2680 vop2_mask_write(vop2, RK3588_DSC_8K_VACT_ST_END + ctrl_regs_offset, DSC_VACT_ST_END_MASK, 2681 DSC_VACT_ST_END_SHIFT, vact_end << 16 | vact_st, false); 2682 } 2683 2684 vop2_mask_write(vop2, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK, 2685 RST_DEASSERT_SHIFT, 1, false); 2686 udelay(10); 2687 /* read current dsc core register and backup to regsbak */ 2688 backup_regs_offset = RK3588_DSC_8K_CTRL0; 2689 vop2->regsbak[backup_regs_offset >> 2] = vop2_readl(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset); 2690 2691 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2692 DSC_EN_SHIFT, 1, false); 2693 vop2_load_pps(state, vop2, dsc_id); 2694 2695 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2696 DSC_RBIT_SHIFT, 1, false); 2697 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2698 DSC_RBYT_SHIFT, 0, false); 2699 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2700 DSC_FLAL_SHIFT, 1, false); 2701 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2702 DSC_MER_SHIFT, 1, false); 2703 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2704 DSC_EPB_SHIFT, 0, false); 2705 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2706 DSC_EPL_SHIFT, 1, false); 2707 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2708 DSC_NSLC_SHIFT, ilog2(cstate->dsc_slice_num), false); 2709 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2710 DSC_SBO_SHIFT, 1, false); 2711 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2712 DSC_IFEP_SHIFT, dsc_sink_cap->version_minor == 2 ? 1 : 0, false); 2713 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2714 DSC_PPS_UPD_SHIFT, 1, false); 2715 2716 printf("DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n", 2717 dsc_id, 2718 cstate->dsc_txp_clk_rate, dsc_txp_clk_div, 2719 cstate->dsc_pxl_clk_rate, dsc_pxl_clk_div, 2720 cstate->dsc_cds_clk_rate, dsc_cds_clk_div); 2721 } 2722 2723 static bool is_extend_pll(struct display_state *state, struct udevice **clk_dev) 2724 { 2725 struct crtc_state *cstate = &state->crtc_state; 2726 struct vop2 *vop2 = cstate->private; 2727 struct udevice *vp_dev, *dev; 2728 struct ofnode_phandle_args args; 2729 char vp_name[10]; 2730 int ret; 2731 2732 if (vop2->version != VOP_VERSION_RK3588) 2733 return false; 2734 2735 sprintf(vp_name, "port@%d", cstate->crtc_id); 2736 if (uclass_find_device_by_name(UCLASS_VIDEO_CRTC, vp_name, &vp_dev)) { 2737 debug("warn: can't get vp device\n"); 2738 return false; 2739 } 2740 2741 ret = dev_read_phandle_with_args(vp_dev, "assigned-clock-parents", "#clock-cells", 0, 2742 0, &args); 2743 if (ret) { 2744 debug("assigned-clock-parents's node not define\n"); 2745 return false; 2746 } 2747 2748 if (uclass_find_device_by_ofnode(UCLASS_CLK, args.node, &dev)) { 2749 debug("warn: can't get clk device\n"); 2750 return false; 2751 } 2752 2753 if (!strcmp(dev->name, "hdmiphypll_clk0") || !strcmp(dev->name, "hdmiphypll_clk1")) { 2754 printf("%s: clk dev :%s: vp port:%s\n", __func__, dev->name, vp_dev->name); 2755 if (clk_dev) 2756 *clk_dev = dev; 2757 return true; 2758 } 2759 2760 return false; 2761 } 2762 2763 static int rockchip_vop2_init(struct display_state *state) 2764 { 2765 struct crtc_state *cstate = &state->crtc_state; 2766 struct rockchip_vp *vp = &cstate->crtc->vps[cstate->crtc_id]; 2767 struct connector_state *conn_state = &state->conn_state; 2768 struct drm_display_mode *mode = &conn_state->mode; 2769 struct vop2 *vop2 = cstate->private; 2770 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 2771 u16 hdisplay = mode->crtc_hdisplay; 2772 u16 htotal = mode->crtc_htotal; 2773 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 2774 u16 hact_end = hact_st + hdisplay; 2775 u16 vdisplay = mode->crtc_vdisplay; 2776 u16 vtotal = mode->crtc_vtotal; 2777 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 2778 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 2779 u16 vact_end = vact_st + vdisplay; 2780 bool yuv_overlay = false; 2781 u32 vp_offset = (cstate->crtc_id * 0x100); 2782 u32 line_flag_offset = (cstate->crtc_id * 4); 2783 u32 val, act_end; 2784 u8 dither_down_en = 0; 2785 u8 pre_dither_down_en = 0; 2786 u8 dclk_div_factor = 0; 2787 char output_type_name[30] = {0}; 2788 char dclk_name[9]; 2789 struct clk dclk; 2790 struct clk hdmi0_phy_pll; 2791 struct clk hdmi1_phy_pll; 2792 struct clk hdmi_phy_pll; 2793 struct udevice *disp_dev; 2794 unsigned long dclk_rate; 2795 int ret; 2796 2797 printf("VOP update mode to: %dx%d%s%d, type:%s for VP%d\n", 2798 mode->crtc_hdisplay, mode->crtc_vdisplay, 2799 mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 2800 mode->vrefresh, 2801 get_output_if_name(conn_state->output_if, output_type_name), 2802 cstate->crtc_id); 2803 2804 if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) { 2805 cstate->splice_mode = true; 2806 cstate->splice_crtc_id = vop2->data->vp_data[cstate->crtc_id].splice_vp_id; 2807 if (!cstate->splice_crtc_id) { 2808 printf("%s: Splice mode is unsupported by vp%d\n", 2809 __func__, cstate->crtc_id); 2810 return -EINVAL; 2811 } 2812 2813 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, EN_MASK, 2814 PORT_MERGE_EN_SHIFT, 1, false); 2815 } 2816 2817 vop2_initial(vop2, state); 2818 if (vop2->version == VOP_VERSION_RK3588) 2819 dclk_rate = rk3588_vop2_if_cfg(state); 2820 else 2821 dclk_rate = rk3568_vop2_if_cfg(state); 2822 2823 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 2824 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT)) 2825 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 2826 2827 vop2_post_color_swap(state); 2828 2829 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, 2830 OUT_MODE_SHIFT, conn_state->output_mode, false); 2831 2832 switch (conn_state->bus_format) { 2833 case MEDIA_BUS_FMT_RGB565_1X16: 2834 dither_down_en = 1; 2835 break; 2836 case MEDIA_BUS_FMT_RGB666_1X18: 2837 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 2838 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 2839 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 2840 dither_down_en = 1; 2841 break; 2842 case MEDIA_BUS_FMT_YUV8_1X24: 2843 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2844 dither_down_en = 0; 2845 pre_dither_down_en = 1; 2846 break; 2847 case MEDIA_BUS_FMT_YUV10_1X30: 2848 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2849 case MEDIA_BUS_FMT_RGB888_1X24: 2850 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 2851 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 2852 default: 2853 dither_down_en = 0; 2854 pre_dither_down_en = 0; 2855 break; 2856 } 2857 2858 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 2859 pre_dither_down_en = 0; 2860 else 2861 pre_dither_down_en = 1; 2862 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2863 DITHER_DOWN_EN_SHIFT, dither_down_en, false); 2864 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2865 PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false); 2866 2867 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0; 2868 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, 2869 yuv_overlay, false); 2870 2871 cstate->yuv_overlay = yuv_overlay; 2872 2873 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, 2874 (htotal << 16) | hsync_len); 2875 val = hact_st << 16; 2876 val |= hact_end; 2877 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); 2878 val = vact_st << 16; 2879 val |= vact_end; 2880 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); 2881 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 2882 u16 vact_st_f1 = vtotal + vact_st + 1; 2883 u16 vact_end_f1 = vact_st_f1 + vdisplay; 2884 2885 val = vact_st_f1 << 16 | vact_end_f1; 2886 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, 2887 val); 2888 2889 val = vtotal << 16 | (vtotal + vsync_len); 2890 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); 2891 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2892 INTERLACE_EN_SHIFT, 1, false); 2893 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2894 DSP_FILED_POL, 1, false); 2895 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2896 P2I_EN_SHIFT, 1, false); 2897 vtotal += vtotal + 1; 2898 act_end = vact_end_f1; 2899 } else { 2900 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2901 INTERLACE_EN_SHIFT, 0, false); 2902 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2903 P2I_EN_SHIFT, 0, false); 2904 act_end = vact_end; 2905 } 2906 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, 2907 (vtotal << 16) | vsync_len); 2908 2909 if (vop2->version == VOP_VERSION_RK3568) { 2910 if (mode->flags & DRM_MODE_FLAG_DBLCLK || 2911 conn_state->output_if & VOP_OUTPUT_IF_BT656) 2912 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2913 CORE_DCLK_DIV_EN_SHIFT, 1, false); 2914 else 2915 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2916 CORE_DCLK_DIV_EN_SHIFT, 0, false); 2917 } 2918 2919 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) 2920 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2921 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0x3, false); 2922 else 2923 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2924 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0, false); 2925 2926 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, 2927 OVL_MODE_SEL_SHIFT + cstate->crtc_id, yuv_overlay, false); 2928 2929 if (yuv_overlay) 2930 val = 0x20010200; 2931 else 2932 val = 0; 2933 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); 2934 if (cstate->splice_mode) { 2935 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, 2936 OVL_MODE_SEL_SHIFT + cstate->splice_crtc_id, 2937 yuv_overlay, false); 2938 vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val); 2939 } 2940 2941 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2942 POST_DSP_OUT_R2Y_SHIFT, yuv_overlay, false); 2943 2944 if (vp->xmirror_en) 2945 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2946 DSP_X_MIR_EN_SHIFT, 1, false); 2947 2948 vop2_tv_config_update(state, vop2); 2949 vop2_post_config(state, vop2); 2950 2951 if (cstate->dsc_enable) { 2952 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2953 vop2_dsc_enable(state, vop2, 0, dclk_rate); 2954 vop2_dsc_enable(state, vop2, 1, dclk_rate); 2955 } else { 2956 vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate); 2957 } 2958 } 2959 2960 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); 2961 ret = clk_get_by_name(cstate->dev, dclk_name, &dclk); 2962 if (ret) { 2963 printf("%s: Failed to get dclk ret=%d\n", __func__, ret); 2964 return ret; 2965 } 2966 2967 ret = uclass_get_device_by_name(UCLASS_VIDEO, "display-subsystem", &disp_dev); 2968 if (!ret) { 2969 ret = clk_get_by_name(disp_dev, "hdmi0_phy_pll", &hdmi0_phy_pll); 2970 if (ret) 2971 debug("%s: hdmi0_phy_pll may not define\n", __func__); 2972 ret = clk_get_by_name(disp_dev, "hdmi1_phy_pll", &hdmi1_phy_pll); 2973 if (ret) 2974 debug("%s: hdmi1_phy_pll may not define\n", __func__); 2975 } else { 2976 hdmi0_phy_pll.dev = NULL; 2977 hdmi1_phy_pll.dev = NULL; 2978 debug("%s: Faile to find display-subsystem node\n", __func__); 2979 } 2980 2981 if (mode->crtc_clock < VOP2_MAX_DCLK_RATE) { 2982 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) 2983 vop2_clk_set_parent(&dclk, &hdmi0_phy_pll); 2984 else if (conn_state->output_if & VOP_OUTPUT_IF_HDMI1) 2985 vop2_clk_set_parent(&dclk, &hdmi1_phy_pll); 2986 2987 /* 2988 * uboot clk driver won't set dclk parent's rate when use 2989 * hdmi phypll as dclk source. 2990 * So set dclk rate is meaningless. Set hdmi phypll rate 2991 * directly. 2992 */ 2993 if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI0) && hdmi0_phy_pll.dev) { 2994 ret = vop2_clk_set_rate(&hdmi0_phy_pll, dclk_rate * 1000); 2995 } else if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI1) && hdmi1_phy_pll.dev) { 2996 ret = vop2_clk_set_rate(&hdmi1_phy_pll, dclk_rate * 1000); 2997 } else { 2998 if (is_extend_pll(state, &hdmi_phy_pll.dev)) 2999 ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000); 3000 else 3001 ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000); 3002 } 3003 } else { 3004 if (is_extend_pll(state, &hdmi_phy_pll.dev)) 3005 ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000); 3006 else 3007 ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000); 3008 } 3009 3010 if (IS_ERR_VALUE(ret)) { 3011 printf("%s: Failed to set vp%d dclk[%ld KHZ] ret=%d\n", 3012 __func__, cstate->crtc_id, dclk_rate, ret); 3013 return ret; 3014 } else { 3015 dclk_div_factor = mode->clock / dclk_rate; 3016 mode->crtc_clock = ret * dclk_div_factor / 1000; 3017 printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock); 3018 } 3019 3020 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, 3021 RK3568_DSP_LINE_FLAG_NUM0_SHIFT, act_end, false); 3022 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, 3023 RK3568_DSP_LINE_FLAG_NUM1_SHIFT, act_end, false); 3024 3025 return 0; 3026 } 3027 3028 static void vop2_setup_scale(struct vop2 *vop2, struct vop2_win_data *win, 3029 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 3030 uint32_t dst_h) 3031 { 3032 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3033 uint16_t hscl_filter_mode, vscl_filter_mode; 3034 uint8_t gt2 = 0, gt4 = 0; 3035 uint32_t xfac = 0, yfac = 0; 3036 uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC; 3037 uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL; 3038 uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL; 3039 uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL; 3040 u32 win_offset = win->reg_offset; 3041 3042 if (src_h >= (4 * dst_h)) 3043 gt4 = 1; 3044 else if (src_h >= (2 * dst_h)) 3045 gt2 = 1; 3046 3047 if (gt4) 3048 src_h >>= 2; 3049 else if (gt2) 3050 src_h >>= 1; 3051 3052 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3053 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3054 3055 if (yrgb_hor_scl_mode == SCALE_UP) 3056 hscl_filter_mode = hsu_filter_mode; 3057 else 3058 hscl_filter_mode = hsd_filter_mode; 3059 3060 if (yrgb_ver_scl_mode == SCALE_UP) 3061 vscl_filter_mode = vsu_filter_mode; 3062 else 3063 vscl_filter_mode = vsd_filter_mode; 3064 3065 /* 3066 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 3067 * at scale down mode 3068 */ 3069 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 3070 printf("win dst_w[%d] should align as 2 pixel\n", dst_w); 3071 dst_w += 1; 3072 } 3073 3074 xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w); 3075 yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h); 3076 3077 if (win->type == CLUSTER_LAYER) { 3078 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset, 3079 yfac << 16 | xfac); 3080 3081 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3082 YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, gt2, false); 3083 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3084 YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, gt4, false); 3085 3086 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3087 YRGB_XSCL_MODE_MASK, CLUSTER_YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 3088 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3089 YRGB_YSCL_MODE_MASK, CLUSTER_YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 3090 3091 } else { 3092 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset, 3093 yfac << 16 | xfac); 3094 3095 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3096 YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false); 3097 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3098 YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false); 3099 3100 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3101 YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 3102 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3103 YRGB_YSCL_MODE_MASK, YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 3104 3105 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3106 YRGB_XSCL_FILTER_MODE_MASK, YRGB_XSCL_FILTER_MODE_SHIFT, 3107 hscl_filter_mode, false); 3108 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3109 YRGB_YSCL_FILTER_MODE_MASK, YRGB_YSCL_FILTER_MODE_SHIFT, 3110 vscl_filter_mode, false); 3111 } 3112 } 3113 3114 static void vop2_axi_config(struct vop2 *vop2, struct vop2_win_data *win) 3115 { 3116 u32 win_offset = win->reg_offset; 3117 3118 if (win->type == CLUSTER_LAYER) { 3119 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, CLUSTER_AXI_ID_MASK, 3120 CLUSTER_AXI_ID_SHIFT, win->axi_id, false); 3121 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_YRGB_ID_MASK, 3122 CLUSTER_AXI_YRGB_ID_SHIFT, win->axi_yrgb_id, false); 3123 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_UV_ID_MASK, 3124 CLUSTER_AXI_UV_ID_SHIFT, win->axi_uv_id, false); 3125 } else { 3126 vop2_mask_write(vop2, RK3568_ESMART0_AXI_CTRL + win_offset, ESMART_AXI_ID_MASK, 3127 ESMART_AXI_ID_SHIFT, win->axi_id, false); 3128 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_YRGB_ID_MASK, 3129 ESMART_AXI_YRGB_ID_SHIFT, win->axi_yrgb_id, false); 3130 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_UV_ID_MASK, 3131 ESMART_AXI_UV_ID_SHIFT, win->axi_uv_id, false); 3132 } 3133 } 3134 3135 static void vop2_set_cluster_win(struct display_state *state, struct vop2_win_data *win) 3136 { 3137 struct crtc_state *cstate = &state->crtc_state; 3138 struct connector_state *conn_state = &state->conn_state; 3139 struct drm_display_mode *mode = &conn_state->mode; 3140 struct vop2 *vop2 = cstate->private; 3141 int src_w = cstate->src_rect.w; 3142 int src_h = cstate->src_rect.h; 3143 int crtc_x = cstate->crtc_rect.x; 3144 int crtc_y = cstate->crtc_rect.y; 3145 int crtc_w = cstate->crtc_rect.w; 3146 int crtc_h = cstate->crtc_rect.h; 3147 int xvir = cstate->xvir; 3148 int y_mirror = 0; 3149 int csc_mode; 3150 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 3151 /* offset of the right window in splice mode */ 3152 u32 splice_pixel_offset = 0; 3153 u32 splice_yrgb_offset = 0; 3154 u32 win_offset = win->reg_offset; 3155 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3156 3157 if (win->splice_mode_right) { 3158 src_w = cstate->right_src_rect.w; 3159 src_h = cstate->right_src_rect.h; 3160 crtc_x = cstate->right_crtc_rect.x; 3161 crtc_y = cstate->right_crtc_rect.y; 3162 crtc_w = cstate->right_crtc_rect.w; 3163 crtc_h = cstate->right_crtc_rect.h; 3164 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; 3165 splice_yrgb_offset = splice_pixel_offset * (state->logo.bpp >> 3); 3166 cfg_done = CFG_DONE_EN | BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3167 } 3168 3169 act_info = (src_h - 1) << 16; 3170 act_info |= (src_w - 1) & 0xffff; 3171 3172 dsp_info = (crtc_h - 1) << 16; 3173 dsp_info |= (crtc_w - 1) & 0xffff; 3174 3175 dsp_stx = crtc_x; 3176 dsp_sty = crtc_y; 3177 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 3178 3179 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 3180 y_mirror = 1; 3181 else 3182 y_mirror = 0; 3183 3184 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); 3185 3186 if (vop2->version == VOP_VERSION_RK3588) 3187 vop2_axi_config(vop2, win); 3188 3189 if (y_mirror) 3190 printf("WARN: y mirror is unsupported by cluster window\n"); 3191 3192 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, 3193 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 3194 false); 3195 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_VIR + win_offset, xvir); 3196 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_YRGB_MST + win_offset, 3197 cstate->dma_addr + splice_yrgb_offset); 3198 3199 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_ACT_INFO + win_offset, act_info); 3200 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_INFO + win_offset, dsp_info); 3201 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_ST + win_offset, dsp_st); 3202 3203 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false); 3204 3205 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 3206 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, 3207 CLUSTER_RGB2YUV_EN_SHIFT, 3208 is_yuv_output(conn_state->bus_format), false); 3209 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK, 3210 CLUSTER_CSC_MODE_SHIFT, csc_mode, false); 3211 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false); 3212 3213 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3214 } 3215 3216 static void vop2_set_smart_win(struct display_state *state, struct vop2_win_data *win) 3217 { 3218 struct crtc_state *cstate = &state->crtc_state; 3219 struct connector_state *conn_state = &state->conn_state; 3220 struct drm_display_mode *mode = &conn_state->mode; 3221 struct vop2 *vop2 = cstate->private; 3222 int src_w = cstate->src_rect.w; 3223 int src_h = cstate->src_rect.h; 3224 int crtc_x = cstate->crtc_rect.x; 3225 int crtc_y = cstate->crtc_rect.y; 3226 int crtc_w = cstate->crtc_rect.w; 3227 int crtc_h = cstate->crtc_rect.h; 3228 int xvir = cstate->xvir; 3229 int y_mirror = 0; 3230 int csc_mode; 3231 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 3232 /* offset of the right window in splice mode */ 3233 u32 splice_pixel_offset = 0; 3234 u32 splice_yrgb_offset = 0; 3235 u32 win_offset = win->reg_offset; 3236 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3237 3238 if (win->splice_mode_right) { 3239 src_w = cstate->right_src_rect.w; 3240 src_h = cstate->right_src_rect.h; 3241 crtc_x = cstate->right_crtc_rect.x; 3242 crtc_y = cstate->right_crtc_rect.y; 3243 crtc_w = cstate->right_crtc_rect.w; 3244 crtc_h = cstate->right_crtc_rect.h; 3245 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; 3246 splice_yrgb_offset = splice_pixel_offset * (state->logo.bpp >> 3); 3247 cfg_done = CFG_DONE_EN | BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3248 } 3249 3250 /* 3251 * This is workaround solution for IC design: 3252 * esmart can't support scale down when actual_w % 16 == 1. 3253 */ 3254 if (src_w > crtc_w && (src_w & 0xf) == 1) { 3255 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); 3256 src_w -= 1; 3257 } 3258 3259 act_info = (src_h - 1) << 16; 3260 act_info |= (src_w - 1) & 0xffff; 3261 3262 dsp_info = (crtc_h - 1) << 16; 3263 dsp_info |= (crtc_w - 1) & 0xffff; 3264 3265 dsp_stx = crtc_x; 3266 dsp_sty = crtc_y; 3267 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 3268 3269 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 3270 y_mirror = 1; 3271 else 3272 y_mirror = 0; 3273 3274 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); 3275 3276 if (vop2->version == VOP_VERSION_RK3588) 3277 vop2_axi_config(vop2, win); 3278 3279 if (y_mirror) 3280 cstate->dma_addr += (src_h - 1) * xvir * 4; 3281 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, 3282 YMIRROR_EN_SHIFT, y_mirror, false); 3283 3284 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3285 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 3286 false); 3287 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); 3288 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, 3289 cstate->dma_addr + splice_yrgb_offset); 3290 3291 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, 3292 act_info); 3293 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, 3294 dsp_info); 3295 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); 3296 3297 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, 3298 WIN_EN_SHIFT, 1, false); 3299 3300 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 3301 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, 3302 RGB2YUV_EN_SHIFT, 3303 is_yuv_output(conn_state->bus_format), false); 3304 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, 3305 CSC_MODE_SHIFT, csc_mode, false); 3306 3307 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3308 } 3309 3310 static void vop2_calc_display_rect_for_splice(struct display_state *state) 3311 { 3312 struct crtc_state *cstate = &state->crtc_state; 3313 struct connector_state *conn_state = &state->conn_state; 3314 struct drm_display_mode *mode = &conn_state->mode; 3315 struct display_rect *src_rect = &cstate->src_rect; 3316 struct display_rect *dst_rect = &cstate->crtc_rect; 3317 struct display_rect left_src, left_dst, right_src, right_dst; 3318 u16 half_hdisplay = mode->crtc_hdisplay >> 1; 3319 int left_src_w, left_dst_w, right_dst_w; 3320 3321 left_dst_w = min_t(u16, half_hdisplay, dst_rect->x + dst_rect->w) - dst_rect->x; 3322 if (left_dst_w < 0) 3323 left_dst_w = 0; 3324 right_dst_w = dst_rect->w - left_dst_w; 3325 3326 if (!right_dst_w) 3327 left_src_w = src_rect->w; 3328 else 3329 left_src_w = src_rect->x + src_rect->w - src_rect->w / 2; 3330 3331 left_src.x = src_rect->x; 3332 left_src.w = left_src_w; 3333 left_dst.x = dst_rect->x; 3334 left_dst.w = left_dst_w; 3335 right_src.x = left_src.x + left_src.w; 3336 right_src.w = src_rect->x + src_rect->w - left_src.x - left_src.w; 3337 right_dst.x = dst_rect->x + left_dst_w - half_hdisplay; 3338 right_dst.w = right_dst_w; 3339 3340 left_src.y = src_rect->y; 3341 left_src.h = src_rect->h; 3342 left_dst.y = dst_rect->y; 3343 left_dst.h = dst_rect->h; 3344 right_src.y = src_rect->y; 3345 right_src.h = src_rect->h; 3346 right_dst.y = dst_rect->y; 3347 right_dst.h = dst_rect->h; 3348 3349 memcpy(&cstate->src_rect, &left_src, sizeof(struct display_rect)); 3350 memcpy(&cstate->crtc_rect, &left_dst, sizeof(struct display_rect)); 3351 memcpy(&cstate->right_src_rect, &right_src, sizeof(struct display_rect)); 3352 memcpy(&cstate->right_crtc_rect, &right_dst, sizeof(struct display_rect)); 3353 } 3354 3355 static int rockchip_vop2_set_plane(struct display_state *state) 3356 { 3357 struct crtc_state *cstate = &state->crtc_state; 3358 struct vop2 *vop2 = cstate->private; 3359 struct vop2_win_data *win_data; 3360 struct vop2_win_data *splice_win_data; 3361 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 3362 char plane_name[10] = {0}; 3363 3364 if (cstate->crtc_rect.w > cstate->max_output.width) { 3365 printf("ERROR: output w[%d] exceeded max width[%d]\n", 3366 cstate->crtc_rect.w, cstate->max_output.width); 3367 return -EINVAL; 3368 } 3369 3370 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); 3371 if (!win_data) { 3372 printf("invalid win id %d\n", primary_plane_id); 3373 return -ENODEV; 3374 } 3375 3376 if (vop2->version == VOP_VERSION_RK3588) { 3377 if (vop2_power_domain_on(vop2, win_data->pd_id)) 3378 printf("open vp%d plane pd fail\n", cstate->crtc_id); 3379 } 3380 3381 if (cstate->splice_mode) { 3382 if (win_data->splice_win_id) { 3383 splice_win_data = vop2_find_win_by_phys_id(vop2, win_data->splice_win_id); 3384 splice_win_data->splice_mode_right = true; 3385 3386 if (vop2_power_domain_on(vop2, splice_win_data->pd_id)) 3387 printf("splice mode: open vp%d plane pd fail\n", cstate->splice_crtc_id); 3388 3389 vop2_calc_display_rect_for_splice(state); 3390 if (win_data->type == CLUSTER_LAYER) 3391 vop2_set_cluster_win(state, splice_win_data); 3392 else 3393 vop2_set_smart_win(state, splice_win_data); 3394 } else { 3395 printf("ERROR: splice mode is unsupported by plane %s\n", 3396 get_plane_name(primary_plane_id, plane_name)); 3397 return -EINVAL; 3398 } 3399 } 3400 3401 if (win_data->type == CLUSTER_LAYER) 3402 vop2_set_cluster_win(state, win_data); 3403 else 3404 vop2_set_smart_win(state, win_data); 3405 3406 printf("VOP VP%d enable %s[%dx%d->%dx%d@%dx%d] fmt[%d] addr[0x%x]\n", 3407 cstate->crtc_id, get_plane_name(primary_plane_id, plane_name), 3408 cstate->src_rect.w, cstate->src_rect.h, cstate->crtc_rect.w, cstate->crtc_rect.h, 3409 cstate->crtc_rect.x, cstate->crtc_rect.y, cstate->format, 3410 cstate->dma_addr); 3411 3412 return 0; 3413 } 3414 3415 static int rockchip_vop2_prepare(struct display_state *state) 3416 { 3417 return 0; 3418 } 3419 3420 static void vop2_dsc_cfg_done(struct display_state *state) 3421 { 3422 struct connector_state *conn_state = &state->conn_state; 3423 struct crtc_state *cstate = &state->crtc_state; 3424 struct vop2 *vop2 = cstate->private; 3425 u8 dsc_id = cstate->dsc_id; 3426 u32 ctrl_regs_offset = (dsc_id * 0x30); 3427 3428 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 3429 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE, EN_MASK, 3430 DSC_CFG_DONE_SHIFT, 1, false); 3431 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK, 3432 DSC_CFG_DONE_SHIFT, 1, false); 3433 } else { 3434 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + ctrl_regs_offset, EN_MASK, 3435 DSC_CFG_DONE_SHIFT, 1, false); 3436 } 3437 } 3438 3439 static int rockchip_vop2_enable(struct display_state *state) 3440 { 3441 struct crtc_state *cstate = &state->crtc_state; 3442 struct vop2 *vop2 = cstate->private; 3443 u32 vp_offset = (cstate->crtc_id * 0x100); 3444 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3445 3446 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 3447 STANDBY_EN_SHIFT, 0, false); 3448 3449 if (cstate->splice_mode) 3450 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3451 3452 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3453 3454 if (cstate->dsc_enable) 3455 vop2_dsc_cfg_done(state); 3456 3457 return 0; 3458 } 3459 3460 static int rockchip_vop2_disable(struct display_state *state) 3461 { 3462 struct crtc_state *cstate = &state->crtc_state; 3463 struct vop2 *vop2 = cstate->private; 3464 u32 vp_offset = (cstate->crtc_id * 0x100); 3465 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3466 3467 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 3468 STANDBY_EN_SHIFT, 1, false); 3469 3470 if (cstate->splice_mode) 3471 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3472 3473 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3474 3475 return 0; 3476 } 3477 3478 static int rockchip_vop2_get_cursor_plane(struct display_state *state, u32 plane_mask, int cursor_plane) 3479 { 3480 struct crtc_state *cstate = &state->crtc_state; 3481 struct vop2 *vop2 = cstate->private; 3482 int i = 0; 3483 int correct_cursor_plane = -1; 3484 int plane_type = -1; 3485 3486 if (cursor_plane < 0) 3487 return -1; 3488 3489 if (plane_mask & (1 << cursor_plane)) 3490 return cursor_plane; 3491 3492 /* Get current cursor plane type */ 3493 for (i = 0; i < vop2->data->nr_layers; i++) { 3494 if (vop2->data->plane_table[i].plane_id == cursor_plane) { 3495 plane_type = vop2->data->plane_table[i].plane_type; 3496 break; 3497 } 3498 } 3499 3500 /* Get the other same plane type plane id */ 3501 for (i = 0; i < vop2->data->nr_layers; i++) { 3502 if (vop2->data->plane_table[i].plane_type == plane_type && 3503 vop2->data->plane_table[i].plane_id != cursor_plane) { 3504 correct_cursor_plane = vop2->data->plane_table[i].plane_id; 3505 break; 3506 } 3507 } 3508 3509 /* To check whether the new correct_cursor_plane is attach to current vp */ 3510 if (correct_cursor_plane < 0 || !(plane_mask & (1 << correct_cursor_plane))) { 3511 printf("error: faild to find correct plane as cursor plane\n"); 3512 return -1; 3513 } 3514 3515 printf("vp%d adjust cursor plane from %d to %d\n", 3516 cstate->crtc_id, cursor_plane, correct_cursor_plane); 3517 3518 return correct_cursor_plane; 3519 } 3520 3521 static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) 3522 { 3523 struct crtc_state *cstate = &state->crtc_state; 3524 struct vop2 *vop2 = cstate->private; 3525 ofnode vp_node; 3526 struct device_node *port_parent_node = cstate->ports_node; 3527 static bool vop_fix_dts; 3528 const char *path; 3529 u32 plane_mask = 0; 3530 int vp_id = 0; 3531 int cursor_plane_id = -1; 3532 3533 if (vop_fix_dts) 3534 return 0; 3535 3536 ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) { 3537 path = vp_node.np->full_name; 3538 plane_mask = vop2->vp_plane_mask[vp_id].plane_mask; 3539 3540 if (cstate->crtc->assign_plane) 3541 continue; 3542 cursor_plane_id = rockchip_vop2_get_cursor_plane(state, plane_mask, 3543 cstate->crtc->vps[vp_id].cursor_plane); 3544 printf("vp%d, plane_mask:0x%x, primary-id:%d, curser-id:%d\n", 3545 vp_id, plane_mask, 3546 vop2->vp_plane_mask[vp_id].primary_plane_id, 3547 cursor_plane_id); 3548 3549 do_fixup_by_path_u32(blob, path, "rockchip,plane-mask", 3550 plane_mask, 1); 3551 do_fixup_by_path_u32(blob, path, "rockchip,primary-plane", 3552 vop2->vp_plane_mask[vp_id].primary_plane_id, 1); 3553 if (cursor_plane_id >= 0) 3554 do_fixup_by_path_u32(blob, path, "cursor-win-id", 3555 cursor_plane_id, 1); 3556 vp_id++; 3557 } 3558 3559 vop_fix_dts = true; 3560 3561 return 0; 3562 } 3563 3564 static int rockchip_vop2_check(struct display_state *state) 3565 { 3566 struct crtc_state *cstate = &state->crtc_state; 3567 struct rockchip_crtc *crtc = cstate->crtc; 3568 3569 if (crtc->splice_mode && cstate->crtc_id == crtc->splice_crtc_id) { 3570 printf("WARN: VP%d is busy in splice mode\n", cstate->crtc_id); 3571 return -ENOTSUPP; 3572 } 3573 3574 if (cstate->splice_mode) { 3575 crtc->splice_mode = true; 3576 crtc->splice_crtc_id = cstate->splice_crtc_id; 3577 } 3578 3579 return 0; 3580 } 3581 3582 static int rockchip_vop2_mode_valid(struct display_state *state) 3583 { 3584 struct connector_state *conn_state = &state->conn_state; 3585 struct crtc_state *cstate = &state->crtc_state; 3586 struct drm_display_mode *mode = &conn_state->mode; 3587 struct videomode vm; 3588 3589 drm_display_mode_to_videomode(mode, &vm); 3590 3591 if (vm.hactive < 32 || vm.vactive < 32 || 3592 (vm.hfront_porch * vm.hsync_len * vm.hback_porch * 3593 vm.vfront_porch * vm.vsync_len * vm.vback_porch == 0)) { 3594 printf("ERROR: VP%d: unsupported display timing\n", cstate->crtc_id); 3595 return -EINVAL; 3596 } 3597 3598 return 0; 3599 } 3600 3601 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 3602 3603 static int rockchip_vop2_plane_check(struct display_state *state) 3604 { 3605 struct crtc_state *cstate = &state->crtc_state; 3606 struct vop2 *vop2 = cstate->private; 3607 struct display_rect *src = &cstate->src_rect; 3608 struct display_rect *dst = &cstate->crtc_rect; 3609 struct vop2_win_data *win_data; 3610 int min_scale, max_scale; 3611 int hscale, vscale; 3612 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 3613 3614 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); 3615 if (!win_data) { 3616 printf("ERROR: invalid win id %d\n", primary_plane_id); 3617 return -ENODEV; 3618 } 3619 3620 min_scale = FRAC_16_16(1, win_data->max_downscale_factor); 3621 max_scale = FRAC_16_16(win_data->max_upscale_factor, 1); 3622 3623 hscale = display_rect_calc_hscale(src, dst, min_scale, max_scale); 3624 vscale = display_rect_calc_vscale(src, dst, min_scale, max_scale); 3625 if (hscale < 0 || vscale < 0) { 3626 printf("ERROR: VP%d %s: scale factor is out of range\n", cstate->crtc_id, win_data->name); 3627 return -ERANGE; 3628 } 3629 3630 return 0; 3631 } 3632 static struct vop2_plane_table rk356x_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { 3633 {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, 3634 {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, 3635 {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, 3636 {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, 3637 {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, 3638 {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, 3639 }; 3640 3641 static struct vop2_vp_plane_mask rk356x_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 3642 { /* one display policy */ 3643 {/* main display */ 3644 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3645 .attached_layers_nr = 6, 3646 .attached_layers = { 3647 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0, 3648 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 3649 }, 3650 }, 3651 {/* second display */}, 3652 {/* third display */}, 3653 {/* fourth display */}, 3654 }, 3655 3656 { /* two display policy */ 3657 {/* main display */ 3658 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3659 .attached_layers_nr = 3, 3660 .attached_layers = { 3661 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 3662 }, 3663 }, 3664 3665 {/* second display */ 3666 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 3667 .attached_layers_nr = 3, 3668 .attached_layers = { 3669 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 3670 }, 3671 }, 3672 {/* third display */}, 3673 {/* fourth display */}, 3674 }, 3675 3676 { /* three display policy */ 3677 {/* main display */ 3678 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3679 .attached_layers_nr = 3, 3680 .attached_layers = { 3681 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 3682 }, 3683 }, 3684 3685 {/* second display */ 3686 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 3687 .attached_layers_nr = 2, 3688 .attached_layers = { 3689 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_SMART1 3690 }, 3691 }, 3692 3693 {/* third display */ 3694 .primary_plane_id = ROCKCHIP_VOP2_ESMART1, 3695 .attached_layers_nr = 1, 3696 .attached_layers = { ROCKCHIP_VOP2_ESMART1 }, 3697 }, 3698 3699 {/* fourth display */}, 3700 }, 3701 3702 {/* reserved for four display policy */}, 3703 }; 3704 3705 static struct vop2_win_data rk3568_win_data[6] = { 3706 { 3707 .name = "Cluster0", 3708 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 3709 .type = CLUSTER_LAYER, 3710 .win_sel_port_offset = 0, 3711 .layer_sel_win_id = 0, 3712 .reg_offset = 0, 3713 .max_upscale_factor = 4, 3714 .max_downscale_factor = 4, 3715 }, 3716 3717 { 3718 .name = "Cluster1", 3719 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 3720 .type = CLUSTER_LAYER, 3721 .win_sel_port_offset = 1, 3722 .layer_sel_win_id = 1, 3723 .reg_offset = 0x200, 3724 .max_upscale_factor = 4, 3725 .max_downscale_factor = 4, 3726 }, 3727 3728 { 3729 .name = "Esmart0", 3730 .phys_id = ROCKCHIP_VOP2_ESMART0, 3731 .type = ESMART_LAYER, 3732 .win_sel_port_offset = 4, 3733 .layer_sel_win_id = 2, 3734 .reg_offset = 0, 3735 .max_upscale_factor = 8, 3736 .max_downscale_factor = 8, 3737 }, 3738 3739 { 3740 .name = "Esmart1", 3741 .phys_id = ROCKCHIP_VOP2_ESMART1, 3742 .type = ESMART_LAYER, 3743 .win_sel_port_offset = 5, 3744 .layer_sel_win_id = 6, 3745 .reg_offset = 0x200, 3746 .max_upscale_factor = 8, 3747 .max_downscale_factor = 8, 3748 }, 3749 3750 { 3751 .name = "Smart0", 3752 .phys_id = ROCKCHIP_VOP2_SMART0, 3753 .type = SMART_LAYER, 3754 .win_sel_port_offset = 6, 3755 .layer_sel_win_id = 3, 3756 .reg_offset = 0x400, 3757 .max_upscale_factor = 8, 3758 .max_downscale_factor = 8, 3759 }, 3760 3761 { 3762 .name = "Smart1", 3763 .phys_id = ROCKCHIP_VOP2_SMART1, 3764 .type = SMART_LAYER, 3765 .win_sel_port_offset = 7, 3766 .layer_sel_win_id = 7, 3767 .reg_offset = 0x600, 3768 .max_upscale_factor = 8, 3769 .max_downscale_factor = 8, 3770 }, 3771 }; 3772 3773 static struct vop2_vp_data rk3568_vp_data[3] = { 3774 { 3775 .feature = VOP_FEATURE_OUTPUT_10BIT, 3776 .pre_scan_max_dly = 42, 3777 .max_output = {4096, 2304}, 3778 }, 3779 { 3780 .feature = 0, 3781 .pre_scan_max_dly = 40, 3782 .max_output = {2048, 1536}, 3783 }, 3784 { 3785 .feature = 0, 3786 .pre_scan_max_dly = 40, 3787 .max_output = {1920, 1080}, 3788 }, 3789 }; 3790 3791 const struct vop2_data rk3568_vop = { 3792 .version = VOP_VERSION_RK3568, 3793 .nr_vps = 3, 3794 .vp_data = rk3568_vp_data, 3795 .win_data = rk3568_win_data, 3796 .plane_mask = rk356x_vp_plane_mask[0], 3797 .plane_table = rk356x_plane_table, 3798 .nr_layers = 6, 3799 .nr_mixers = 5, 3800 .nr_gammas = 1, 3801 }; 3802 3803 static struct vop2_plane_table rk3588_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { 3804 {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, 3805 {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, 3806 {ROCKCHIP_VOP2_CLUSTER2, CLUSTER_LAYER}, 3807 {ROCKCHIP_VOP2_CLUSTER3, CLUSTER_LAYER}, 3808 {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, 3809 {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, 3810 {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER}, 3811 {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER}, 3812 }; 3813 3814 static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 3815 { /* one display policy */ 3816 {/* main display */ 3817 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3818 .attached_layers_nr = 8, 3819 .attached_layers = { 3820 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART2, 3821 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART3, 3822 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3 3823 }, 3824 }, 3825 {/* second display */}, 3826 {/* third display */}, 3827 {/* fourth display */}, 3828 }, 3829 3830 { /* two display policy */ 3831 {/* main display */ 3832 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3833 .attached_layers_nr = 4, 3834 .attached_layers = { 3835 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, 3836 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 3837 }, 3838 }, 3839 3840 {/* second display */ 3841 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3842 .attached_layers_nr = 4, 3843 .attached_layers = { 3844 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2, 3845 ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 3846 }, 3847 }, 3848 {/* third display */}, 3849 {/* fourth display */}, 3850 }, 3851 3852 { /* three display policy */ 3853 {/* main display */ 3854 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3855 .attached_layers_nr = 3, 3856 .attached_layers = { 3857 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART0 3858 }, 3859 }, 3860 3861 {/* second display */ 3862 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3863 .attached_layers_nr = 3, 3864 .attached_layers = { 3865 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART1 3866 }, 3867 }, 3868 3869 {/* third display */ 3870 .primary_plane_id = ROCKCHIP_VOP2_ESMART2, 3871 .attached_layers_nr = 2, 3872 .attached_layers = { ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 }, 3873 }, 3874 3875 {/* fourth display */}, 3876 }, 3877 3878 { /* four display policy */ 3879 {/* main display */ 3880 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3881 .attached_layers_nr = 2, 3882 .attached_layers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0 }, 3883 }, 3884 3885 {/* second display */ 3886 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER1, 3887 .attached_layers_nr = 2, 3888 .attached_layers = { ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 }, 3889 }, 3890 3891 {/* third display */ 3892 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3893 .attached_layers_nr = 2, 3894 .attached_layers = { ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 }, 3895 }, 3896 3897 {/* fourth display */ 3898 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER3, 3899 .attached_layers_nr = 2, 3900 .attached_layers = { ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 }, 3901 }, 3902 }, 3903 3904 }; 3905 3906 static struct vop2_win_data rk3588_win_data[8] = { 3907 { 3908 .name = "Cluster0", 3909 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 3910 .splice_win_id = ROCKCHIP_VOP2_CLUSTER1, 3911 .type = CLUSTER_LAYER, 3912 .win_sel_port_offset = 0, 3913 .layer_sel_win_id = 0, 3914 .reg_offset = 0, 3915 .axi_id = 0, 3916 .axi_yrgb_id = 2, 3917 .axi_uv_id = 3, 3918 .pd_id = VOP2_PD_CLUSTER0, 3919 .max_upscale_factor = 4, 3920 .max_downscale_factor = 4, 3921 }, 3922 3923 { 3924 .name = "Cluster1", 3925 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 3926 .type = CLUSTER_LAYER, 3927 .win_sel_port_offset = 1, 3928 .layer_sel_win_id = 1, 3929 .reg_offset = 0x200, 3930 .axi_id = 0, 3931 .axi_yrgb_id = 6, 3932 .axi_uv_id = 7, 3933 .pd_id = VOP2_PD_CLUSTER1, 3934 .max_upscale_factor = 4, 3935 .max_downscale_factor = 4, 3936 }, 3937 3938 { 3939 .name = "Cluster2", 3940 .phys_id = ROCKCHIP_VOP2_CLUSTER2, 3941 .splice_win_id = ROCKCHIP_VOP2_CLUSTER3, 3942 .type = CLUSTER_LAYER, 3943 .win_sel_port_offset = 2, 3944 .layer_sel_win_id = 4, 3945 .reg_offset = 0x400, 3946 .axi_id = 1, 3947 .axi_yrgb_id = 2, 3948 .axi_uv_id = 3, 3949 .pd_id = VOP2_PD_CLUSTER2, 3950 .max_upscale_factor = 4, 3951 .max_downscale_factor = 4, 3952 }, 3953 3954 { 3955 .name = "Cluster3", 3956 .phys_id = ROCKCHIP_VOP2_CLUSTER3, 3957 .type = CLUSTER_LAYER, 3958 .win_sel_port_offset = 3, 3959 .layer_sel_win_id = 5, 3960 .reg_offset = 0x600, 3961 .axi_id = 1, 3962 .axi_yrgb_id = 6, 3963 .axi_uv_id = 7, 3964 .pd_id = VOP2_PD_CLUSTER3, 3965 .max_upscale_factor = 4, 3966 .max_downscale_factor = 4, 3967 }, 3968 3969 { 3970 .name = "Esmart0", 3971 .phys_id = ROCKCHIP_VOP2_ESMART0, 3972 .splice_win_id = ROCKCHIP_VOP2_ESMART1, 3973 .type = ESMART_LAYER, 3974 .win_sel_port_offset = 4, 3975 .layer_sel_win_id = 2, 3976 .reg_offset = 0, 3977 .axi_id = 0, 3978 .axi_yrgb_id = 0x0a, 3979 .axi_uv_id = 0x0b, 3980 .max_upscale_factor = 8, 3981 .max_downscale_factor = 8, 3982 }, 3983 3984 { 3985 .name = "Esmart1", 3986 .phys_id = ROCKCHIP_VOP2_ESMART1, 3987 .type = ESMART_LAYER, 3988 .win_sel_port_offset = 5, 3989 .layer_sel_win_id = 3, 3990 .reg_offset = 0x200, 3991 .axi_id = 0, 3992 .axi_yrgb_id = 0x0c, 3993 .axi_uv_id = 0x0d, 3994 .pd_id = VOP2_PD_ESMART, 3995 .max_upscale_factor = 8, 3996 .max_downscale_factor = 8, 3997 }, 3998 3999 { 4000 .name = "Esmart2", 4001 .phys_id = ROCKCHIP_VOP2_ESMART2, 4002 .splice_win_id = ROCKCHIP_VOP2_ESMART3, 4003 .type = ESMART_LAYER, 4004 .win_sel_port_offset = 6, 4005 .layer_sel_win_id = 6, 4006 .reg_offset = 0x400, 4007 .axi_id = 1, 4008 .axi_yrgb_id = 0x0a, 4009 .axi_uv_id = 0x0b, 4010 .pd_id = VOP2_PD_ESMART, 4011 .max_upscale_factor = 8, 4012 .max_downscale_factor = 8, 4013 }, 4014 4015 { 4016 .name = "Esmart3", 4017 .phys_id = ROCKCHIP_VOP2_ESMART3, 4018 .type = ESMART_LAYER, 4019 .win_sel_port_offset = 7, 4020 .layer_sel_win_id = 7, 4021 .reg_offset = 0x600, 4022 .axi_id = 1, 4023 .axi_yrgb_id = 0x0c, 4024 .axi_uv_id = 0x0d, 4025 .pd_id = VOP2_PD_ESMART, 4026 .max_upscale_factor = 8, 4027 .max_downscale_factor = 8, 4028 }, 4029 }; 4030 4031 static struct dsc_error_info dsc_ecw[] = { 4032 {0x00000000, "no error detected by DSC encoder"}, 4033 {0x0030ffff, "bits per component error"}, 4034 {0x0040ffff, "multiple mode error"}, 4035 {0x0050ffff, "line buffer depth error"}, 4036 {0x0060ffff, "minor version error"}, 4037 {0x0070ffff, "picture height error"}, 4038 {0x0080ffff, "picture width error"}, 4039 {0x0090ffff, "number of slices error"}, 4040 {0x00c0ffff, "slice height Error "}, 4041 {0x00d0ffff, "slice width error"}, 4042 {0x00e0ffff, "second line BPG offset error"}, 4043 {0x00f0ffff, "non second line BPG offset error"}, 4044 {0x0100ffff, "PPS ID error"}, 4045 {0x0110ffff, "bits per pixel (BPP) Error"}, 4046 {0x0120ffff, "buffer flow error"}, /* dsc_buffer_flow */ 4047 4048 {0x01510001, "slice 0 RC buffer model overflow error"}, 4049 {0x01510002, "slice 1 RC buffer model overflow error"}, 4050 {0x01510004, "slice 2 RC buffer model overflow error"}, 4051 {0x01510008, "slice 3 RC buffer model overflow error"}, 4052 {0x01510010, "slice 4 RC buffer model overflow error"}, 4053 {0x01510020, "slice 5 RC buffer model overflow error"}, 4054 {0x01510040, "slice 6 RC buffer model overflow error"}, 4055 {0x01510080, "slice 7 RC buffer model overflow error"}, 4056 4057 {0x01610001, "slice 0 RC buffer model underflow error"}, 4058 {0x01610002, "slice 1 RC buffer model underflow error"}, 4059 {0x01610004, "slice 2 RC buffer model underflow error"}, 4060 {0x01610008, "slice 3 RC buffer model underflow error"}, 4061 {0x01610010, "slice 4 RC buffer model underflow error"}, 4062 {0x01610020, "slice 5 RC buffer model underflow error"}, 4063 {0x01610040, "slice 6 RC buffer model underflow error"}, 4064 {0x01610080, "slice 7 RC buffer model underflow error"}, 4065 4066 {0xffffffff, "unsuccessful RESET cycle status"}, 4067 {0x00a0ffff, "ICH full error precision settings error"}, 4068 {0x0020ffff, "native mode"}, 4069 }; 4070 4071 static struct dsc_error_info dsc_buffer_flow[] = { 4072 {0x00000000, "rate buffer status"}, 4073 {0x00000001, "line buffer status"}, 4074 {0x00000002, "decoder model status"}, 4075 {0x00000003, "pixel buffer status"}, 4076 {0x00000004, "balance fifo buffer status"}, 4077 {0x00000005, "syntax element fifo status"}, 4078 }; 4079 4080 static struct vop2_dsc_data rk3588_dsc_data[] = { 4081 { 4082 .id = ROCKCHIP_VOP2_DSC_8K, 4083 .pd_id = VOP2_PD_DSC_8K, 4084 .max_slice_num = 8, 4085 .max_linebuf_depth = 11, 4086 .min_bits_per_pixel = 8, 4087 .dsc_txp_clk_src_name = "dsc_8k_txp_clk_src", 4088 .dsc_txp_clk_name = "dsc_8k_txp_clk", 4089 .dsc_pxl_clk_name = "dsc_8k_pxl_clk", 4090 .dsc_cds_clk_name = "dsc_8k_cds_clk", 4091 }, 4092 4093 { 4094 .id = ROCKCHIP_VOP2_DSC_4K, 4095 .pd_id = VOP2_PD_DSC_4K, 4096 .max_slice_num = 2, 4097 .max_linebuf_depth = 11, 4098 .min_bits_per_pixel = 8, 4099 .dsc_txp_clk_src_name = "dsc_4k_txp_clk_src", 4100 .dsc_txp_clk_name = "dsc_4k_txp_clk", 4101 .dsc_pxl_clk_name = "dsc_4k_pxl_clk", 4102 .dsc_cds_clk_name = "dsc_4k_cds_clk", 4103 }, 4104 }; 4105 4106 static struct vop2_vp_data rk3588_vp_data[4] = { 4107 { 4108 .splice_vp_id = 1, 4109 .feature = VOP_FEATURE_OUTPUT_10BIT, 4110 .pre_scan_max_dly = 54, 4111 .max_dclk = 600000, 4112 .max_output = {7680, 4320}, 4113 }, 4114 { 4115 .feature = VOP_FEATURE_OUTPUT_10BIT, 4116 .pre_scan_max_dly = 54, 4117 .max_dclk = 600000, 4118 .max_output = {4096, 2304}, 4119 }, 4120 { 4121 .feature = VOP_FEATURE_OUTPUT_10BIT, 4122 .pre_scan_max_dly = 52, 4123 .max_dclk = 600000, 4124 .max_output = {4096, 2304}, 4125 }, 4126 { 4127 .feature = 0, 4128 .pre_scan_max_dly = 52, 4129 .max_dclk = 200000, 4130 .max_output = {1920, 1080}, 4131 }, 4132 }; 4133 4134 static struct vop2_power_domain_data rk3588_vop_pd_data[] = { 4135 { 4136 .id = VOP2_PD_CLUSTER0, 4137 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER0), 4138 }, 4139 { 4140 .id = VOP2_PD_CLUSTER1, 4141 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER1), 4142 .parent_id = VOP2_PD_CLUSTER0, 4143 }, 4144 { 4145 .id = VOP2_PD_CLUSTER2, 4146 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER2), 4147 .parent_id = VOP2_PD_CLUSTER0, 4148 }, 4149 { 4150 .id = VOP2_PD_CLUSTER3, 4151 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER3), 4152 .parent_id = VOP2_PD_CLUSTER0, 4153 }, 4154 { 4155 .id = VOP2_PD_ESMART, 4156 .module_id_mask = BIT(ROCKCHIP_VOP2_ESMART1) | 4157 BIT(ROCKCHIP_VOP2_ESMART2) | 4158 BIT(ROCKCHIP_VOP2_ESMART3), 4159 }, 4160 { 4161 .id = VOP2_PD_DSC_8K, 4162 .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_8K), 4163 }, 4164 { 4165 .id = VOP2_PD_DSC_4K, 4166 .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_4K), 4167 }, 4168 }; 4169 4170 const struct vop2_data rk3588_vop = { 4171 .version = VOP_VERSION_RK3588, 4172 .nr_vps = 4, 4173 .vp_data = rk3588_vp_data, 4174 .win_data = rk3588_win_data, 4175 .plane_mask = rk3588_vp_plane_mask[0], 4176 .plane_table = rk3588_plane_table, 4177 .pd = rk3588_vop_pd_data, 4178 .dsc = rk3588_dsc_data, 4179 .dsc_error_ecw = dsc_ecw, 4180 .dsc_error_buffer_flow = dsc_buffer_flow, 4181 .nr_layers = 8, 4182 .nr_mixers = 7, 4183 .nr_gammas = 4, 4184 .nr_pd = ARRAY_SIZE(rk3588_vop_pd_data), 4185 .nr_dscs = 2, 4186 .nr_dsc_ecw = ARRAY_SIZE(dsc_ecw), 4187 .nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow), 4188 }; 4189 4190 const struct rockchip_crtc_funcs rockchip_vop2_funcs = { 4191 .preinit = rockchip_vop2_preinit, 4192 .prepare = rockchip_vop2_prepare, 4193 .init = rockchip_vop2_init, 4194 .set_plane = rockchip_vop2_set_plane, 4195 .enable = rockchip_vop2_enable, 4196 .disable = rockchip_vop2_disable, 4197 .fixup_dts = rockchip_vop2_fixup_dts, 4198 .check = rockchip_vop2_check, 4199 .mode_valid = rockchip_vop2_mode_valid, 4200 .plane_check = rockchip_vop2_plane_check, 4201 }; 4202